CN103794496A - Method for overgrowing germanium silicon acting as source and drain electrode base material on semiconductor silicon substrate - Google Patents
Method for overgrowing germanium silicon acting as source and drain electrode base material on semiconductor silicon substrate Download PDFInfo
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- CN103794496A CN103794496A CN201210419410.0A CN201210419410A CN103794496A CN 103794496 A CN103794496 A CN 103794496A CN 201210419410 A CN201210419410 A CN 201210419410A CN 103794496 A CN103794496 A CN 103794496A
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- silicon substrate
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 49
- 239000010703 silicon Substances 0.000 title claims abstract description 49
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 239000000758 substrate Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000000463 material Substances 0.000 title claims abstract description 17
- 238000001312 dry etching Methods 0.000 claims abstract description 19
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 7
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 7
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 7
- 239000000428 dust Substances 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000003595 mist Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010277 boron hydride Inorganic materials 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 8
- 238000004140 cleaning Methods 0.000 abstract 2
- 208000012868 Overgrowth Diseases 0.000 abstract 1
- 239000003292 glue Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000006378 damage Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a method for overgrowing germanium silicon acting as source and drain electrode base material on a semiconductor silicon substrate. According to the method, after a "sigma"-shaped recessed structure acting as source and drain electrodes is formed in the semiconductor silicon substrate, a layer of oxidation mat is grown on the surface of the "sigma"-shaped recessed structure acting as the source and drain electrodes in a high-temperature way before pre-cleaning, and then the oxidation mat is removed via pre-cleaning. In the process, silicon on the surface of the "sigma"-shaped recessed structure acting as the source and drain electrodes is crystallized, pits on the surface of a "bow"-shaped recessed structure 203 formed by adopting dry etching are filled so that the "sigma"-shaped recessed structure acting as the source and drain electrodes is enabled to be smooth. Germanium silicon overgrowth is performed on the smooth "sigma"-shaped recessed structure acting as the source and drain electrodes so that a defect of stacking does not appear and quality of the overgrown germanium silicon is enhanced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of growing nonparasitically upon another plant as the method for the germanium silicon of source-drain electrode base material on semiconductor silicon substrate.
Background technology
Along with the development of semiconductor technology, germanium silicon is embedded into the source-drain electrode base material as PMOS pipe in semiconductor silicon substrate, be widely used.On semiconductor silicon substrate, grow nonparasitically upon another plant and as the process of the germanium of source-drain electrode base material be: first step, on semiconductor silicon substrate, make grid and formed grid curb wall; Second step forms respectively source electrode groove and drain trenches in the semiconductor silicon substrate on grid and grid curb wall both sides, source electrode groove and drain trenches be shaped as " ∑ " shape; Third step, the germanium silicon material of growing nonparasitically upon another plant in formed source electrode groove and drain trenches.
Particularly, Fig. 1 is that prior art is grown nonparasitically upon another plant as the method flow diagram of the germanium silicon of source-drain electrode base material on semiconductor silicon substrate, on semiconductor silicon substrate, grow nonparasitically upon another plant as the cross-sectional view of the germanium silicon process of source-drain electrode base material in conjunction with the prior art shown in Fig. 2 a～2d, be elaborated:
In this step, the mode of dry etching is: at semiconductor silicon substrate 200, grid 201 and grid curb wall 202 surface-coated photoresistance glue, patterning photoresistance glue, make photoresistance glue cover semiconductor silicon substrate 200, grid 201 and the grid curb wall 202 except reserved source drain region, take the photoresistance glue of patterning as mask, dry etching semiconductor silicon deposition 200;
In this step, owing to adopting dry etching mode, " bow " shape recessed structures 203 forming is by dry etching ion dam age;
In this step, adopt TMAH to carry out wet etching, can remove the photoresistance glue being patterned simultaneously;
In this step, can adopt dilution hydrogen fluoride (DHF) to carry out prerinse;
Just formed the germanium silicon base of source-drain electrode according to the step of Fig. 1, wherein, while adopting step 105 to grow nonparasitically upon another plant germanium silicon 205, because carry out on the surface of growing nonparasitically upon another plant in " ∑ " shape recessed structures 204, so its smooth surface degree is very important to the quality of the germanium silicon 254 of growing nonparasitically upon another plant.Owing to adopting dry etching when the step 102, can damage " bow " shape recessed structures 203 forming, cause formed " bow " shape recessed structures 203 surfaces to occur pit, in follow-up formation " ∑ " shape recessed structures 204 and prerinse process, all cannot make smooth surface, so grow nonparasitically upon another plant in process in step 105, can only carry out in " ∑ " shape recessed structures 204 with rough surface, this can affect the quality of the germanium silicon 205 of growing nonparasitically upon another plant, as shown in Figure 3, Fig. 3 is the cross-sectional view of the source-drain electrode germanium silicon base of prior art formation, as shown in the figure, when the source-drain electrode germanium silicon base forming is grown nonparasitically upon another plant at dry etching damage place, there will be stacking defect.The performance such as such as stress of this germanium silicon 205 that can make to grow nonparasitically upon another plant reduces, and finally makes the semiconductor device failure forming.
Summary of the invention
In view of this, the invention provides a kind of growing nonparasitically upon another plant as the method for the germanium silicon of source-drain electrode base material on semiconductor silicon substrate, the method, before the source-drain electrode germanium silicon base of growing nonparasitically upon another plant, makes " ∑ " shape recessed structures surface smoothing as source-drain electrode in semiconductor silicon substrate.
Technical scheme of the present invention is achieved in that
On semiconductor silicon substrate, grow nonparasitically upon another plant as a method for the germanium silicon of source-drain electrode base material, the method comprises:
On semiconductor silicon substrate, make the utmost point and grid curb wall, adopted dry etching grid and grid curb wall 2 both sides, in the semiconductor silicon substrate on grid and grid curb wall both sides, formed " bow " shape recessed structures;
Use tetramethyl ammonium hydroxide TMAH wet etching, make " bow " shape recessed structures become " ∑ " shape recessed structures;
After " ∑ " shape recessed structures surface high-temp growth oxide pad, prerinse;
The germanium silicon of growing nonparasitically upon another plant in " ∑ " shape recessed structures, forms source-drain electrode germanium silicon base.
Described high growth temperature oxide pad adopts rapid thermal oxidation RTO mode, spike annealing spike anneal mode or high temperature furnace furnace mode of oxidizing.
When described employing RTO mode or spike anneal mode, adopt the mist growth oxide pad of oxygen and nitrogen.
The temperature range of described high growth temperature oxide pad is 700 degrees Celsius～1100 degrees Celsius.
The growth thickness of described high growth temperature oxide pad is 1 dust～30 dust.
The temperature that the described germanium silicon of growing nonparasitically upon another plant adopts is 500 degrees Celsius～800 degrees Celsius, hold in the palm～100 holders of the pressure 1 of employing, and the gas of employing is silane SiH
4, hydrogen chloride HCI, boron hydride B
2h
6, germne GeH
4with hydrogen H
2, SiH wherein
4, GeH
4with HCI and B
2h
6the flow of mist be 1～1000 milliliter per minute, the flow of hydrogen be 0.1～50 milliliter per minute.
The temperature that the described germanium silicon of growing nonparasitically upon another plant adopts is 500 degrees Celsius～800 degrees Celsius, hold in the palm～100 holders of the pressure 1 of employing, and the gas of employing is SiH
2cI
2, B
2h
6and H
2.
Can find out from such scheme, the method that the present invention adopts is forming in semiconductor silicon substrate after " ∑ " shape recessed structures as source-drain electrode, before prerinse, in " ∑ " shape recessed structures surface high-temp growth one deck oxide pad as source-drain electrode, carry out again prerinse and remove this oxide pad, in this process, there is crystallization in the silicon as " ∑ " shape recessed structures surface of source-drain electrode, fill the pit that adopts " bow " shape recessed structures 203 surfaces that dry etching forms, make as " ∑ " shape recessed structures of source-drain electrode level and smooth, carrying out germanium silicon in this level and smooth " ∑ " shape recessed structures as source-drain electrode grows nonparasitically upon another plant, there will not be stacking defect, improve the quality of the germanium silicon of growing nonparasitically upon another plant.Therefore, method provided by the invention, before the source-drain electrode germanium silicon base of growing nonparasitically upon another plant, makes " ∑ " shape recessed structures surface smoothing as source-drain electrode in semiconductor silicon substrate.
Accompanying drawing explanation
Fig. 1 is that prior art is grown nonparasitically upon another plant as the method flow diagram of the germanium silicon of source-drain electrode base material on semiconductor silicon substrate;
Fig. 2 a～2d is that prior art is grown nonparasitically upon another plant as the cross-sectional view of the germanium silicon process of source-drain electrode base material on semiconductor silicon substrate;
Fig. 3 is the cross-sectional view of the source-drain electrode germanium silicon base of prior art formation;
Fig. 4 is provided by the invention growing nonparasitically upon another plant on semiconductor silicon substrate as the method flow diagram of the germanium silicon of source-drain electrode base material;
Fig. 5 a～5e is provided by the invention growing nonparasitically upon another plant on semiconductor silicon substrate as the cross-sectional view of the germanium silicon process of source-drain electrode base material.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention will be further described.
Can find out from background technology, there is stacking defect in the source-drain electrode germanium silicon base of formation.The performance such as such as stress of germanium silicon of making to grow nonparasitically upon another plant reduces, finally make semiconductor device failure former that form because: " bow " shape recessed structures as source drain region that adopts dry etching damage to form, cause formed " bow " shape recessed structures surface to occur pit, make " ∑ " shape recessed structures air spots as source drain region of follow-up formation sliding, the germanium silicon of growing nonparasitically upon another plant on rough " ∑ " shape recessed structures surface, just there will be stacking defect.
Therefore, the present invention is in order to overcome this defect, after " ∑ " shape recessed structures as source-drain electrode in formation semiconductor silicon substrate, before prerinse, in " ∑ " shape recessed structures surface high-temp growth one deck oxide pad as source-drain electrode, carry out again prerinse and remove this oxide pad, in this process, there is crystallization in the silicon as " ∑ " shape recessed structures surface of source-drain electrode, fill the pit that adopts " bow " shape recessed structures 203 surfaces that dry etching forms, make as " ∑ " shape recessed structures of source-drain electrode level and smooth, carrying out germanium silicon in this level and smooth " ∑ " shape recessed structures as source-drain electrode grows nonparasitically upon another plant, there will not be stacking defect, improve the quality of the germanium silicon of growing nonparasitically upon another plant.
Fig. 4 is provided by the invention growing nonparasitically upon another plant on semiconductor silicon substrate as the method flow diagram of the germanium silicon of source-drain electrode base material, on semiconductor silicon substrate, grow nonparasitically upon another plant as the cross-sectional view of the germanium silicon process of source-drain electrode base material in conjunction with provided by the invention shown in Fig. 5 a～5e, be elaborated:
Step 401, has as shown in Figure 5 a been made grid 201 and grid curb wall 202 on semiconductor silicon substrate 200;
Step 402, as shown in Figure 5 b, adopts dry etching grid 201 and grid curb wall 202 both sides, forms " bow " shape recessed structures 203 in the semiconductor silicon substrate 200 on grid 201 and grid curb wall 202 both sides;
In this step, the mode of dry etching is: at semiconductor silicon substrate 200, grid 201 and grid curb wall 202 surface-coated photoresistance glue, patterning photoresistance glue, make photoresistance glue cover semiconductor silicon substrate 200, grid 201 and the grid curb wall 202 except reserved source drain region, take the photoresistance glue of patterning as mask, dry etching semiconductor silicon deposition 200;
In this step, owing to adopting dry etching mode, " bow " shape recessed structures 203 forming is by dry etching ion dam age;
Step 403, as shown in Figure 5 c, is used TMAH to carry out wet etching, forms " ∑ " shape recessed structures 204 in the semiconductor silicon substrate 200 on grid 201 and grid curb wall 202 both sides;
In this step, adopt TMAH to carry out wet etching, can remove the photoresistance glue being patterned simultaneously;
Step 404, as shown in Fig. 5 d, in the semiconductor silicon substrate 200 on grid 201 and grid curb wall 202 both sides, form " ∑ " shape recessed structures surface high-temp growth one deck oxide pad 206;
In this step, high growth temperature one deck oxide pad 206 can adopt rapid thermal oxidation (RTO) mode, spike annealing (spike anneal) mode or high temperature furnace (furnace) mode of oxidizing to carry out; In the time adopting spike anneal or RTO mode to carry out, can adopt the mist of oxygen and nitrogen to carry out;
In this step, the temperature range of high growth temperature one deck oxide pad is 700 degrees Celsius～1100 degrees Celsius, and the oxidizing gas of employing is oxygen and nitrogen, or is oxygen, and the growth thickness of oxide pad is 1 dust～30 dust;
Step 405, carry out prerinse to form " ∑ " shape recessed structures 204 in the semiconductor silicon substrate 200 on grid 201 and grid curb wall 202 both sides, remove the oxide pad 206 generating;
In this step, can adopt dilution hydrogen fluoride (DHF) to carry out prerinse;
After having passed through step 403 and step 404, the silicon face that forms " ∑ " shape recessed structures 204 produces crystallization, fill step 402 and adopted the pit on " bow " shape recessed structures 203 surfaces that dry etching forms, made as " ∑ " shape recessed structures of source-drain electrode smoothly;
Step 406, as shown in Fig. 5 e, in the semiconductor silicon substrate 200 on grid 201 and grid curb wall 202 both sides, form " ∑ " shape recessed structures 204 germanium silicon 205 of growing nonparasitically upon another plant, form the substrate of source-drain electrode;
In this step, the temperature adopting of growing nonparasitically upon another plant is 500 degrees Celsius～800 degrees Celsius, hold in the palm～100 holders of the pressure 1 of employing, and the gas of employing is silane (SiH
4), hydrogen chloride (HCI), boron hydride (B
2h
6), germne (GeH
4) and hydrogen (H
2), SiH wherein
4, HCI, GeH
4and B
2h
6the flow of mist be 1～1000 milliliter per minute, the flow of hydrogen be 0.1～50 milliliter per minute, wherein, SiH
4can replace with SiH
2cI
2.Adopt above-mentioned steps, can form germanium borosilicate, formed the substrate of source-drain electrode.
Can find out from the final source-drain electrode germanium silicon base forming of Fig. 5 e, not occur stacking defect, improve the quality of the germanium silicon of growing nonparasitically upon another plant.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (7)
1. on semiconductor silicon substrate, grow nonparasitically upon another plant as a method for the germanium silicon of source-drain electrode base material, the method comprises:
On semiconductor silicon substrate, make the utmost point and grid curb wall, adopted dry etching grid and grid curb wall 2 both sides, in the semiconductor silicon substrate on grid and grid curb wall both sides, formed " bow " shape recessed structures;
Use tetramethyl ammonium hydroxide TMAH wet etching, make " bow " shape recessed structures become " ∑ " shape recessed structures;
After " ∑ " shape recessed structures surface high-temp growth oxide pad, prerinse;
The germanium silicon of growing nonparasitically upon another plant in " ∑ " shape recessed structures, forms source-drain electrode germanium silicon base.
2. the method for claim 1, is characterized in that, described high growth temperature oxide pad adopts rapid thermal oxidation RTO mode, spike annealing spike anneal mode or high temperature furnace furnace mode of oxidizing.
3. method as claimed in claim 2, is characterized in that, when described employing RTO mode or spikeanneal mode, adopts the mist growth oxide pad of oxygen and nitrogen.
4. the method for claim 1, is characterized in that, the temperature range of described high growth temperature oxide pad is 700 degrees Celsius～1100 degrees Celsius.
5. the method for claim 1, is characterized in that, the growth thickness of described high growth temperature oxide pad is 1 dust～30 dust.
6. the method for claim 1, is characterized in that, described in the temperature that germanium silicon adopts of growing nonparasitically upon another plant be 500 degrees Celsius～800 degrees Celsius, the pressure 1 of employing holds in the palm～100 holders, the gas of employing is silane SiH
4, hydrogen chloride HCI, boron hydride B
2h
6, germne GeH
4with hydrogen H
2, SiH wherein
4, GeH
4with HCI and B
2h
6the flow of mist be 1～1000 milliliter per minute, the flow of hydrogen be 0.1～50 milliliter per minute.
7. the method for claim 1, is characterized in that, described in the temperature that germanium silicon adopts of growing nonparasitically upon another plant be 500 degrees Celsius～800 degrees Celsius, the pressure 1 of employing holds in the palm～100 holders, the gas of employing is SiH
2cI
2, B
2h
6and H
2.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871902A (en) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | Semiconductor treatment technology and semiconductor device preparation method |
| CN107658227A (en) * | 2017-09-26 | 2018-02-02 | 上海华力微电子有限公司 | The forming method of source/drain and the forming method of semiconductor devices |
| CN109786380A (en) * | 2017-11-10 | 2019-05-21 | 联华电子股份有限公司 | The production method of the extension contact structures of semiconductor storage |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101208786B (en) * | 2005-06-30 | 2010-12-01 | 英特尔公司 | Transistor with improved tip profile and method of manufacture thereof |
| CN102637728A (en) * | 2011-02-14 | 2012-08-15 | 台湾积体电路制造股份有限公司 | Method of manufacturing strained source/drain structures |
-
2012
- 2012-10-29 CN CN201210419410.0A patent/CN103794496A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101208786B (en) * | 2005-06-30 | 2010-12-01 | 英特尔公司 | Transistor with improved tip profile and method of manufacture thereof |
| CN102637728A (en) * | 2011-02-14 | 2012-08-15 | 台湾积体电路制造股份有限公司 | Method of manufacturing strained source/drain structures |
Non-Patent Citations (1)
| Title |
|---|
| 陈媛媛，等: "热氧化方法改善硅干法刻蚀波导的表面粗糙度", 《半导体学报》, vol. 25, no. 11, 30 November 2004 (2004-11-30), pages 1544 - 1548 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871902A (en) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | Semiconductor treatment technology and semiconductor device preparation method |
| CN107658227A (en) * | 2017-09-26 | 2018-02-02 | 上海华力微电子有限公司 | The forming method of source/drain and the forming method of semiconductor devices |
| CN109786380A (en) * | 2017-11-10 | 2019-05-21 | 联华电子股份有限公司 | The production method of the extension contact structures of semiconductor storage |
| CN109786380B (en) * | 2017-11-10 | 2020-11-10 | 联华电子股份有限公司 | Method for manufacturing epitaxial contact structure of semiconductor memory device |
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Application publication date: 20140514 |