CN100442457C - Flank wall making method - Google Patents
Flank wall making method Download PDFInfo
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- CN100442457C CN100442457C CNB2005100285365A CN200510028536A CN100442457C CN 100442457 C CN100442457 C CN 100442457C CN B2005100285365 A CNB2005100285365 A CN B2005100285365A CN 200510028536 A CN200510028536 A CN 200510028536A CN 100442457 C CN100442457 C CN 100442457C
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- side wall
- silicon nitride
- making method
- nitride film
- etching
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Abstract
The invention relates to a method for producing side wall, which comprises: first producing silica film; producing silicon nitride film; then etching the side wall; repeating steps 2 and 3, until obtaining the side wall in D shape and width at 500-800ai. And the invention can obtain ideal shape in the process under 0.13 micro meters.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of flank wall making method.
Background technology
Generally all can use the structure of side wall in the production process of semiconductor below 1 micron, side wall generally is used for around polysilicon gate, prevents that more heavy dose of source leakage injection too consequently may the leakage break-through of generation source near raceway groove.
In the side wall production technology of the general D pattern more than 0.15 micron roughly as shown in Figure 1, at first be with chemical vapour deposition (CVD) (Chemical Vapor Deposition, hereinafter to be referred as CVD) method at silicon face growth layer of silicon dioxide film, and then, carry out the side wall etching again with CVD method one deck silicon nitride film of on silica membrane, growing.The layer of silicon dioxide film of growing up can prevent that hypogenous silicon nitride film is grown directly upon silicon chip surface and the stress defective that causes, and the silicon nitride film of being grown in second step is the chief component as side wall.
Along with the development of semiconductor technology, the live width of semiconductor technology is more and more littler, in the technology below 0.13 micron, if adopt existing processes, will produce many problems.More and more narrow along with distance between the polysilicon lines, the ability that CVD fills silicon nitride can be restricted, and the phenomenon in cavity is arranged in the middle of occurring.Can cause the variation of the whole pattern of side wall after the etching, thereby cause the inefficacy of device.In the technology below 0.13 micron, if adopt existing technology, after the grown silicon nitride film pattern of side wall as shown in Figure 2, the pattern of side wall etching back side wall is as shown in Figure 3.
Summary of the invention
Technical problem to be solved by this invention provides a kind of flank wall making method, is applied in the technology below 0.13 micron, can obtain desirable side wall pattern.
For solving the problems of the technologies described above, a kind of flank wall making method of the present invention may further comprise the steps, and the first step is at the silicon chip surface silicon dioxide thin film growth; Second step, grown silicon nitride film on silica membrane, the thickness of the silicon nitride film of being grown is the 1/2-1/4 of normal growth thickness thickness, i.e. the 200-600 dust; The 3rd step, with excessive dried quarter etching carry out the side wall etching; In the 4th step, repeating step two and three is the side wall of " D " shape of 500-800 dust until obtaining width.
As a kind of flank wall making method of a kind of optimal technical scheme of the present invention, preferably adopt the chemical gaseous phase depositing process silicon dioxide thin film growth in the first step.
As a kind of flank wall making method of the another kind of optimal technical scheme of the present invention, preferably adopt chemical gaseous phase depositing process grown silicon nitride film in second step.
Compare with the chemical-mechanical polishing mathing in the prior art, a kind of flank wall making method of the present invention, after the silicon chip surface silicon dioxide thin film growth, repeat the grown silicon nitride film on silica membrane in second step, and the side wall etching in the 3rd step, make in the technology below 0.13 micron, can obtain desirable side wall pattern.
Description of drawings
Below in conjunction with drawings and Examples the present invention is further described:
Fig. 1 is a kind of flank wall making method process chart of existing technology;
Fig. 2 is the flank wall making method grown silicon nitride film back side wall structure chart of prior art;
Fig. 3 is the flank wall making method side wall etching back side wall structure chart of prior art;
Fig. 4 is the present invention's grown silicon nitride film first time back side wall structure chart;
Fig. 5 carries out the side wall etching back side wall structure chart first time for the present invention;
Fig. 6 is the present invention's grown silicon nitride film second time back side wall structure chart;
Fig. 7 carries out the side wall etching back side wall structure chart second time for the present invention;
Fig. 8 is a kind of flank wall making method flow chart of the present invention.
Embodiment
As shown in Figure 8, a kind of flank wall making method of the present invention may further comprise the steps: may further comprise the steps, the first step is at the silicon chip surface silicon dioxide thin film growth; Second step, grown silicon nitride film on silica membrane, the thickness of the silicon nitride film of being grown is the 1/2-1/4 of normal growth thickness thickness, i.e. the 200-600 dust; The 3rd step, with excessive dried quarter etching carry out the side wall etching; In the 4th step, repeating step two and three is the side wall of " D " shape of 500-800 dust until obtaining width.
Be elaborated below, in order to prevent in CVD method grown silicon nitride, the cavity to occur between the polysilicon lines, formerly with after the CVD method growth layer of silicon dioxide film, and then with CVD method growth one deck silicon nitride film, its thickness is about the 1/2-1/4 of normal growth thickness thickness, i.e. the 200-600 dust.Sidewall structure figure as shown in Figure 4.Carry out anisotropic side wall again and do to carve etching, after increasing etching at some, sidewall structure figure as shown in Figure 5 at excessive dried quarter.Then, clean, after removal produced secondary product owing to etching, with CVD method growth one deck silicon nitride film, its thickness was about the 1/2-1/4 of normal growth thickness thickness, i.e. the 200-600 dust more again.Sidewall structure figure as shown in Figure 6.Repeat top anisotropic side wall again and do the etching at quarter, and then, carry out anisotropic side wall and do the etching at quarter, up to obtaining desirable side wall figure, as shown in Figure 7 up to sidewall structure figure with CVD method growth one deck silicon nitride film.
Claims (3)
1. a flank wall making method is characterized in that, may further comprise the steps, and the first step is at the silicon chip surface silicon dioxide thin film growth; Second step, grown silicon nitride film on silica membrane, the thickness of the silicon nitride film of being grown is the 1/2-1/4 of normal growth thickness thickness, i.e. the 200-600 dust; The 3rd step, with excessive dried quarter etching carry out the side wall etching; In the 4th step, repeating step two and three is " D " shape side wall of 500-800 dust until obtaining width.
2. flank wall making method as claimed in claim 1 is characterized in that, adopts the chemical gaseous phase depositing process silicon dioxide thin film growth in the first step.
3. flank wall making method as claimed in claim 1 is characterized in that, adopts chemical gaseous phase depositing process grown silicon nitride film in second step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100285365A CN100442457C (en) | 2005-08-05 | 2005-08-05 | Flank wall making method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100285365A CN100442457C (en) | 2005-08-05 | 2005-08-05 | Flank wall making method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1909195A CN1909195A (en) | 2007-02-07 |
| CN100442457C true CN100442457C (en) | 2008-12-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005100285365A Active CN100442457C (en) | 2005-08-05 | 2005-08-05 | Flank wall making method |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214575A (en) * | 2010-04-02 | 2011-10-12 | 中芯国际集成电路制造(上海)有限公司 | Making method for MOS (Metal Oxide Semiconductor) transistor |
| CN102723271B (en) * | 2012-06-20 | 2015-03-18 | 上海华力微电子有限公司 | Method for forming silicon dioxide side wall with uniform thickness |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11284062A (en) * | 1998-03-31 | 1999-10-15 | Nec Corp | Manufacturing method of semiconductor device |
| US6165883A (en) * | 1998-11-20 | 2000-12-26 | Kabushiki Kaisha Toshiba | Method for forming multilayer sidewalls on a polymetal stack gate electrode |
| JP2002016134A (en) * | 2000-06-28 | 2002-01-18 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
| JP2004342694A (en) * | 2003-05-13 | 2004-12-02 | Ｆａｓｌ Ｊａｐａｎ 株式会社 | Method of manufacturing semiconductor device |
-
2005
- 2005-08-05 CN CNB2005100285365A patent/CN100442457C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11284062A (en) * | 1998-03-31 | 1999-10-15 | Nec Corp | Manufacturing method of semiconductor device |
| US6165883A (en) * | 1998-11-20 | 2000-12-26 | Kabushiki Kaisha Toshiba | Method for forming multilayer sidewalls on a polymetal stack gate electrode |
| JP2002016134A (en) * | 2000-06-28 | 2002-01-18 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
| JP2004342694A (en) * | 2003-05-13 | 2004-12-02 | Ｆａｓｌ Ｊａｐａｎ 株式会社 | Method of manufacturing semiconductor device |
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| CN1909195A (en) | 2007-02-07 |
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Effective date of registration: 20171214 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206 Shanghai Road, Bridge No. 1188, 718 Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |
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