CN102214575A - Making method for MOS (Metal Oxide Semiconductor) transistor - Google Patents
Making method for MOS (Metal Oxide Semiconductor) transistor Download PDFInfo
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- CN102214575A CN102214575A CN2010101442716A CN201010144271A CN102214575A CN 102214575 A CN102214575 A CN 102214575A CN 2010101442716 A CN2010101442716 A CN 2010101442716A CN 201010144271 A CN201010144271 A CN 201010144271A CN 102214575 A CN102214575 A CN 102214575A
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Abstract
The invention provides a making method for a MOS (Metal Oxide Semiconductor) transistor. The making method comprises the following steps: providing a semiconductor substrate on which a gate structure is formed; forming a liner oxidation layer on the semiconductor substrate and the gate structure; forming a clearance wall dielectric layer on the liner oxidation layer; performing plasma treatment on the clearance wall dielectric layer; and repeating the formation process of the clearance wall dielectric layer and the formation process of the plasma treatment for at least one time until the accumulated thickness of the clearance wall dielectric layer reaches the target thickness. The making method for the MOS transistor provided by the invention reduces the thickness deviation of the MOS transistor clearance walls in different areas of the thickness of the devices on the semiconductor substrate, thus consistency in effective trench lengths of the MOS transistors can be improved and consistency in the performances of the MOS transistors can be further improved.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to the manufacture method of MOS transistor.
Background technology
Integrated circuit is the IC continuous advancement in technology, and the component number that is integrated on the same chip has evolved to present millions of from tens initial hundreds ofs.Performance and the complexity of IC were far from originally and can imagine at present.For the requirement of satisfying complexity and current densities (that is: be integrated into the number of devices of determining in the zone), minimum characteristic size, just " how much live widths " of known device is more and more littler along with the innovation of technology.Nowadays, the minimum feature of MOS transistor is less than 65 nanometers.
Along with constantly reducing of MOS transistor minimum feature, highlight day by day such as short-channel effects such as thermoelectronic effects, become the key factor that influences the MOS transistor performance.Therefore, in order to reduce the influence of described short-channel effect, light dope source region and lightly doped drain are introduced in the transistor arrangement, and be corresponding, and the clearance wall structure that is used for isolating heavy-doped source/drain region and grid is introduced in transistor simultaneously.
Application number is the formation method that the U.S. patent documents of US6686232 promptly discloses a kind of MOS transistor clearance wall structure, and described clearance wall structure adopts the composite construction of cushion oxide layer and clearance wall dielectric layer.Described clearance wall dielectric layer is the silicon nitride that plasma enhanced CVD (PECVD) forms, and the cushion oxide layer of described silicon nitride below is as the etching stop layer of dry etching silicon nitride.
Yet, prior art MOS transistor manufacture method is when forming the clearance wall dielectric layer, because the load effect (Pattern Loading Effect) of plasma enhanced CVD technology, the thickness of described clearance wall dielectric layer changes with the device density on the Semiconductor substrate and deviation to some extent: for the higher zone of device density on the Semiconductor substrate, the thickness of described clearance wall dielectric layer is less, and the lower zone of device density, the thickness of described clearance wall dielectric layer is bigger; Clearance wall dielectric layer with the 250 Izod right sides is an example, and the thickness deviation of different components density area may surpass 40 dusts.
The thickness deviation of described clearance wall dielectric layer makes the clearance wall thickness of zones of different MOS transistor produce corresponding deviation, and the thickness deviation of described clearance wall can influence the length of effective channel of MOS transistor.For MOS transistor, length of effective channel is the key factor of its threshold voltage of decision and saturated source-drain current, special MOS transistor for the following channel length of 65 nanometers, its length of effective channel is very little, if deviation in a big way takes place length of effective channel again, must cause the significantly deviation of MOS transistor device performance.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of MOS transistor, and the manufacture method of described MOS transistor has reduced the thickness deviation of the clearance wall of zones of different MOS transistor on the Semiconductor substrate, has improved the consistency of MOS transistor device performance.
For addressing the above problem, the invention provides a kind of manufacture method of MOS transistor, comprising:
Semiconductor substrate is provided, is formed with grid structure on the described Semiconductor substrate;
On described Semiconductor substrate and grid structure, form cushion oxide layer;
On described cushion oxide layer, form the clearance wall dielectric layer;
Described clearance wall dielectric layer is carried out plasma treatment;
Repeat described clearance wall dielectric layer and form technology and plasma-treating technology at least 1 time, reach target thickness until the cumulative thickness of described clearance wall dielectric layer.
Optionally, described clearance wall dielectric layer is a silicon nitride, and using plasma chemical gas-phase deposition enhanced method forms described silicon nitride, wherein, adopts SiH
4With NH
3As reacting gas, SiH
4With NH
3Flow-rate ratio be 1: 10 to 1: 50; Reaction temperature is set to 400 to 480 degrees centigrade, and reaction pressure is set to 5 to 10 holders, and the radio-frequency power of reaction cavity is set to 50 to 200 watts.
Optionally, described clearance wall dielectric layer is carried out plasma treatment to be comprised, adopt helium, nitrogen or argon gas as reacting gas, gas flow is 5000 to 20000sccm, reaction temperature is set to 400 to 480 degrees centigrade, reaction pressure is set to 5 to 10 holders, and the radio-frequency power of reaction cavity is set to 200 to 500 watts.
Compared with prior art, the present invention has the following advantages:
1. adopt the processing method that forms clearance wall dielectric layer-plasma treatment, reduced the thickness deviation of the MOS transistor clearance wall of zones of different on the Semiconductor substrate, thereby improved the consistency of MOS transistor length of effective channel.
2. the reaction cavity of plasma treatment is same reaction cavity with the reaction cavity that forms the clearance wall dielectric layer, does not need described Semiconductor substrate is taken out from reaction cavity, and it is integrated to be beneficial to technology.
Description of drawings
Fig. 1 is the schematic flow sheet of an embodiment of MOS transistor manufacture method of the present invention;
Fig. 2 to Fig. 6 is the cross-sectional view of an embodiment of MOS transistor manufacture method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, prior art MOS transistor manufacture method is when forming the clearance wall dielectric layer, because the load effect of plasma enhanced CVD, the thickness of described clearance wall dielectric layer changes the process deviation that has greatly with the device density on the Semiconductor substrate, and the thickness deviation of described clearance wall dielectric layer can influence the length of effective channel of MOS transistor, and then influences the consistency of MOS transistor threshold voltage and saturated source-drain current.
The present inventor finds, when carrying out plasma treatment for the dielectric layer on the Semiconductor substrate, can have the etching effect with certain load effect equally.Described plasma treatment is to utilize gas ion that the dielectric layer on the Semiconductor substrate is carried out physical bombardment, thereby realizes the processing mode of etching dielectric layer.For the dielectric layer of zones of different on the Semiconductor substrate, through after the described plasma treatment, the etching depth of dielectric layer is relevant with its position on Semiconductor substrate, and the etching depth of dielectric layer has identical trend with the thickness of dielectric layer deposit.Specifically, for the higher zone of device density on the Semiconductor substrate, the degree of depth that dielectric layer is etched is less, and the lower zone of device density, the degree of depth that dielectric layer is etched is bigger.Therefore, can with the described plasma treatment that has load effect equally on the Semiconductor substrate the load effect of the clearance wall dielectric layer of deposit revise, just can reduce the uneven distribution of clearance wall dielectric layer, thereby improve the consistency of device performance.
Based on above-mentioned principle, the inventor provides following technical proposals, the clearance wall dielectric layer that article on plasma body chemical gas-phase deposition enhanced forms carries out plasma treatment, and the formation clearance wall dielectric layer-plasma treatment cycling by repeatedly, the cumulative thickness of realizing the clearance wall dielectric layer reaches target thickness, thereby realizes the making of clearance wall.
Fig. 1 is the schematic flow sheet of an embodiment of MOS transistor manufacture method of the present invention, comprising:
Execution in step S102 provides Semiconductor substrate, is formed with grid structure on the described Semiconductor substrate;
Execution in step S104 forms cushion oxide layer on described Semiconductor substrate and grid structure;
Execution in step S106 forms the clearance wall dielectric layer on described cushion oxide layer;
Execution in step S108 carries out plasma treatment to described clearance wall dielectric layer.
According to the difference of specific embodiment intermediate gap wall dielectric layer target thickness, repeated execution of steps S106 to S108 at least once reaches target thickness until the cumulative thickness of described clearance wall dielectric layer.
Be described in detail below in conjunction with the manufacture method of accompanying drawing the MOS transistor of the embodiment of the invention.
Fig. 2 to Fig. 6 is the cross-sectional view of an embodiment of MOS transistor manufacture method of the present invention.
As shown in Figure 2, provide Semiconductor substrate 201, be formed with grid structure on the described Semiconductor substrate 201.In one embodiment of the invention, the present invention is used to form MOS transistor, and described grid structure comprises gate dielectric layer 205 and gate electrode 207, wherein, and the silicon oxide layer that described gate dielectric layer 205 forms for thermal oxidation; Described gate electrode 207 is a polysilicon layer.In another embodiment of the present invention, the present invention is used to form flash memory transistor, accordingly, described grid structure is the grid structure that piles up, and comprises successively from bottom to top: dielectric layer and control gate between the grid of gate dielectric layer, floating boom, isolation floating boom and control gate.
Then, described Semiconductor substrate 201 is carried out ion inject, in the Semiconductor substrate 201 of described grid structure 207 both sides, form light dope source region 211 and lightly doped drain 213.
As shown in Figure 3, on described Semiconductor substrate 201 and gate electrode 207, form cushion oxide layer 215.In specific embodiment, described cushion oxide layer 215 forms as pre-reaction material, employing time normal pressure chemical vapor deposition (SACVD) or low-pressure chemical vapor phase deposition (LPCVD) mode with ozone and silicon tetraethyl methane (TEOS); The thickness of described cushion oxide layer 215 is 50 to 200 dusts, and it can be used as the etching stop layer of dry etching silicon nitride, and improves the stress coupling between follow-up clearance wall dielectric layer and the Semiconductor substrate 201.
As shown in Figure 4, on described cushion oxide layer 215, continue to form clearance wall dielectric layer 217.In specific embodiment, described clearance wall dielectric layer is silicon nitride, silica or silicon oxynitride.
For fear of once forming the thickness deviation that clearance wall dielectric layer 217 produces, described clearance wall dielectric layer 217 adopts the mode that repeatedly forms clearance wall dielectric layer-plasma treatment circulation to form.In specific embodiment, the thickness that at every turn forms clearance wall dielectric layer-clearance wall dielectric layer 217 that the plasma treatment circulation forms is 10 to 30 dusts.
For described clearance wall dielectric layer 217 is the situation of silicon nitride, and using plasma chemical gas-phase deposition enhanced method forms described silicon nitride, wherein, adopts SiH
4With NH
3As reacting gas, SiH
4Flow be 10 to 50sccm, SiH
4With NH
3Flow-rate ratio be 1: 50 to 1: 10, preferred, SiH
4Flow be 10 to 50sccm, NH
3Flow be 500 to 1000sccm; Reaction temperature is set to 400 to 480 degrees centigrade, and reaction pressure is set to 5 to 10 holders, and the radio-frequency power of reaction cavity is set to 50 to 200 watts.In specific embodiment, the reaction time that at every turn forms clearance wall dielectric layer 217 was smaller or equal to 4 minutes.
After forming described clearance wall dielectric layer 217, continuation is carried out plasma treatment to described clearance wall dielectric layer 217, adopting helium, nitrogen or argon gas is reacting gas, gas flow is 5000 to 20000sccm, reaction temperature is set to 400 to 480 degrees centigrade, reaction pressure is set to 5 to 10 holders, and the radio-frequency power of reaction cavity is set to 200 to 500 watts.
Because the reacting gas of described plasma treatment is nitrogen or inert gas, its chemical property torpescence, its etch rate to clearance wall dielectric layer 217 is relatively slow, and therefore, the reaction time of described plasma treatment is also longer relatively.In specific embodiment, each clearance wall dielectric layer formation technology is 1: 2 to 1: 5 with the reaction time ratio of plasma-treating technology.
Because the plasma treatment of described clearance wall dielectric layer 217 and the formation of clearance wall dielectric layer 217 have similar load effect, be that clearance wall dielectric layer 217 can be owing to plasma treatment is etched, and the etching depth of clearance wall dielectric layer 217 is relevant with its position on Semiconductor substrate 201: for the clearance wall dielectric layer 217 in the device density upper zone on the Semiconductor substrate 201, its etching depth is less than the clearance wall dielectric layer 217 of device density lower region.The inhomogeneous etching of this clearance wall dielectric layer 217 is just in time offset the inhomogeneities that clearance wall dielectric layer 217 forms, thereby has improved the uniformity of clearance wall dielectric layer 217 on the whole Semiconductor substrate 201.
But, described plasma treatment can have certain attenuate to clearance wall dielectric layer 217, for thickness is the clearance wall dielectric layer 217 of 10 dusts, the thickness that is etched away because of plasma treatment is roughly 1 dust, and described attenuate effect can remedy to increase formation clearance wall dielectric layer-plasma treatment loop number.
For a cyclic process of described formation clearance wall dielectric layer-plasma treatment, the thickness of the clearance wall dielectric layer of its formation is 10 dust to the 30 Izod right sides.Therefore,, need to form the clearance wall dielectric layer of target thickness described clearance wall dielectric layer and then can be used to form the clearance wall structure so through after 10 to 30 circulations if target thickness is 300 dusts.In specific embodiment, the clearance wall medium thickness that adopts the present invention's formation is at 100 to 1000 dusts.
In specific embodiment, described clearance wall dielectric layer using plasma chemical gas-phase deposition enhanced mode forms, and the reaction cavity of described plasma enhanced CVD can be same reaction cavity with the reaction cavity of plasma treatment, therefore, the plasma treatment of this original position has technology integrated level preferably.In addition, integrated for the ease of technology, when carrying out plasma treatment, temperature, pressure in the time of can keeping the temperature, pressure of reaction cavity and formation clearance wall dielectric layer are constant, and for example the reaction temperature of plasma treatment and plasma enhanced CVD is 480 degrees centigrade.This processing mode can be so that do not heat up temperature-fall period between two process steps, reduced the process time and reduced the heat budget of technology.
As shown in Figure 5, through repeatedly forming the cyclic process of clearance wall dielectric layer-plasma treatment, the thickness of clearance wall dielectric layer reaches target thickness, then, described clearance wall dielectric layer of etching and cushion oxide layer 215 form the compound clearance wall construction of being made up of clearance wall 219 and cushion oxide layer 215.Described compound clearance wall construction and gate electrode 207 are as the mask of follow-up heavy doping source region and the injection of heavy doping drain region ion.
Compared with prior art, after the clearance wall dielectric layer formation method that adopts MOS transistor manufacture method of the present invention, the thickness deviation of the clearance wall 219 of zones of different obviously reduces on the Semiconductor substrate 201, with thickness is that the clearance wall of 250 dusts is an example, the thickness deviation of prior art is 40 to 50 dusts, and thickness deviation of the present invention is reduced to 15 to 25 dusts.
As shown in Figure 6, Semiconductor substrate 201 is carried out ion inject, form heavy doping source region 223 and heavy doping drain region 225.Afterwards, carry out annealing in process to activate dopant ion and to recover the lattice damage of Semiconductor substrate 201.In specific embodiment, described annealing in process adopts short annealing to handle (RTA), and peak temperature is 1000 to 1100 degrees centigrade.
After above-mentioned processing step enforcement, form the MOS transistor of the embodiment of the invention.As shown in Figure 6, comprise: Semiconductor substrate 201, gate electrode 207 on the Semiconductor substrate 201, light dope source region 211, lightly doped drain 213, heavy doping source region 223 and heavy doping drain region 215 in described gate electrode 207 semiconductor substrates on two sides 201, and the cushion oxide layer 215 and clearance wall 219 of described gate electrode 207 both sides.
MOS transistor manufacture method of the present invention adopts the processing method of formation clearance wall dielectric layer-plasma treatment repeatedly, reduced the thickness deviation of the MOS transistor clearance wall of device density zones of different on the Semiconductor substrate, thereby improved the consistency of MOS transistor length of effective channel, and then improved the consistency of MOS transistor device performance; Simultaneously, the reaction cavity of described plasma treatment can be same reaction cavity with the reaction cavity that forms the clearance wall dielectric layer, does not need described Semiconductor substrate is taken out from reaction cavity, has improved processing compatibility, and it is integrated to help technology.
Should be appreciated that example herein and embodiment only are exemplary, those skilled in the art can make various modifications and corrigendum under the situation of the spirit and scope of the present invention that do not deviate from the application and claims and limited.
Claims (12)
1. the manufacture method of a MOS transistor is characterized in that, comprising:
Semiconductor substrate is provided, is formed with grid structure on the described Semiconductor substrate;
On described Semiconductor substrate and grid structure, form cushion oxide layer;
On described cushion oxide layer, form the clearance wall dielectric layer;
Described clearance wall dielectric layer is carried out plasma treatment;
Repeat described clearance wall dielectric layer and form technology and plasma-treating technology at least 1 time, reach target thickness until the cumulative thickness of described clearance wall dielectric layer.
2. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, described clearance wall dielectric layer is silicon nitride, silica or silicon oxynitride.
3. the manufacture method of MOS transistor as claimed in claim 2 is characterized in that, described clearance wall dielectric layer is a silicon nitride, and using plasma chemical gas-phase deposition enhanced method forms described silicon nitride, wherein, adopts SiH
4With NH
3As reacting gas, SiH
4With NH
3Flow-rate ratio be 1: 10 to 1: 50; Reaction temperature is set to 400 to 480 degrees centigrade, and reaction pressure is set to 5 to 10 holders, and the radio-frequency power of reaction cavity is set to 50 to 200 watts.
4. the manufacture method of MOS transistor as claimed in claim 3 is characterized in that, SiH
4Flow be 10 to 50sccm, NH
3Flow be 500 to 1000sccm.
5. the manufacture method of MOS transistor as claimed in claim 3, it is characterized in that, described clearance wall dielectric layer is carried out plasma treatment to be comprised, adopt helium, nitrogen or argon gas as reacting gas, gas flow is 5000 to 20000sccm, reaction temperature is set to 400 to 480 degrees centigrade, and reaction pressure is set to 5 to 10 holders, and the radio-frequency power of reaction cavity is set to 200 to 500 watts.
6. the manufacture method of MOS transistor as claimed in claim 5 is characterized in that, forming the reaction cavity of described clearance wall dielectric layer is same reaction cavity with the reaction cavity that described clearance wall dielectric layer is carried out plasma treatment.
7. the manufacture method of MOS transistor as claimed in claim 6 is characterized in that, after the deposit of clearance wall dielectric layer forms, keeps reaction temperature, the reaction pressure of depositing technics constant, only changes radio-frequency power and reacting gas, carries out plasma treatment.
8. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, each clearance wall dielectric layer formation technology is 1: 2 to 1: 5 with the reaction time ratio of plasma-treating technology.
9. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, each forms in clearance wall dielectric layer-plasma treatment cyclic process, and the thickness of the clearance wall dielectric layer of formation is 10 to 30 dusts.
10. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, the target thickness of described clearance wall dielectric layer is 100 to 1000 dusts.
11. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, described grid structure comprises the gate electrode on gate dielectric layer and the gate dielectric layer.
12. the manufacture method of MOS transistor as claimed in claim 1 is characterized in that, described grid structure comprises dielectric layer and control gate between gate dielectric layer, floating boom, grid from bottom to top successively.
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| CN2010101442716A CN102214575A (en) | 2010-04-02 | 2010-04-02 | Making method for MOS (Metal Oxide Semiconductor) transistor |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040092074A1 (en) * | 2002-11-07 | 2004-05-13 | Nanya Technology Corporation | Method of forming source/drain regions in semiconductor devices |
| US20040178419A1 (en) * | 2003-03-12 | 2004-09-16 | Seung-Chul Song | Semiconductor device having a photon absorption layer to prevent plasma damage |
| US20060246669A1 (en) * | 2001-11-29 | 2006-11-02 | Hynix Semiconductor Inc. | Method for fabricating semiconductor devices having dual gate oxide layer |
| CN1909195A (en) * | 2005-08-05 | 2007-02-07 | 上海华虹Nec电子有限公司 | Flank wall making method |
| CN101047182A (en) * | 2006-03-30 | 2007-10-03 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| US20100044806A1 (en) * | 2008-08-21 | 2010-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit metal gate structure and method of fabrication |
| CN101930922A (en) * | 2009-06-26 | 2010-12-29 | 中芯国际集成电路制造(上海)有限公司 | Production method of MOS (Metal Oxide Semiconductor) transistor |
-
2010
- 2010-04-02 CN CN2010101442716A patent/CN102214575A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060246669A1 (en) * | 2001-11-29 | 2006-11-02 | Hynix Semiconductor Inc. | Method for fabricating semiconductor devices having dual gate oxide layer |
| US20040092074A1 (en) * | 2002-11-07 | 2004-05-13 | Nanya Technology Corporation | Method of forming source/drain regions in semiconductor devices |
| US20040178419A1 (en) * | 2003-03-12 | 2004-09-16 | Seung-Chul Song | Semiconductor device having a photon absorption layer to prevent plasma damage |
| CN1909195A (en) * | 2005-08-05 | 2007-02-07 | 上海华虹Nec电子有限公司 | Flank wall making method |
| CN101047182A (en) * | 2006-03-30 | 2007-10-03 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| US20100044806A1 (en) * | 2008-08-21 | 2010-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit metal gate structure and method of fabrication |
| CN101930922A (en) * | 2009-06-26 | 2010-12-29 | 中芯国际集成电路制造(上海)有限公司 | Production method of MOS (Metal Oxide Semiconductor) transistor |
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