CN103646919B - 双大马士革结构的制造方法 - Google Patents

双大马士革结构的制造方法 Download PDF

Info

Publication number
CN103646919B
CN103646919B CN201310630206.8A CN201310630206A CN103646919B CN 103646919 B CN103646919 B CN 103646919B CN 201310630206 A CN201310630206 A CN 201310630206A CN 103646919 B CN103646919 B CN 103646919B
Authority
CN
China
Prior art keywords
layer
plane
manufacture method
double damask
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310630206.8A
Other languages
English (en)
Other versions
CN103646919A (zh
Inventor
吴敏
杨渝书
王一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
Original Assignee
Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201310630206.8A priority Critical patent/CN103646919B/zh
Publication of CN103646919A publication Critical patent/CN103646919A/zh
Application granted granted Critical
Publication of CN103646919B publication Critical patent/CN103646919B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • H01L2221/1015Forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明公开了一种双大马士革结构的制造方法,其包括半导体结构上形成沟槽;形成沟槽两侧的通孔;以金属掩膜层为掩膜,刻蚀沟槽下的部分低介电常数层,形成圆弧型或斜边型斜面,并打开通孔,形成双大马士革结构;以含有CF4的气体并以高偏置功率对具有圆弧型或斜边型斜面的低介电常数层进行刻蚀,形成Z字型斜面。本发明通过预处理形成具有小尺寸斜面的低介电常数层边缘,随后进一步刻蚀以增大斜面尺寸,最终得到大尺寸斜面,本发明提高了双大马士革结构后续沉积能力,并提高了半导体元器件的可靠性性能。

Description

双大马士革结构的制造方法
技术领域
本发明涉及半导体制造领域,尤其涉及一种双大马士革结构的制造方法。
背景技术
随着半导体技术的发展,半导体器件特征尺寸越来越小,半导体后段铜制程取代了铝制程,低介电常数材质(如硅、氧、碳、氢元素组成的SiOCH的黑钻石(blackdiamond,BD)、氮掺杂的碳化硅(NdopedSiC,NDC)等)取代了传统氧化硅成为主流工艺。在铜双大马士革制备工艺中,由于低介电常数材质的多孔率、材质疏松等特性,使其内在击穿强度明显低于传统的氧化硅材质,其可靠性性能明显不及传统氧化硅。因此,对刻蚀低介电常数材质的双大马士革结构提出更高的要求。
研究表明,双大马士革结构的可靠性与斜面(Chamfer)的尺寸和形貌强相关。图1和图2是现有双大马士革结构中斜面的两种基本形貌。图1是圆弧型斜面91,这种刻蚀工艺需要较高的聚合物保护斜面的形貌,使其表面光滑,但所得斜面尺寸比较小,而且不利于后续PVD淀积金属阻挡层(TaN、Ta)和铜籽晶层。图2中的是斜边型斜面92,相对于圆弧型斜面,此种斜面能够获得相对较大的尺寸,且便于后续物理气相沉积(PVD)金属阻挡层(TaN、Ta)和铜籽晶层;但随着特征尺寸的减小,以及对工艺要求的不断提高,此斜面仍不足以完全符合工艺要求,以保证元器件的可靠性性能。
发明内容
为了解决上述现有技术存在的问题,本发明提供了一种具有大尺寸斜面(Chamfer)的双大马士革结构的制造方法,以提高后续物理气相沉积(PVD)金属阻挡层(TaN、Ta)和铜籽晶层的沉积能力,并提高半导体元器件的可靠性性能。
本发明提供一种双大马士革结构的制造方法,其包括以下步骤:
步骤S01,提供一半导体结构,其自下而上依次具有阻挡层、低介电常数层、金属掩膜层和顶层;
步骤S02,在该半导体结构之上依次涂覆第一抗反射层和第一光刻胶,图案化该第一光刻胶,以形成沟槽图形;
步骤S03,依次刻蚀去除该沟槽图形内的第一抗反射层、顶层、金属掩膜层和部分低介电常数层,之后去除该第一光刻胶,形成沟槽;
步骤S04,在步骤S03得到的半导体结构之上涂覆第二抗反射层和第二光刻胶,图形化该第二光刻胶,以形成沟槽两侧的通孔图形;
步骤S05,依次刻蚀去除该通孔图形内的第二抗反射层、顶层、金属掩膜层和部分低介电常数层,之后去除该第二光刻胶,形成沟槽两侧的通孔;
步骤S06,以金属掩膜层为掩膜,刻蚀沟槽下的部分低介电常数层,形成圆弧型或斜边型斜面,并打开通孔,形成双大马士革结构;
步骤S07,以含有CF4的气体并以高偏置功率对具有圆弧型或斜边型斜面的低介电常数层进行刻蚀,形成Z字型斜面。
进一步地,步骤S07中所用的偏置电压的功率为300-500瓦。
进一步地,步骤S07中所用的CF4流量为200-400标准立方厘米/分钟;该偏置电压为2-13MHz;刻蚀反应腔体内的压力为40-100毫托;刻蚀时间为20-40秒。
进一步地,步骤S03、步骤S05和步骤S06的刻蚀介质是含有CXHY的气体。
进一步地,步骤S06中刻蚀介质含有C4F8
进一步地,步骤S06的刻蚀介质还含有O2、N2、Ar。
进一步地,步骤S03中刻蚀介质含有C2H4,步骤S05中刻蚀介质含有C4F8和CH2F2
进一步地,步骤S03的刻蚀介质还含有Cl2、O2、Ar,步骤S05的刻蚀介质还含有N2、Ar。
进一步地,该顶层是二氧化硅、该金属掩膜层是TiN,该低介电常数层是BD、该阻挡层是NDC,它们通过化学气相沉积或物理气相沉积依次沉积,该抗反射层的材质可以是BARC(BottomAnti-ReflectiveCoating,底部抗反射层)。
本发明提出了一种双大马士革结构的制造方法,通过对具有圆弧型或斜边型斜面的低介电常数层以高偏置功率进行刻蚀,形成Z字型斜面,从而增加斜面尺寸。本发明提高了双大马士革结构后续物理气相沉积(PVD)金属阻挡层(TaN、Ta)和铜籽晶层的沉积能力,并提高了半导体元器件的可靠性性能。
附图说明
为能更清楚理解本发明的目的、特点和优点,以下将结合附图对本发明的较佳实施例进行详细描述,其中:
图1是现有双大马士革结构中斜面的第一种基本形貌;
图2是现有双大马士革结构中斜面的第二种基本形貌;
图3a至3g是本发明第一实施例各步骤的结构示意图。
具体实施方式
第一实施例
请参阅图3a至图3g,本实施例的双大马士革结构的制造方法,其包括以下步骤。
步骤S01,提供一半导体结构,其自下而上依次通过化学气相沉积工艺(CVD)沉积NDC阻挡层11、BD低介电常数层12、TiN金属掩膜层13和二氧化硅顶层14,如图3a所示。
步骤S02,在该半导体结构之上依次涂覆第一抗反射层15和第一光刻胶16,图案化该第一光刻胶16,以形成沟槽图形,如图3a所示。
其中,该沟槽图形是朝与纸面相垂直的方向延伸的。
步骤S03,依次刻蚀去除该沟槽图形内的第一抗反射层15、顶层14、金属掩膜层13和10%厚度的低介电常数层12,之后去除该第一光刻胶16,形成沟槽2,如图3b所示。
其中,该沟槽2是朝与纸面相垂直的方向延伸的一段凹形槽。本步骤中,刻蚀介质选用50Cl2/20O2/10C2H4/200Ar(组分中数字代表体积份数,下同)。
步骤S04,在步骤S03得到的半导体结构之上涂覆第二抗反射层17和第二光刻胶18,图形化该第二光刻胶18,以形成沟槽两侧的通孔图形,如图3c所示。
其中,该通孔图形是图3c中从上而下延伸的。
步骤S05,依次刻蚀去除该通孔图形内的第二抗反射层17、顶层14、金属掩膜层13和部分低介电常数层12,保留20%厚度的低介电常数层12,之后去除该第二光刻胶18,形成沟槽两侧的通孔3,如图3d所示,图中虚线为沟槽2的底面。
本步骤中,刻蚀介质选用5C4F8/5CH2F2/300N2/300Ar。
其中,该通孔3是图3d中从上而下延伸的。图3e是沿图3d中A-A方向的剖面图,可以看到,步骤S05之后,沟槽2两侧为通孔3,露出了矩形的低介电常数层121。
步骤S06,以金属掩膜层13为掩膜,刻蚀沟槽2下的部分低介电常数层121,形成圆弧型斜面41,并打开通孔3,形成双大马士革结构,如图3f所示。
本步骤中,刻蚀介质选用50C4F8/25O2/100N2/1000Ar。
步骤S07,以含有CF4的气体并以高偏置功率对具有圆弧型或斜边型斜面的低介电常数层进行刻蚀,形成Z字型斜面42,如图3g所示。
其中,本步骤中所用的偏置电压的功率为400瓦;CF4流量为300标准立方厘米/分钟;该偏置电压为10MHz;刻蚀反应腔体内的压力为80毫托;刻蚀时间为30秒。通过本步骤的刻蚀可以调节圆弧型斜面41的形貌和尺寸,得到Z字型斜面42,具有较圆弧型斜面41更大的尺寸,提高了双大马士革结构后续的沉积能力,从而提高器件的可靠性性能。

Claims (9)

1.一种双大马士革结构的制造方法,其特征在于,其包括以下步骤:
步骤S01,提供一半导体结构,其自下而上依次具有阻挡层、低介电常数层、金属掩膜层和顶层;
步骤S02,在该半导体结构之上依次涂覆第一抗反射层和第一光刻胶,图案化该第一光刻胶,以形成沟槽图形;
步骤S03,依次刻蚀去除该沟槽图形内的第一抗反射层、顶层、金属掩膜层和部分低介电常数层,之后去除该第一光刻胶,形成沟槽;
步骤S04,在步骤S03得到的半导体结构之上涂覆第二抗反射层和第二光刻胶,图形化该第二光刻胶,以形成沟槽两侧的通孔图形;
步骤S05,依次刻蚀去除该通孔图形内的第二抗反射层、顶层、金属掩膜层和部分低介电常数层,之后去除该第二光刻胶,形成沟槽两侧的通孔;
步骤S06,以金属掩膜层为掩膜,刻蚀沟槽下的部分低介电常数层,形成圆弧型或斜边型斜面,并打开通孔,形成双大马士革结构;
步骤S07,以含有CF4的气体并预设偏置电压的功率对具有圆弧型或斜边型斜面的低介电常数层进行刻蚀,形成Z字型斜面。
2.根据权利要求1所述的双大马士革结构的制造方法,其特征在于:步骤S07中所用的偏置电压的功率为300-500瓦。
3.根据权利要求2所述的双大马士革结构的制造方法,其特征在于:步骤S07中所用的CF4流量为200-400标准立方厘米/分钟;该偏置电压的频率为2-13MHz;刻蚀反应腔体内的压力为40-100毫托;刻蚀时间为20-40秒。
4.根据权利要求2所述的双大马士革结构的制造方法,其特征在于:步骤S03、步骤S05和步骤S06中刻蚀介质是含有CXHY的气体。
5.根据权利要求4所述的双大马士革结构的制造方法,其特征在于:步骤S06中刻蚀介质含有C4F8
6.根据权利要求5所述的双大马士革结构的制造方法,其特征在于:步骤S06的刻蚀介质还含有O2、N2、Ar。
7.根据权利要求4所述的双大马士革结构的制造方法,其特征在于:步骤S03中刻蚀介质含有C2H4,步骤S05中刻蚀介质含有C4F8和CH2F2
8.根据权利要求7所述的双大马士革结构的制造方法,其特征在于:步骤S03的刻蚀介质还含有Cl2、O2、Ar,步骤S05的刻蚀介质还含有N2、Ar。
9.根据权利要求1至8任一项所述的双大马士革结构的制造方法,其特征在于:该顶层是二氧化硅、该金属掩膜层是TiN,所述顶层以及金属掩膜层通过化学气相沉积或物理气相沉积依次沉积。
CN201310630206.8A 2013-11-29 2013-11-29 双大马士革结构的制造方法 Active CN103646919B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310630206.8A CN103646919B (zh) 2013-11-29 2013-11-29 双大马士革结构的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310630206.8A CN103646919B (zh) 2013-11-29 2013-11-29 双大马士革结构的制造方法

Publications (2)

Publication Number Publication Date
CN103646919A CN103646919A (zh) 2014-03-19
CN103646919B true CN103646919B (zh) 2016-03-16

Family

ID=50252117

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310630206.8A Active CN103646919B (zh) 2013-11-29 2013-11-29 双大马士革结构的制造方法

Country Status (1)

Country Link
CN (1) CN103646919B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097681A (zh) * 2014-05-06 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN104505367B (zh) * 2014-11-07 2017-08-22 上海华力微电子有限公司 后段铜互连工艺中降低通孔间介质材料的k值的方法
CN108565216B (zh) * 2018-05-31 2020-11-24 上海华力集成电路制造有限公司 双大马士革通孔工艺的返工方法
CN110809367B (zh) * 2019-10-16 2020-11-06 胜宏科技(惠州)股份有限公司 一种采用蚀刻法加工金属基斜边的生产工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543859A (zh) * 2012-02-28 2012-07-04 上海华力微电子有限公司 改善金属互联工艺中多孔介质薄膜密封性的方法
CN102800628A (zh) * 2012-09-11 2012-11-28 上海华力微电子有限公司 防止图形倒塌的双大马士革结构制备方法
CN103165522A (zh) * 2011-12-15 2013-06-19 中芯国际集成电路制造(上海)有限公司 半导体结构及半导体结构的形成方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7262127B2 (en) * 2005-01-21 2007-08-28 Sony Corporation Method for Cu metallization of highly reliable dual damascene structures
US7671362B2 (en) * 2007-12-10 2010-03-02 International Business Machines Corporation Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165522A (zh) * 2011-12-15 2013-06-19 中芯国际集成电路制造(上海)有限公司 半导体结构及半导体结构的形成方法
CN102543859A (zh) * 2012-02-28 2012-07-04 上海华力微电子有限公司 改善金属互联工艺中多孔介质薄膜密封性的方法
CN102800628A (zh) * 2012-09-11 2012-11-28 上海华力微电子有限公司 防止图形倒塌的双大马士革结构制备方法

Also Published As

Publication number Publication date
CN103646919A (zh) 2014-03-19

Similar Documents

Publication Publication Date Title
US9941199B2 (en) Two step metallization formation
US9099400B2 (en) Semiconductor device manufacturing methods
US9607883B2 (en) Trench formation using rounded hard mask
US20170186616A1 (en) Spacers with Rectangular Profile and Methods of Forming the Same
US9040417B2 (en) Semiconductor devices and methods of manufacture thereof
JP2007081113A (ja) 半導体装置の製造方法
CN103646919B (zh) 双大马士革结构的制造方法
US20210217623A1 (en) Semiconductor device and semiconductor device manufacturing method
JP2006352124A (ja) 半導体デバイスおよびその構造体の製造方法
US20140264895A1 (en) Semiconductor Devices and Methods of Manufacture Thereof
US20190393074A1 (en) Barrier layer removal method and semiconductor structure forming method
US9373541B2 (en) Hard mask removal scheme
CN105789111B (zh) 半导体结构的形成方法
KR20150020053A (ko) 측벽층 및 매우 두꺼운 금속층을 갖는 집적회로 및 그 제조 방법
CN103646921B (zh) 双大马士革结构的制造方法
TWI282602B (en) Dual damascene process
CN106971973B (zh) 一种半导体器件及其制造方法、电子装置
JP4224422B2 (ja) プラズマエッチング処理方法
CN104302811A (zh) 全部在一整合蚀刻中的金属硬掩模
TW201737330A (zh) 阻擋層的去除方法和半導體結構的形成方法
WO2016058174A1 (en) Barrier layer removal method and semiconductor structure forming method
JP2006073907A (ja) 半導体装置の製造方法および半導体装置
KR20110071430A (ko) 반도체 소자의 층간 절연막 형성방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant