CN103633143B - 在最外鳍的外侧表面上包括外延生长阻挡物的多鳍finfet器件和相关方法 - Google Patents

在最外鳍的外侧表面上包括外延生长阻挡物的多鳍finfet器件和相关方法 Download PDF

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CN103633143B
CN103633143B CN201310343682.1A CN201310343682A CN103633143B CN 103633143 B CN103633143 B CN 103633143B CN 201310343682 A CN201310343682 A CN 201310343682A CN 103633143 B CN103633143 B CN 103633143B
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finfet device
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CN103633143A (zh
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柳青
P·卡雷
N·劳贝特
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STMicroelectronics lnc USA
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Abstract

一种多鳍FINFET器件可以包括衬底以及从衬底向上延伸并且沿着衬底间隔开的多个半导体鳍。每个半导体鳍可以具有相对的第一和第二端以及在第一端与第二端之间的中间部分，并且多个半导体鳍中的最外鳍可以在其外侧表面上包括外延生长阻挡物。FINFET还可以包括：至少一个栅极，覆盖半导体鳍的中间部分；在半导体鳍之间的多个凸起外延半导体源极区域，与半导体鳍的第一端相邻；以及在半导体鳍之间的多个凸起外延半导体漏极区域，与半导体鳍的第二端相邻。

Description

在最外鳍的外侧表面上包括外延生长阻挡物的 多鳍FINFET器件和相关方法
技术领域
本发明涉及电子器件领域，并且更具体地涉及半导体器件及其相关方法。
背景技术
半导体器件技术继续发展从而提供更高芯片密度和操作频率。鳍型场效应晶体管(FINFET)是用来帮助在维持适当功率消耗预算时提供所需器件缩放的一类晶体管技术。
第2010/0203732号美国专利公开一种FINFET器件和相关方法，其中每个FINFET可以具有亚光刻尺度宽度。该方法包括在位于衬底上的包含半导体的层上面形成具有多个开口的掩模。然后执行成角度离子注入以向包含半导体的层的第一部分引入掺杂物，其中基本上无掺杂物的剩余部分存在于掩模下面。随后对包含半导体的层的基本上无掺杂物的剩余部分选择性去除包含半导体的层的包含掺杂物的第一部分以提供图案。然后向衬底中传送图案以提供具有亚光刻尺度宽度的鳍结构。
另一类FINFET器件是多鳍FINFET。这一器件通常包括具有覆盖鳍的三栅极的多个间隔开的半导体鳍。FINFET的有效栅极宽度2nh，其中n是鳍数目并且h是鳍高度。因此，可以通过使用多个鳍来获得具有更高接通电流的更宽晶体管。然而，更高鳍数目可能造成更复杂的器件结构，这些器件结构可能带来制作挑战。
发明内容
因此鉴于前述背景，本发明的目的是提供一种可靠并且容易制作的多鳍FINFET器件。
根据本发明的这一和其它目的、特征及优点由一种多鳍FINFET器件提供，该多鳍FINFET器件可以包括衬底以及从衬底向上延伸并且沿着衬底间隔开的多个半导体鳍。每个半导体鳍可以具有相对的第一端和第二端以及在第一端与第二端之间的中间部分，并且多个半导体鳍中的最外鳍可以在其外侧表面上包括外延生长阻挡物。FINFET还可以包括：至少一个栅极，覆盖半导体鳍的中间部分；在半导体鳍之间的多个凸起外延半导体源极区域，与半导体鳍的第一端相邻；以及在半导体鳍之间的多个凸起外延半导体漏极区域，与半导体鳍的第二端相邻。这样，可以在生长凸起外延源极和漏极区域期间避免在最外鳍的外侧表面上的外延生长，这可以有利地造成减少的电短接可能性
举例而言，外延生长阻挡物可以包括化合物，化合物包括半导体以及在碳和氟中的至少一项。另外，多个半导体鳍可以例如包括硅。更具体而言，多个半导体鳍可以包括第一组P沟道鳍和从第一组P沟道鳍间隔开的第二组N沟道鳍以限定互补金属氧化物半导体(CMOS)FINFET，并且至少一个栅极可以包括用于第一组P沟道鳍和第二组N沟道鳍中的每个沟道鳍的相应栅极。
该多鳍FINFET器件还可以包括耦合到栅极并且从衬底向上延伸而且从半导体鳍间隔开的栅极接触区域。此外，该多鳍FINFET器件也可以包括：源极接触区域，耦合到多个半导体鳍的第一端；以及漏极接触区域，耦合到多个半导体鳍的第二端。
一种制作多鳍FINFET器件的相关方法可以包括形成从衬底向上延伸并且沿着衬底间隔开的多个半导体鳍，其中每个半导体鳍具有相对第一和第二端以及在第一与第二端之间的中间部分。该方法还可以包括：形成至少一个栅极，至少一个栅极覆盖半导体鳍的中间部分；在多个半导体鳍中的最外鳍的外侧表面上形成外延生长阻挡物；在半导体鳍之间形成与半导体鳍的第一端相邻的多个凸起外延半导体源极区域；并且在半导体鳍之间形成与半导体鳍的第二端相邻的多个凸起外延半导体漏极区域。
附图说明
图1是根据本发明的CMOS多鳍FINFET器件的透视图。
图2A和图2B是分别示出图1的FINFET的鳍形成的侧视和俯视图。
图3A和图3B是分别示出在图1的FINFET的鳍上形成三栅极的侧视和俯视图。
图4是示出用于在图1的FINFET的最外鳍的外侧表面上形成外延生长阻挡物的离子注入步骤的例视图。
图5A和图5B是分别示出图1的FINFET的外延源极和漏极区域形成的侧视和俯视图。
图6是与图2A、图2B、图3A、图3B、图4、图5A和图5B中所示步骤对应的流程图。
具体实施方式
现在下文将参照附图更完全地描述本发明，在附图中示出本发明的优选实施例。然而本发明可以用许多不同形式来体现而不应解释为限于这里阐述的实施例。实际上，提供这些实施例使得本公开内容将透彻而完整并且将向本领域技术人员完全传达本发明的范围。相似标号全篇指代相似单元。
首先参照图1-图5，先描述多鳍FINFET器件30和关联方法方面。在所示示例中，FINFET30是包括NFET和PFET的互补金属氧化物半导体(CMOS)器件。FINFET30可以被配置用于使用以下进一步描述的接触区域来提供各种器件，诸如存储器、逻辑门等。然而应当注意，也可以在不同实施例中使用非CMOS配置(即，个别NFET或者PFET)。
FINFET30示例地包括衬底31，该衬底可以是半导体衬底(例如硅、锗、Si/Ge等)、绝缘体上半导体(SOI)衬底等。另外，用于相应NFET和PFET器件的多个半导体鳍32n、32p从衬底31向上延伸并且沿着衬底被横向间隔开(在图2A、图2B中从左到右)。在图2A至图5B中，NFET在左侧上并且PFET在右侧上。每个半导体鳍32n、32p分别具有相对第一和第二端33a、33b和34a、34b以及在它们之间的相应中间区域35a、35b(在图2B中用虚线指示)。如以下将进一步描述的那样，多个半导体鳍中的最外鳍(即它们的相应一组鳍中的在最左和右侧上的鳍32n、32p)在其外侧表面上包括外延生长阻挡物35n、35p。
FINFET30还示例地包括用于NFET和PFET的相应栅极37n、37p，这些栅极覆盖鳍32n、32p的相应中间部分35a、35b。更具体而言，栅极37n、37p是三栅极结构，每个三栅极结构可以包括绝缘体层和覆盖绝缘体层的电极层。此外，多个凸起外延半导体源极区域38n、38p分别与半导体鳍32n、32p的第一端33a、34a相邻在半导体鳍32n、32p之间延伸。另外，多个凸起外延半导体漏极区域39n、39p与半导体鳍32n、32p的第二端33b、34b相邻在半导体鳍32n、32p之间延伸。FINFET30还示例地包括分别耦合到栅极37n、37p并且从栅极31向上延伸而且从半导体40n、40p间隔开的栅极接触区域40n、40p(图1)。类似地，相应源极接触区域41n、41p耦合到半导体鳍32n、32p的第一端33a、34a，并且相应漏极接触区域42n、42p耦合到半导体鳍32n、32p的第二端33b、34b。
如以上所言，多鳍FINFET有利在于有效栅极宽度是2nh，其中n是鳍数目并且h是鳍高度。因而，可以通过使用多个鳍来获得具有更高接通电流的更宽晶体管。然而在源极/漏极外延生长用来合并鳍32n、32p以降低外部电阻时，外延生长将另外出现于两组鳍之间。也就是说，不仅有外延半导体材料在鳍32n与32p之间的鳍内生长，而且在典型FINFET集成工艺中例如将有在两组鳍之间的鳍间生长。这可能另外成问题，因为它可能引起在NFET与PFET鳍32n、32p之间短接。上述外延生长阻挡物36n、36p有利地帮助使对鳍内生长的外延生长限于在鳍32n、32p之间的内部或者内鳍表面，并且因此减少在NFET与PFET器件之间短接的可能性。
现在将参照图6的流程图60进一步描述用于制作具有外延生长阻挡物36n、36p的FINFET30的示例方式。在块61开始，如以上所述，在块62处，形成从衬底31向上延伸并且沿着衬底间隔开的半导体(例如硅、锗、Si/Ge等)鳍32n、32p(图2A和图2B)。然后在块63处，形成栅极37n、37p，这些栅极覆盖半导体鳍32n、32p的中间部分35a、35b。同样利用三栅极结构，如图3A、图3B中所见，栅极37n、37p(分别包括绝缘体层和栅极电极层)将卷绕(warp)于鳍32n、32p的顶表面和侧表面周围。
如上所述，该方法还包括在块64处在来自多组鳍32n、32p的最外鳍的外侧表面上形成外延生长阻挡物36n、36p。更具体而言，这可以通过如图4中的虚线箭头代表的那样在从衬底31的法线偏移的角度α执行离子注入来完成。更具体而言，可以使用碳氟化物(例如CF4)或者其它适当气体来执行双角度注入/反应离子蚀刻(RIE)。作为结果，外延生长阻挡物36n、36p将包括化合物，该化合物包括半导体鳍材料(例如硅等)、碳和/或氟成分。外延生长阻挡物36n、36p将作为膜或者涂层出现，并且它们将在块65-66处在形成凸起源极区域38n、38p和漏极区域39n、39p期间抑制外延半导体材料的生长，这示例地结束图6中所示方法(块67)。
可以选择注入角度α以免太陡峭，并且由此允许离子渗透在鳍32n或者32p之间太深而又未太浅，使得彼此相向的多组鳍的外侧表面未在底部上变成被涂覆(如上文描述的那样，这将允许过量鳍间外延生长，该过量鳍间外延生长可能造成在NFET与PFET器件之间短接)。一般而言，注入角度α可以根据在给定的实施例中使用的鳍32n、32p的高度和横向间距在范围30至60度中。由于相邻鳍使鳍32n、32p的内表面免于离子轰击，所以这些内表面将具有来自注入的相对很少影响或者损坏，并且将由此仍然允许后续外延源极和漏极生长。有了恰当角度选择，这些内表面的在鳍32n、32p的顶部附近的仅小部分将受注入影响，并且由此具有在其上形成的外延生长阻挡物36n、36p，如图4和图5A中所示。
因此将理解，以上描述的方式可以相对易于实施，因为可以向多鳍FINFET制作过程添加附加步骤(即离子注入)以提供外延生长阻挡物36n、36p并且减少成品器件中的短接可能性。也就是说，以上描述的方式有利地允许制作相对高密度的多鳍配置而无外延出现于NFET与PFET之间。外延生长阻挡物36n、36p可以提供对外延生长的所需阻止，从而这一生长限于鳍32n、32p的其中需要该生长的内表面。
从在前文描述和关联附图中呈现的教导中受益的本领域技术人员将想到本发明的许多修改和其它实施例。因此理解本发明不限于公开的具体实施例并且修改和实施例旨在于包含在所附权利要求的范围内。

Claims (22)

1.一种多鳍FINFET器件，包括：
衬底；
多个半导体鳍，从所述衬底向上延伸并且沿着所述衬底被间隔开，每个半导体鳍具有相对的第一端和第二端以及在所述第一端与所述第二端之间的中间部分，所述多个半导体鳍中的最外鳍在其外侧表面和顶表面上以及在与所述顶表面相邻的其内部表面的部分上包括外延生长阻挡物；
至少一个栅极，覆盖所述半导体鳍的所述中间部分；
在所述半导体鳍之间的多个凸起外延半导体源极区域，与所述半导体鳍的所述第一端相邻；以及
在所述半导体鳍之间的多个凸起外延半导体漏极区域，与所述半导体鳍的所述第二端相邻。
2.根据权利要求1所述的多鳍FINFET器件，其中所述外延生长阻挡物包括化合物，所述化合物包括半导体以及碳和氟中的至少一项。
3.根据权利要求1所述的多鳍FINFET器件，其中所述多个半导体鳍包括硅。
4.根据权利要求1所述的多鳍FINFET器件，其中所述多个半导体鳍包括第一组P沟道鳍和从所述第一组P沟道鳍间隔开的第二组N沟道鳍以限定互补金属氧化物半导体(CMOS)FINFET。
5.根据权利要求4所述的多鳍FINFET器件，其中所述至少一个栅极包括用于所述第一组P沟道鳍和所述第二组N沟道鳍中的每个沟道鳍的相应栅极。
6.根据权利要求1所述的多鳍FINFET器件，还包括耦合到所述栅极并且从所述衬底向上延伸而且从所述半导体鳍间隔开的栅极接触区域。
7.根据权利要求1所述的多鳍FINFET器件，还包括：
源极接触区域，耦合到所述多个半导体鳍的所述第一端；以及
漏极接触区域，耦合到所述多个半导体鳍的所述第二端。
8.一种多鳍FINFET器件，包括：
衬底；
多个硅鳍，从所述衬底向上延伸并且沿着所述衬底被间隔开，每个硅鳍具有相对的第一端和第二端以及在所述第一端与所述第二端之间的中间部分，所述多个硅鳍中的最外鳍在其外侧表面和顶表面上以及在与所述顶表面相邻的其内部表面的部分上包括外延生长阻挡物，并且所述外延生长阻挡物包括化合物，所述化合物包括硅以及碳和氟中的至少一项；
至少一个栅极，覆盖所述硅鳍的所述中间部分；
在所述硅鳍之间的多个凸起外延半导体源极区域，与所述硅鳍的所述第一端相邻；以及
在所述硅鳍之间的多个凸起外延半导体漏极区域，与所述硅鳍的所述第二端相邻。
9.根据权利要求8所述的多鳍FINFET器件，其中所述多个硅鳍包括第一组P沟道鳍和从所述第一组P沟道鳍间隔开的第二组N沟道鳍以限定互补金属氧化物半导体(CMOS)FINFET。
10.根据权利要求9所述的多鳍FINFET器件，其中所述至少一个栅极包括用于所述第一组P沟道鳍和所述第二组N沟道鳍中的每个沟道鳍的相应栅极。
11.根据权利要求8所述的多鳍FINFET器件，还包括耦合到所述栅极并且从所述衬底向上延伸而且从所述硅鳍间隔开的栅极接触区域。
12.根据权利要求8所述的多鳍FINFET器件，还包括：
源极接触区域，耦合到所述多个硅鳍的所述第一端；以及
漏极接触区域，耦合到所述多个硅鳍的所述第二端。
13.一种制作多鳍FINFET器件的方法，包括：
形成从衬底向上延伸并且沿着所述衬底间隔开的多个半导体鳍，每个半导体鳍具有相对的第一端和第二端以及在所述第一端与所述第二端之间的中间部分；
形成至少一个栅极，所述至少一个栅极覆盖所述半导体鳍的所述中间部分；
在所述多个半导体鳍中的最外鳍的外侧表面和顶表面上以及在与所述顶表面相邻的其内部表面的部分上形成外延生长阻挡物；
在所述半导体鳍之间形成与所述半导体鳍的所述第一端相邻的多个凸起外延半导体源极区域；并且
在所述半导体鳍之间形成与所述半导体鳍的所述第二端相邻的多个凸起外延半导体漏极区域。
14.根据权利要求13所述的方法，其中形成所述外延生长阻挡物包括在从所述衬底的法线偏移的角度执行离子注入。
15.根据权利要求14所述的方法，其中所述角度在30度至60度的范围中。
16.根据权利要求14所述的方法，其中执行所述离子注入包括使用碳氟气体来执行反应离子蚀刻(RIE)。
17.根据权利要求13所述的方法，其中形成所述外延生长阻挡物包括形成包括半导体以及在碳和氟中的至少一项的外延生长阻挡物。
18.根据权利要求13所述的方法，其中形成所述多个半导体鳍包括形成多个硅鳍。
19.根据权利要求13所述的方法，其中形成所述多个半导体鳍包括形成第一组P沟道鳍和从所述第一组P沟道鳍间隔开的第二组N沟道鳍以定义互补金属氧化物半导体(CMOS)FINFET。
20.根据权利要求19所述的方法，其中形成所述至少一个栅极包括形成用于所述第一组P沟道鳍和所述第二组N沟道鳍中的每个沟道鳍的相应栅极。
21.根据权利要求13所述的方法，还包括形成从所述衬底向上延伸并且从所述半导体鳍间隔开而且耦合到所述栅极的栅极接触区域。
22.根据权利要求13所述的方法，还包括：
形成耦合到所述多个半导体鳍的所述第一端的源极接触区域；并且
形成耦合到所述多个半导体鳍的所述第二端的漏极接触区域。
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