CN103632974B - P型ldmos表面沟道器件提高面内均匀性的制造方法 - Google Patents

P型ldmos表面沟道器件提高面内均匀性的制造方法 Download PDF

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CN103632974B
CN103632974B CN201210305990.0A CN201210305990A CN103632974B CN 103632974 B CN103632974 B CN 103632974B CN 201210305990 A CN201210305990 A CN 201210305990A CN 103632974 B CN103632974 B CN 103632974B
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silica
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周正良
遇寒
马彪
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种P型LDMOS表面沟道器件提高面内均匀性的制造方法，以多晶硅和金属硅化物作为栅极，采用沟道注入、长时间高温推进、N型重掺杂的多晶硅电连接下沉工艺、多晶硅栅极硼离子掺杂的工艺次序，在栅极形成时没有掺杂硼，这样就可以进行长时间高温推进以形成足够宽的沟道，避免了短沟道效应造成的器件穿透或漏电；形成低掺杂的漏端漂移区后，淀积氧化硅并进行N型重掺杂的多晶硅电连接下沉工艺，再形成栅极多晶硅侧墙，并对多晶硅栅极进行硼注入，由于硼注入后没有长时间高温推进工艺，因此避免了硼穿透栅氧化层，也避免了重掺杂的多晶硅电连接下沉通道中N型杂质外扩到沟道或其它区域，这样形成的器件性能稳定，而工艺流程也简单易于实施。

Description

P型LDMOS表面沟道器件提高面内均匀性的制造方法
技术领域
本发明涉及半导体集成电路领域，特别属于一种P型LDMOS表面沟道器件提高面内均匀性的制造方法。
背景技术
对电池供电的手提式电子产品的电子元器件，较小的体积和较低的漏电是必须的性能要求，除此之外还需要有快的开关速度。P型LDMOS(LaterallyDiffusedMetalOxideSemiconductor，即横向扩散金属氧化物半导体)由多个栅极形成阵列以得到大于10A的输出电流，被广泛用于手提式电子产品的电源管理电路中。大的阵列意味着栅极总宽度很大，如何达到好的均匀性以保持低漏电是很大的问题。同时为了得到高的开关速度，阈值电压要较低，但较低的阈值电压会引起较高的漏电流。相比埋沟，表面沟道器件可折中低阈值电压和低漏电。目前，P型LDMOS表面沟道器件，如图1所示，包括N型衬底1’、N型外延区2’、N型沟道5’、第一轻掺杂漏扩散漂移区6’、第二轻掺杂漏扩散漂移区7’、N型重掺杂的多晶硅电连接下沉通道3’、栅氧化层9’、栅极多晶硅4’、钨硅叠层8’、漏极10’、源极11’、多晶硅侧墙13’，其生产工艺大致如下：在重掺杂的N型衬底1’上生长N型外延区2’，在N型外延区2’中进行多晶硅下沉深槽刻蚀，填充N型重掺杂多晶硅，回刻多晶硅至和硅表面齐平，形成N型重掺杂的多晶硅电连接下沉通道3’；进行第一次P型离子注入形成第一轻掺杂漏扩散漂移区6’；生长栅氧化层9’，在栅氧化层9’上淀积P型掺杂的多晶硅和钨硅叠层8’，光刻和干刻形成由栅极多晶硅4’和钨硅叠层8’组成的栅极；进行N型沟道离子注入，为避免栅极多晶硅4’中的P型杂质(通常为硼)穿透栅氧化层9’及分离到钨硅叠层8’中，用快速热退火激活沟道离子形成N型沟道5’，这样沟道长度必然较短并有较大变化，当然也可以采用长时间高温推进工艺以避免短沟道效应，但高温推进过程会使得下沉深槽中重掺杂多晶硅的杂质向沟道扩散，同时栅极中的硼容易穿透栅氧化层9’进入沟道5’，而且采用多晶硅栅极4’加钨硅叠层8’的栅极，由于钨硅对硼的固溶度高于多晶硅，硼会扩散到钨硅叠层8’中，造成多晶硅栅极中有较少硼而引起器件容易耗尽，这都会造成器件的阈值电压和其它关键指标不稳定；进行P型离子注入形成第二轻掺杂漏扩散漂移区7’，淀积侧墙介质并刻蚀形成多晶硅侧墙13’，然后光刻和离子注入形成源漏区，并快速热退火激活整个器件，最后形成金属硅化物12’、接触孔和金属连接等工艺形成器件。
发明内容
本发明要解决的技术问题是提供一种P型LDMOS表面沟道器件提高面内均匀性的制造方法，可以避免器件耗尽、穿透或漏电，提高器件的均匀性和稳定性。
为解决上述技术问题，本发明的P型LDMOS表面沟道器件提高面内均匀性的制造方法，包括以下步骤：
步骤1，在N型衬底上生长N型外延区，N型外延区上方生长栅氧化层，栅氧化层上方淀积一层非掺杂的多晶硅；
步骤2，光刻和干刻非掺杂的多晶硅形成多晶硅栅极，利用光刻胶遮挡后续形成漏区的区域以及靠近该区域的部分多晶硅栅极并进行N型离子注入，离子注入能量未穿透多晶硅栅极；
步骤3，去除光刻胶并进行第一次P型离子注入，注入的P型离子为硼，进行高温推进形成N型沟道和第一轻掺杂漏扩散漂移区；
步骤4，进行第二次P型离子注入，注入的P型离子为硼，形成第二轻掺杂漏扩散漂移区；
步骤5，淀积一层氧化硅，通过光刻和干刻打开N型沟道远离多晶硅栅极一侧的氧化硅，在打开区域刻蚀N型外延区形成深沟槽，所述深沟槽的底部位于N型衬底中；
步骤6，在深沟槽内和氧化硅上淀积N型重掺杂多晶硅，所述N型重掺杂多晶硅填充满深沟槽形成多晶硅电连接下沉通道；
步骤7，回刻N型重掺杂多晶硅并停止在氧化硅上；
步骤8，淀积一层有机介质，回刻有机介质和氧化硅，去除多晶硅栅极顶部的有机介质和氧化硅，并在多晶硅栅极侧面形成氧化硅侧墙，其余区域保留部分有机介质和全部氧化硅；
步骤9，对多晶硅栅极进行P型离子注入，注入的P型离子为硼，注入能量未穿透剩余的部分有机介质和氧化硅；
步骤10，去除有机介质，光刻定义源漏区，湿法去除部分氧化硅，进行源漏区离子注入并快速退火，在氧化硅去除部分下方形成源极和漏极；
步骤11，打开源漏区需要金属硅化的区域，进行金属硅化工艺，在多晶硅栅极和源极、漏极上形成金属硅化物。
步骤1中，所述N型衬底为重掺杂，掺杂浓度为1020cm-3以上；所述N型外延区为轻掺杂，掺杂浓度为1014～1016cm-3，其中N型外延区厚度每增加1μm，器件的击穿电压提高10～12伏；所述栅氧化层的厚度为120～300埃；所述非掺杂的多晶硅的厚度为1500～4000埃。
步骤2中，所述N型离子采用自对准的沟道注入，注入离子为磷，注入能量为80keV以下，剂量为1012～1014cm-2。
步骤3中，第一次P型离子注入的注入能量为30～120keV,剂量为1011～1013cm-2，高温推进的温度为900～1050℃，时间为30～180分钟。
步骤4中，第二次P型离子注入的注入能量为30～120keV,剂量为1011～1013cm-2。
步骤5中，所述氧化硅的厚度为1500～3000埃。
步骤6中，所述N型重掺杂多晶硅的掺杂离子为磷或砷，浓度大于1020cm-3，其中位于氧化硅上的N型重掺杂多晶硅的厚度是深沟槽宽度的1.2倍以上。
步骤7中，回刻后的多晶硅电连接下沉通道内的多晶硅表面比N型外延区的表面高出0～300埃。
步骤8中，所述有机介质的厚度为1000～5000埃。
步骤9中，P型离子注入的注入能量为2～15keV，剂量为1015cm-2以上。
步骤10中，所述源漏区的注入离子为硼，注入能量为5～80keV,剂量为1015cm-2以上，快速热退火的温度为1000～1100℃，时间为5～30秒。
本发明采用多晶硅和金属硅化物作为栅极，并调整了沟道注入、长时间高温推进、N型重掺杂的多晶硅电连接下沉工艺、多晶硅栅极硼离子掺杂的工艺次序，在栅极形成时没有掺杂硼，这样就可以进行长时间高温推进以形成足够宽的沟道，避免了短沟道效应造成的器件穿透或漏电；形成低掺杂的漏端漂移区后，淀积氧化硅并进行N型重掺杂的多晶硅电连接下沉工艺，再形成栅侧墙，并对多晶硅栅极进行硼注入，由于硼注入后没有长时间高温推进工艺，因此避免了硼穿透栅氧化层，也避免了重掺杂的多晶硅电连接下沉通道中N型杂质外扩到沟道或其它区域，这样形成的器件性能稳定，而工艺流程也简单易于实施。
附图说明
图1是现有P型LDMOS表面沟道器件的截面示意图；
图2至图15是本发明中P型LDMOS表面沟道器件在各工艺中的截面示意图；
图16是本发明P型LDMOS多个栅极并联形成的多指器件的俯视图；
图17是本发明中多个栅极并联的截面示意图；
图18是本发明P型LDMOS表面沟道器件的制造方法流程图。
具体实施方式
下面结合附图与具体实施方式对本发明作进一步详细的说明。
本发明提供的P型LDMOS表面沟道器件提高面内均匀性的制造方法，如图18所示，包括以下步骤：
步骤1，在重掺杂的N型衬底1上生长轻掺杂的N型外延区2，N型外延区2上方生长120～300埃的栅氧化层3，栅氧化层3上方淀积一层非掺杂的多晶硅，如图2所示；N型衬底1的掺杂浓度为1020cm-3以上，N型外延区2的掺杂浓度为1014～1016cm-3，其中N型外延区2厚度每增加1μm，器件的击穿电压提高10～12伏；非掺杂的多晶硅的厚度为1500～4000埃；
步骤2，对非掺杂的多晶硅进行光刻和干刻形成多晶硅栅极4，利用光刻胶遮挡后续形成漏区的区域以及靠近该区域的部分多晶硅栅极，其余部分的多晶硅栅极和后续形成源区的区域暴露，自对准栅极进行N型沟道离子注入，如图3所示，其中注入离子为磷，注入能量为80keV以下，剂量为1012～1014cm-2，离子注入能量未穿透多晶硅栅极；
步骤3，去除光刻胶并进行第一次P型离子注入，注入离子为硼，注入能量为30～120keV,剂量为1011～1013cm-2，如图4所示；
步骤4，进行高温推进形成N型沟道5和第一轻掺杂漏扩散漂移区6，如图5所示，其中高温推进的温度为900～1050℃，时间为30～180分钟；沟道长度由高温推进深度决定，可调整温度和时间得到所需的沟道长度，分级的第一轻掺杂漏扩散漂移区6的深度也由高温推进决定；
步骤5，进行第二次P型离子注入，注入离子为硼，注入能量为30～120keV,剂量为1011～1013cm-2，形成第二轻掺杂漏扩散漂移区7，如图6所示；
步骤6，淀积一层1500～3000埃的氧化硅，如图7所示；
步骤7，通过光刻和干刻打开N型沟道5远离多晶硅栅极4一侧的氧化硅，在打开区域刻蚀N型外延区2形成深沟槽，深沟槽的底部位于N型衬底1中，如图8所示；
步骤8，在深沟槽内和氧化硅上淀积N型重掺杂多晶硅，该N型重掺杂多晶硅填充满深沟槽形成多晶硅电连接下沉通道9，如图9所示；所述N型重掺杂多晶硅的掺杂离子为磷或砷，浓度大于1020cm-3，其中位于氧化硅上的N型重掺杂多晶硅的厚度是深沟槽宽度的1.2倍以上；
步骤9，回刻N型重掺杂多晶硅并停止在氧化硅上，如图10所述，回刻后的多晶硅电连接下沉通道9内的多晶硅表面比N型外延区2的表面高出0～300埃；
步骤10，淀积一层1000～5000埃的有机介质20，如图11所示；
步骤11，回刻有机介质20和氧化硅，去除多晶硅栅极4顶部的有机介质20和氧化硅，并在多晶硅栅极4侧面形成氧化硅侧墙8，其余区域保留部分有机介质和全部氧化硅，如图12所示；
步骤12，对多晶硅栅极4进行P型离子注入，如图13所示，注入杂质为硼，注入能量为2～15keV，剂量为1015cm-2以上，注入能量未穿透剩余的部分有机介质和氧化硅形成的叠层；
步骤13，去除有机介质20，光刻定义源漏区，湿法去除欲形成源极和漏极处的氧化硅，进行源漏区离子注入并快速退火，在氧化硅去除部分下方形成P型重掺杂的源极11和P型重掺杂的漏极10，如图14所示，源漏区的注入离子为硼，注入能量为5～80keV,剂量为1015cm-2以上，快速热退火的温度为1000～1100℃，时间为5～30秒；
步骤11，打开源漏区需要金属硅化的区域，进行金属硅化工艺，在多晶硅栅极4和源极11、漏极10上形成金属硅化物12，如图15所示。
本发明的P型LDMOS是由多个栅极并联而阵列的分立器件，其总输出电流大于10安培，其总栅极宽度大于50毫米，其中N型沟道5和多晶硅电连接下沉通道9形成电连接，而N型重掺杂的多晶硅电连接下沉通道9将源极11电连接到N型衬底1，P型重掺杂漏极10和多晶硅电连接下沉通道9的两侧各有一个栅极，即两个栅极共有漏极10和下沉通道9，如图16和17所示。
本发明采用多晶硅和金属硅化物作为栅极，并调整了沟道注入、长时间高温推进、N型重掺杂的多晶硅电连接下沉工艺、多晶硅栅极硼离子掺杂的工艺次序，在栅极形成时没有掺杂硼，这样就可以进行长时间高温推进以形成足够宽的沟道，避免了短沟道效应造成的器件穿透或漏电；形成低掺杂的漏端漂移区后，淀积氧化硅并进行N型重掺杂的多晶硅电连接下沉工艺，再形成栅侧墙，并对多晶硅栅极进行硼注入，由于硼注入后没有长时间高温推进工艺，因此避免了硼穿透栅氧化层，也避免了重掺杂的多晶硅电连接下沉通道中N型杂质外扩到沟道或其它区域，这样形成的器件性能稳定，而工艺流程也简单易于实施。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员可对本发明做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (11)

1.一种P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，包括以下步骤：
步骤1，在N型衬底(1)上生长N型外延区(2)，N型外延区(2)上方生长栅氧化层(3)，栅氧化层(3)上方淀积一层非掺杂的多晶硅；
步骤2，光刻和干刻非掺杂的多晶硅形成多晶硅栅极(4)，利用光刻胶遮挡后续形成漏区的区域以及靠近该区域的部分多晶硅栅极并进行N型离子注入，离子注入能量未穿透多晶硅栅极；
步骤3，去除光刻胶并进行第一次P型离子注入，注入的P型离子为硼，进行高温推进形成N型沟道(5)和第一轻掺杂漏扩散漂移区(6)；
步骤4，进行第二次P型离子注入，注入的P型离子为硼，形成第二轻掺杂漏扩散漂移区(7)；
步骤5，淀积一层氧化硅，通过光刻和干刻打开N型沟道(5)远离多晶硅栅极(4)一侧的氧化硅，在打开区域刻蚀N型外延区(2)形成深沟槽，所述深沟槽的底部位于N型衬底(1)中；
步骤6，在深沟槽内和氧化硅上淀积N型重掺杂多晶硅，所述N型重掺杂多晶硅填充满深沟槽形成多晶硅电连接下沉通道(9)；
步骤7，回刻N型重掺杂多晶硅并停止在氧化硅上；
步骤8，淀积一层有机介质(20)，回刻有机介质(20)和氧化硅，去除多晶硅栅极(4)顶部的有机介质(20)和氧化硅，并在多晶硅栅极(4)侧面形成氧化硅侧墙(8)，其余区域保留部分有机介质和全部氧化硅；
步骤9，对多晶硅栅极(4)进行P型离子注入，注入的P型离子为硼，注入能量未穿透剩余的部分有机介质和氧化硅；
步骤10，去除有机介质(20)，光刻定义源漏区，湿法去除部分氧化硅，进行源漏区离子注入并快速退火，在氧化硅去除部分下方形成源极(11)和漏极(10)；
步骤11，打开源漏区需要金属硅化的区域，进行金属硅化工艺，在多晶硅栅极(4)和源极(11)、漏极(10)上形成金属硅化物(12)。
2.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤1中，所述N型衬底(1)为重掺杂，掺杂浓度为1020cm-3以上；所述N型外延区(2)为轻掺杂，掺杂浓度为1014～1016cm-3，其中N型外延区(2)厚度每增加1μm，器件的击穿电压提高10～12伏；所述栅氧化层(3)的厚度为120～300埃；所述非掺杂的多晶硅的厚度为1500～4000埃。
3.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤2中，所述N型离子采用自对准的沟道注入，注入离子为磷，注入能量为80keV以下，剂量为1012～1014cm-2。
4.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤3中，第一次P型离子注入的注入能量为30～120keV,剂量为1011～1013cm-2，高温推进的温度为900～1050℃，时间为30～180分钟。
5.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤4中，第二次P型离子注入的注入能量为30～120keV,剂量为1011～1013cm-2。
6.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤5中，所述氧化硅的厚度为1500～3000埃。
7.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤6中，所述N型重掺杂多晶硅的掺杂离子为磷或砷，浓度大于1020cm-3，其中位于氧化硅上的N型重掺杂多晶硅的厚度是深沟槽宽度的1.2倍以上。
8.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤7中，回刻后的多晶硅电连接下沉通道(9)内的多晶硅表面比N型外延区(2)的表面高出0～300埃。
9.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤8中，所述有机介质(20)的厚度为1000～5000埃。
10.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤9中，P型离子注入的注入能量为2～15keV，剂量为1015cm-2以上。
11.根据权利要求1所述的P型LDMOS表面沟道器件提高面内均匀性的制造方法，其特征是，步骤10中，所述源漏区的注入离子为硼，注入能量为5～80keV,剂量为1015cm-2以上，快速热退火的温度为1000～1100℃，时间为5～30秒。
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