CN103608899B - Substrate, semiconductor device and manufacture method thereof - Google Patents

Substrate, semiconductor device and manufacture method thereof Download PDF

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Publication number
CN103608899B
CN103608899B CN201280030546.0A CN201280030546A CN103608899B CN 103608899 B CN103608899 B CN 103608899B CN 201280030546 A CN201280030546 A CN 201280030546A CN 103608899 B CN103608899 B CN 103608899B
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substrate
front surface
surface roughness
less
back surface
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CN103608899A (en
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石桥惠二
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

Provide the method for the substrate that can realize being reduced in the probability forming the defect produced in the step of epitaxial film or semiconductor element, the semiconductor device comprising this substrate and manufacture semiconductor device.Substrate (1) is the substrate (1) with front surface and back surface, wherein, being made up of monocrystalline silicon carbide at least partially of front surface, substrate has the mean value of the surface roughness Ra at front surface place being not more than 0.5nm, the standard deviation of this surface roughness Ra is not more than 0.2nm, be not less than 0.3nm and be not more than the mean value of the surface roughness Ra at back surface place of 10nm, and the standard deviation of this surface roughness Ra is not more than 3nm, and be not less than the diameter of front surface of 110mm.

Description

Substrate, semiconductor device and manufacture method thereof
Technical field
The present invention relates to substrate, semiconductor device and manufacture method thereof, and more specifically, relate to the substrate formed by carborundum at least partially of wherein front surface, semiconductor device and manufacture method thereof.
Background technology
The substrate of known such as single-crystal silicon carbide substrate traditionally, wherein being formed by carborundum at least partially of front surface.Because such carborundum is higher than the nitride-based semiconductor of such as gallium nitride (GaN) in thermal conductivity, so expect the substrate that is made up of the carborundum material as the power device for controlling high pressure and high electric current.Such as, U.S. Patent Publication No.2006/0225645(is hereinafter referred to as PTL1) disclose the silicon carbide substrates with 3 inch diameters, for it, define about warpage or TTV(total thickness variations) value, to prevent the film quality of obtained epitaxial film to be deteriorated due to uneven temperature distribution when forming epitaxial film on the front surface of silicon carbide substrates.In addition, WO2010/119792(is hereinafter referred to as PTL2) disclose the definition of following characteristic: namely, designated shape, the warpage or bending of such as substrate, and the value of the surface roughness Ra in the front-surface side of substrate is set to 1nm or less, and the value of the surface roughness Ra on the back surface side of substrate is set to 100nm or less.PTL2 defines roughness as above, ensures the regulation shape of substrate when forming film with box lunch on the front surface of substrate.
Reference listing
Patent documentation
PTL1：US2006/0225645A1
PTL2：WO2010/119792
Summary of the invention
Technical problem
PTL1 as above is not specifically related to the surface roughness of substrate.Although PTL2 defines the front surface of substrate and the surface roughness of back surface to ensure the regulation shape of substrate, but it does not relate to the relation between the film quality of the surface roughness (surface roughness specifically, on back surface side) and the epitaxial film that formed on the front surface of substrate etc. of substrate yet.
But, as the result of the absorbed research of the present inventor, the present inventor has been found that, when special surface roughness on the back surface of substrate is large, on the front surface of substrate growing epitaxial film step in Heat Treatment, contact condition change thereon between the receiver of carrier substrate and the back surface of substrate, and therefore, produce in the substrate in Temperature Distribution.Such Temperature Distribution adversely may affect the film quality of formed epitaxial film.
In addition, the front surface of substrate forms epitaxial film and is formed on epitaxial film in the step of semiconductor element, the back surface of substrate may by vacuum suction.If such by vacuum suction during surface roughness at back surface place large, then in some cases, substrate can not reliably be adsorbed.Therefore, defect may be produced in the step forming semiconductor element.
And when the surface roughness at the back surface place at substrate is large, crystal defect may develop from the back surface side of substrate at the Heat Treatment for the formation of epitaxial film, and substrate may warpage.So, when substrate increases in size, the absolute value of the amount of warpage of substrate becomes large, and this may cause the factor causing defect in the step forming epitaxial film or forming element.
The present invention is made and solves the problems referred to above, and the object of this invention is to provide and a kind ofly can realize being reduced in the substrate of the probability forming the defect produced in the step of epitaxial film or semiconductor element, the semiconductor device comprising this substrate and manufacture method thereof.
For the solution of problem
A kind of substrate according to the present invention is the substrate with front surface and back surface, wherein, being made up of carborundum at least partially of front surface, 0.5nm is not more than and the standard deviation of this surface roughness Ra is not more than 0.2nm at the mean value of the surface roughness Ra at front surface place, be not less than 0.3nm at the mean value of the surface roughness Ra at back surface place and be not more than 10nm and the standard deviation of this surface roughness Ra is not more than 3nm, further, the diameter of front surface is not less than 110mm.
By doing like this, the front surface of substrate being formed in the step of epitaxial loayer, the local in the state of the Contact of the receiver of support substrates and the back surface of substrate can be suppressed to change.Therefore, it is possible to suppress along with the change in the state of contact and the uneven temperature appeared on substrate distributes such problem, and result, can be formed in epitaxial loayer good on film quality.
At this, depend on the material of substrate, the surface state being suitable for forming epitaxial loayer or forming device is different, and also different by the impact of its surface roughness.That is, the surface roughness being suitable for being formed epitaxial loayer etc. is different between the substrate be made up of carborundum at least partially and the substrate be made up of other semi-conducting materials of wherein front surface according to the present invention.In addition, because machinery and chemical durability depend on material and different, for the processing conditions (polishing condition) of the technique damaged layer controlled at front surface place or surface roughness for each substrate difference be made up of different materials.Therefore, suitable processing method also the substrate that is made up of carborundum according to the present invention and by the substrate that other materials is formed between different.
Based on such discovery, in substrate according to the present invention, be controlled as at the mean value of the surface roughness Ra at back surface place and be not less than 0.3nm and be not more than 10nm, and its standard deviation is controlled as and is not more than 3nm.Therefore, on the front surface of substrate in growing epitaxial film, generation or the development of the crystal defect on back surface side can be suppressed, and therefore, also can suppress the warpage of substrate.As a result, the probability of the generation of the defect of the warpage owing to substrate can be reduced in the step forming epitaxial film or in later step in forming element.
Note, surface roughness Ra refers at the undefined arithmetic average roughness Ra of JISB0601, and, it is defined as the value calculated by following manner: on the direction of its average line, extract reference length from roughness curve, and also average to distance (absolute value of the deviation) summation of experiment curv to the average line of the line segment extracted from this.Be not more than 0.5nm at the mean value of the surface roughness Ra at the front surface place of substrate, as mentioned above, but preferably, it is not less than 0.1nm and is not more than 0.3nm.When surface roughness Ra is not more than 0.5nm, good epitaxially grown layer can be formed on the front surface of substrate.In addition, when surface roughness Ra is not less than 0.1nm, suppress in such as CMP(chemico-mechanical polishing) polishing in increase on step number, and suppress the reduction on productive rate.Therefore, it is possible to avoid the excessive increase in manufacturing cost.
In addition, although be not more than 0.2nm in the standard deviation of the surface roughness Ra at the front surface place of substrate, as mentioned above, preferably, it is not more than 0.1nm, and it is further preferred that it is not more than 0.05nm.When such standard deviation is not more than 0.2nm, uniform epitaxially grown layer can be formed on the front surface of substrate.
And although be not less than 0.3nm at the mean value of the surface roughness Ra at back surface place and be not more than 10nm, preferably, it is not less than 0.4nm and is not more than 5nm, and it is further preferred that it is not less than 0.5nm and is not more than 2nm.It should be noted that when the mean value of the surface roughness Ra at back surface place is not less than 10nm, the local in the step forming epitaxially grown layer of the contact condition between receiver and the back surface of substrate changes (change).Therefore, Temperature Distribution in the substrate becomes uneven, and the quality of resultant epitaxial loayer may reduce.And the problem of the large warpage of the substrate caused from the expansion of the back surface of substrate due to during heating crystal defect occurs, and the productive rate in device step may reduce.In order to be set to be less than 0.3nm by the mean value of the surface roughness Ra at back surface place, need the surface treatment of high complexity, this causes the increase manufactured on the cost of substrate, and is manufacturing the productivity ratio reduced in the process of substrate.Such as, in order to the mean value of the surface roughness Ra by the back surface place at substrate is set to be less than 0.3nm, need the CMP process using colloidal silica and chemical composition etc., use the normal buff of neutral diamond slurries to realize this sample value because be difficult to utilize.
Although be not more than 3nm in the standard deviation of the surface roughness Ra at back surface place, as mentioned above, preferably, it is not more than 1.5nm, and it is further preferred that it is not more than 0.7nm.By doing like this, the contact condition between the back surface and receiver of substrate can on whole back surface general uniform, and therefore, it is possible to form even epitaxially grown layer on the front surface of substrate.
In addition, the diameter of the back surface of substrate is set to 110mm or larger.By doing like this, large-area substrate can be had increase by using the quantity of the semiconductor element (chip) that can be formed on substrate.Therefore, it is possible to reduce the manufacturing cost in the step (device step) forming semiconductor element, and productivity ratio can be improved.
A kind of semiconductor device according to the present invention comprises above-mentioned substrate, epitaxial loayer and electrode.Epitaxial loayer is formed on the front surface of substrate, and is made up of carborundum.Epitaxial loayer forms electrode.In this case, can realize semiconductor device, this semiconductor device achieves defect and produces the reduction of probability and the suppression of manufacturing cost.
In addition, a kind of method manufacturing substrate according to the present invention comprises step: prepare the ingot be made up of carborundum; There is front surface and back surface and the diameter of front surface is not less than the substrate of 110mm by ingot section being obtained; Further, the front surface of polished substrate and back surface.In polishing step, by controlling the resistance coefficient in polishing step, polishing front surface and back surface, make to be not more than 0.5nm and the standard deviation of surface roughness Ra is not more than 0.2nm at the mean value of the surface roughness Ra at front surface place, and make be not less than 0.3nm at the mean value of the surface roughness Ra at back surface place and be not more than 10nm, and the standard deviation of surface roughness Ra is not more than 3nm.In this case, can reliably obtain according to substrate of the present invention.
A kind of method manufacturing semiconductor device according to the present invention comprises step: prepare above-mentioned substrate; The front surface of substrate is formed the epitaxial loayer be made up of carborundum; Further, epitaxial loayer forms electrode.In this case, by using according to substrate of the present invention, reduce the probability that defect produces, and the cost manufacturing semiconductor device can be suppressed.
Beneficial effect of the present invention
According to the present invention, can provide a kind of and can allow to be formed the epitaxial film with good film quality and reduce the substrate of the probability that defect produces, semiconductor device and manufacture method thereof.
Accompanying drawing explanation
Fig. 1 is the perspective diagram of the embodiment illustrated according to substrate of the present invention.
Fig. 2 is the partial cross section schematic diagram of substrate shown in FIG.
Fig. 3 is the flow chart of the method for illustrating the substrate shown in shop drawings 1.
Fig. 4 is the partial cross section schematic diagram of the change of embodiment according to substrate of the present invention.
Fig. 5 is the schematic cross-section of the embodiment that semiconductor device according to the invention is shown.
Fig. 6 is the flow chart for illustrating the method being manufactured on the semiconductor device shown in Fig. 5.
Fig. 7 is the schematic cross-section of the change of the embodiment that semiconductor device according to the invention is shown.
Embodiment
Below with reference to accompanying drawing, one embodiment of the present of invention are described.Note, in accompanying drawing below, identical or corresponding element is assigned identical Reference numeral, and will not repeat its description.
With reference to Fig. 1 and 2, an embodiment according to substrate of the present invention is described.
Substrate 1 is in fig 1 and 2 the substrate 1 be made up of the monocrystalline of carborundum, and is not more than 0.5nm at the mean value of the surface roughness Ra at front surface 11 place of substrate 1, and the standard deviation of surface roughness Ra is not more than 0.2nm.In addition, be not less than 0.3nm at the mean value of the surface roughness Ra at back surface 12 place of substrate 1 and be not more than 10nm, and the standard deviation of surface roughness Ra is not more than 3nm.And the diameter D of the front surface of substrate 1 is not less than 110mm.Therefore, also controlling in the substrate 1 of its surface roughness for back surface 12 except front surface 11, front surface 11 grows in the process of the epitaxial film be made up of carborundum, can make back surface 12 and on it film forming device of carrier substrate 1 receiver between contact condition on whole back surface 12 evenly.Therefore, it is possible to suppress the Temperature Distribution produced in substrate 1 occurred owing to the localized variation on contact condition.Therefore, it is possible to improve the uniformity of film quality, the degree of crystallinity such as in formed epitaxial film or impurity concentration.As a result, the change in the characteristic of the semiconductor device by utilizing epitaxial film to be formed can be suppressed, and the productive rate of resultant semiconductor device can be improved.
In addition, substrate 1 meets relational expression 100≤D/T≤1000 and 0≤Wb/T≤0.2, and wherein, D(is see Fig. 1) represent the diameter of front surface 11, T(is see Fig. 2) and represent the thickness of substrate 1, and Wb represents the warpage of the back surface in above-mentioned substrate 1.In this case, the present invention is applied to substrate 1 relatively large in warpage, and following more remarkable effect of the present invention: the probability producing defect in the step forming epitaxial film or the process of being used for producing the semiconductor devices can be lowered.
Next the method for substrate 1 in a kind of Fig. 1 of being manufactured on and shown in 2, that be made up of carborundum is described with reference to Figure 3.
See Fig. 3, initially, substrate preparation step (S10) is performed.At this, prepare the substrate be made up of carborundum, this substrate is the object that will process and its surface roughness will be adjusted.Specifically, such as, the crystal growth step (S11) be used at seed substrate Epitaxial growth carborundum is performed.Therefore, obtain and to be made up of carborundum and there is the ingot of to a certain degree size.
Then, ingot forming step (S12) is performed.Particularly, the front surface of the ingot obtained in step as above (S11), back surface and periphery etc. are ground, to obtain the ingot with regulation shape and planar orientation.
Then, slicing step (S13) is performed.In this step (S13), by the ingot section using scroll saw etc. to obtain as mentioned above.As a result, obtain the substrate be made up of carborundum, this substrate is the object that will process, and its surface roughness will be adjusted.
Then, as shown in Figure 3, actuating surface treatment step (S20).Specifically, grinding steps (S21) is performed, for utilizing conventionally known method to grind front surface and the back surface of substrate.By this step (S21), the thickness of adjustment substrate, makes the surface roughness Ra in the front-surface side and back surface side of substrate be reduced to particular value.
Then, polishing step (S22) is performed.In this step (S22), such as polishing equipment or CMP equipment by using, coming front surface and the back surface of polished substrate.By this step (S22), obtain front surface 11 and the back surface 12 with surface roughness Ra as above.
Then, the cleaning (S30) shown in performing in figure 3.Specifically, any method known is traditionally used to come front surface and the back surface of the substrate of clean polishing.Therefore, it is possible to the substrate 1 be made up of carborundum shown in obtaining in fig 1 and 2.
The present invention is not only applicable to the substrate be made up of monocrystal SiC as above, and is applicable to as shown in Figure 4 in conjunction with substrate (combined substrate).The version of the embodiment according to substrate of the present invention is described with reference to Fig. 4.
See Fig. 4, the substrate 1 as the version of the embodiment of substrate according to the present invention be by engage multiple monocrystalline tile (tile) substrate 30 of being made up of monocrystalline silicon carbide to the front surface of base substrate 20 and obtain in conjunction with substrate.By to cheap large base substrate in conjunction with high-quality small pieces single crystalline substrate, large-diameter substrates good on the crystal mass of front surface can be manufactured on low cost.
Preferably, the gap between multiple monocrystalline tile substrate 30 is buried at composition surface 31 place.Although be not particularly limited for the material of base substrate 20, heat-resisting and intensity preferably uses the substrate be made up of carborundum.Carborundum can be any form of monocrystalline, polycrystalline and the sintered body with many dislocation or defect.
Also in this substrate 1, can be not more than 0.5nm, and its standard deviation can be not more than 0.2nm at the mean value of the surface roughness Ra at front surface 11 place, wherein, front surface 11 is exposed single-crystal carborundum and will forms the surface of epitaxial film etc. thereon.In addition, be not less than 0.3nm at the mean value of the surface roughness Ra at front surface 11 place, and be not more than 10nm, and its standard deviation is not more than 3nm.Such substrate 1 also can realize the effect identical with the effect utilizing substrate shown in fig 1 and 2 to obtain.
Summary is manufactured on the method for the substrate 1 shown in Fig. 4.The method being manufactured on the substrate 1 shown in Fig. 4 is identical with the method for manufacture substrate 1 in fig 1 and 2, but the substrate preparation step (S10) is in figure 3 with shown in fig 1 and 2 to manufacture in the method for substrate different.Namely, in the method for the manufacture substrate 1 in the diagram, although perform identical step until as the above-mentioned crystal growth step (S11) of the substrate preparation step (S10) shown in figure 3, ingot forming step (S12) and slicing step (S13), but subsequently, perform for the formation of monocrystalline tile substrate 30(see Fig. 4) tile substrate forming step (S14).In this step (S14), such as, by using cast-cutting saw, scroll saw etc. from the substrate obtained at above-mentioned slicing step (S13), cut monocrystalline tile substrate 30.The two-dimensional shapes of this single crystalline substrate 30 can have any shape, such as comprises polygon or the circle of triangle and quadrangle.
Afterwards, integrating step (S15) is performed.In this step (S15), utilize any method to be arranged in base substrate 20 by multiple monocrystalline tile substrate 30, and be engaged with each other.As the method used in this integrating step (S15), such as, any method can be used, such as utilize sublimation method etc. to form carborundum using as the method for grafting material and the method that utilizes binding agent to engage.
Afterwards, substrate 1 shown in the diagram can be obtained by the surface treatment step (S20) shown in execution in figure 3 and cleaning (S30).
Now, the semiconductor device utilizing the substrate 1 shown in Fig. 1 or 4 to be formed is described with reference to figure 5.
UMOS410 in Figure 5 comprises: according to substrate 1 of the present invention; n -type SiC epitaxial layer 102; P-type well area 117; p +type trap contact extrinsic region 116; n +type source extrinsic region pair; Gate insulating film 107, it is formed in the inner wall surface of groove, and groove is removed at n by part +type source extrinsic region between p-type well area 117 and n -type SiC epitaxial layer 102 and formed; Gate electrode 122, it is formed on gate insulating film 107 to bury groove; Interlayer dielectric 106, the surface of its covering grid electrode 122 and p-type well area 117; The opening formed in interlayer dielectric 106, for exposing n +type source extrinsic region 111 and p +a part for the upper surface of type trap contact extrinsic region; Source electrode 121, it is connected to n by this opening +type source extrinsic region 111 and p +type trap contact extrinsic region 116; And drain electrode 124, it is formed on the back surface of substrate 1.
In UMOS410 in Figure 5, form gate insulating film 107 and extend and the basal surface relative with the lowermost part of gate electrode 122 with on left/right direction to cover the side surface that the up/down direction of the groove formed in p-type well area 117 extends.It should be noted that p-type and the N-shaped of each parts above-mentioned that can all reverse.
The operation of present description UMOS410.Along gate insulating film 107, on the side surface of p-type well area 117 (near composition surface), can apply according to the voltage for gate electrode 122, form the inversion layer because electronics causes.Then, according to the electrical potential difference between source electrode 121 and drain electrode 124, above-mentioned source electrode 121 can be striden across and drain electrode 124 applies through n +type source extrinsic region 111, the inversion layer in p-type well area 117, n -type SiC epitaxial layer 102 and as n +the electric current of the substrate 1 of type SiC substrate.Electric current now between source electrode 121 and drain electrode 124 flows along gate insulating film 107.
Because the UMOS410 in Figure 5 comprises according to substrate 1 of the present invention, so to n -the uniformity of temperature profile in substrate 1 has been made during the formation of type SiC epitaxial layer 102.Therefore, n -type SiC epitaxial layer 102 has good film quality.Therefore, it is possible to realize UMOS410 good in electrical characteristics.
Next the method being manufactured on the UMOS410 shown in Fig. 5 is described with reference to Figure 6.As shown in Figure 6, in the method manufacturing UMOS410, initially, the substrate preparation step (S100) as the step preparing substrate 1 is performed.In this step (S100), substrate 1 can be prepared by the step performing manufacture substrate shown in figure 3.Then, execution forms n as on the front surface of substrate 1 -the epitaxial growth steps (S200) of the step of type SiC epitaxial layer 102.Then, the procedure of processing (S300) shown in performing in figure 6.Specifically, utilize ion implantation etc. to perform and form p-type well area 117, p +type trap contact extrinsic region 116 and n +the step (S310) of type source extrinsic region 111.
Then, in step (S300), perform by partly removing at n +type source extrinsic region between p-type well area 117 and n -type SiC epitaxial layer 102 forms the step (S320) of groove.In this step (S320), can such as by using reactive ion etching (RIE) to form groove.It should be noted that, in order to the conducting by forming inversion layer to guarantee near the side surface in the groove in p-type well area 117 between source electrode 121 and drain electrode 124, the degree of depth on the up/down direction of groove is preferably more than the thickness of p-type well area 117.
Then, the electrode forming step (S400) corresponding with the step of the structure formed except epitaxial loayer is performed.Specifically, on the inner surface of the groove that the method on use is formed and on the upper surface of p-type well area 117, such as utilizing thermal oxidation to be formed will as the dielectric film of gate insulating film 107.Afterwards, be used in the mask pattern that formed in lithography step as mask, partly etch away dielectric film, be formed in the gate insulating film 107 shown in Fig. 5 thus.Gate insulating film 107 is formed gate electrode 122.In addition, after interlayer dielectric 106 being formed as cover entirety, etching as mask by being used in the mask pattern that interlayer dielectric 106 is formed, and partly remove interlayer dielectric 106.Thus, opening is formed to expose n +type source extrinsic region 111 and p +a part for the upper surface of type trap contact extrinsic region.Then, source electrode 121 is formed, to be connected to n by opening +type source extrinsic region 111 and p +type trap contact extrinsic region, and cover the interlayer dielectric 106 on gate electrode 122.In addition, the back surface side of substrate 1 forms drain electrode 124.UMOS410 shown in can obtaining thus in Figure 5.
With reference now to Fig. 7, the version of the semiconductor device according to the invention of substrate 1 formation utilized shown in Fig. 1 or 4 is described.
DMOS420 in the figure 7 represents the vertical MOSFET of a type.In DMOS420 in the figure 7, electronics flows to the n relative with gate insulating film 107 from source electrode 121 -the region of type SiC epitaxial layer 102, and afterwards, electronics is branched to flow to drain electrode 124.Therefore DMOS is configured such that electric current flows between source electrode 121 and drain electrode 124.
Specifically, as shown in Figure 7, similar with the UMOS410 in Figure 5, DMOS420 comprises according to substrate 1 of the present invention and the n that formed on the front surface of substrate 1 -type SiC epitaxial layer 102.At n -in the front surface of type SiC epitaxial layer 102, form the p-type well area 117 arranged at a certain distance each other right.In the front surface of p-type well area 117, form p +type trap contact extrinsic region 116 and n +type source extrinsic region 111.Gate insulating film 107 be formed from p-type well area 117 between n -the front surface of type SiC epitaxial layer 102 is to p-type well area 117 and n above it +type source extrinsic region 111 extends.Gate insulating film 107 is formed gate electrode 122.
Interlayer dielectric 106 is formed the front surface of a covering grid electrode 122 and p-type well area 117.In interlayer dielectric 106, form opening to expose n +type source extrinsic region 111 and p +a part for the upper surface of type trap contact extrinsic region.Formed and be connected to n by opening +type source extrinsic region 111 and p +the source electrode 121 of type trap contact extrinsic region 116.In addition, the back surface of substrate 1 forms drain electrode 124.Note, all can reverse p-type and the N-shaped of each parts above-mentioned.
It should be noted that p-type well area 117 has the thickness of such as about 1.5 μm, and about 1 × 10 can be comprised 16cm -3the aluminium as impurity.P +type trap contact extrinsic region 116 can comprise about 1 × 10 19cm -3the aluminium as impurity, and the thickness of about 0.4 μm can be had.
The operation of present description DMOS420.If do not apply voltage to gate electrode 122, then in DMOS420, or at n +between type source extrinsic region 111 and p-type well area 117 or at p-type well area 117 and n -between type SiC epitaxial layer 102, prevent the conducting from source electrode 121 to drain electrode 124, because n +type source extrinsic region 111 is N-shapeds, and p-type well area 117 is p-types, and n -type SiC epitaxial layer 102 is N-shapeds.If apply negative voltage to gate electrode 122, then below gate electrode 122 with gate insulating film 107 cover p-type well area 117 in form the accumulation layer caused by the hole of main charge carrier.Therefore, the flowing of electric current becomes more difficult.
But, if apply positive voltage to gate electrode 122, then form inversion layer because electronics causes in the p-type well area 117 covered with gate insulating film 107 below gate electrode 122.Therefore, from n +type source extrinsic region 111 does not form depletion layer in the region that drain electrode 124 extends.Therefore, electric current can depend on that the electrical potential difference between source electrode 121 and drain electrode 124 is come to flow between source electrode 121 and drain electrode 124.
Because the DMOS420 in the figure 7 utilizes according to substrate 1 of the present invention, form n mainly with arriving -the uniformity of temperature profile in substrate 1 has been made during type SiC epitaxial layer 102.Therefore, n -type SiC epitaxial layer 102 has good film quality.Therefore, it is possible to realize DMOS420 good in electrical characteristics.
It should be noted that p +type trap contact extrinsic region 116 has the effect of the electromotive force by be electrically connected to each other source electrode 121 and p-type well area 117 and fixing p-type well area 117 place.As mentioned above, the impurity concentration in p-type well area 117 is low reaches 1 × 10 16cm -3.Therefore, be difficult to by direct joining p-type well area 117 and source electrode 121, they are electrically connected to each other.Then, in DMOS420, that be made up of p-type implanted layer identical with p-type well area 117 in type, higher than p-type well area 117 in impurity concentration p +type trap contact extrinsic region 116 is arranged such that source of engagement electrode 121.Therefore, source electrode 121 and p-type well area 117 can pass through p +type trap contact extrinsic region 116 is electrically connected to each other.
Be described in now the method for the manufacture DMOS420 shown in Fig. 7.The method of the manufacture DMOS420 is in the figure 7 substantially the same with the method for manufacture UMOS410 shown in figure 6, and the step (S100) performed in figure 6 is to step (S300).Although perform in step (S300) and form p-type well area 117, p +type trap contact extrinsic region 116 and n +the step (S310) of type source extrinsic region 111, but it is such to be different from the method being manufactured on the UMOS410 shown in Fig. 5, does not form groove afterwards.
Afterwards, electrode forming step (S400) is performed.In step (S400), at p +the contact of type trap extrinsic region 116, n +on the upper surface of type source extrinsic region 111 and p-type well area 117, such as, utilize thermal oxidation, being formed will as the dielectric film of gate insulating film 107.Afterwards, be used in the mask pattern that formed in lithography step as mask, partly etch away dielectric film, be formed in the gate insulating film 107 shown in Fig. 7 thus.Gate insulating film 107 is formed with a part for blanket p-type well area 117 and n -type SiC epitaxial layer 102 and n +a part for type source extrinsic region 111.Afterwards, the situation of UMOS410 is as shown in FIG. 5 such, forms gate electrode 122, source electrode 121 and drain electrode 124.DMOS420 shown in can obtaining thus in the figure 7.
Property feature of the present invention is listed, although those the partly redundancies in they and above-described embodiment at this.
Substrate 1 according to the present invention is the substrate 1 with front surface 11 and back surface 12, wherein, being made up of monocrystalline silicon carbide at least partially of front surface 11, and be not more than 0.5nm at the mean value of the surface roughness Ra at front surface 11 place, and the standard deviation of surface roughness Ra is not more than 0.2nm, and be not less than 0.3nm at the mean value of the surface roughness Ra at back surface 12 place and be not more than 10nm, and the standard deviation of surface roughness Ra is not more than 3nm, and the diameter D of front surface 11 is not less than 110mm.
By doing like this, the front surface 11 of substrate 1 forms epitaxial loayer (such as, n in Figure 5 -type SiC epitaxial layer 102) step in, the local in the state of the contact between the receiver and the back surface 12 of substrate 1 of support substrates can be suppressed to change.Therefore, it is possible to suppress the problem of the uneven temperature distribution appeared at along with the change on contact condition in substrate 1, and result, can be formed in epitaxial loayer good on film quality.
In addition, by the mean value of the surface roughness Ra at back surface 12 place is controlled as being not less than 0.3nm and being not more than 10nm and controlling be not more than 3nm by its standard deviation, on the front surface 11 of substrate 1 in growing epitaxial film, generation or the development of the crystal defect on back surface 12 side can be suppressed, and therefore, also can suppress the warpage of substrate 1.As a result, the probability that the defect owing to the warpage of substrate 1 produces can be reduced in the step forming epitaxial film or in later step in forming element.
Note, be not more than 0.5nm at the mean value of the surface roughness Ra at front surface 11 place of substrate 1, as mentioned above, but preferably, it is not less than 0.1nm and is not more than 0.3nm.When surface roughness Ra is not more than 0.5nm, good epitaxial loayer (n can be formed on the front surface 11 of substrate 1 -type SiC epitaxial layer 102).In addition, when surface roughness Ra is not less than 0.1nm, suppress the increase on step number in the polishing of such as CMP, and suppress the reduction on productive rate.Therefore, it is possible to avoid the excessive increase in manufacturing cost.
In addition, although be not more than 0.2nm in the standard deviation of the surface roughness Ra at front surface 11 place of substrate 1, as mentioned above, preferably, it is not more than 0.1nm, and it is further preferred that it is not more than 0.05nm.When such standard deviation is not more than 0.2nm, uniform epitaxial loayer can be formed on the front surface 11 of substrate 1.
And although be not less than 0.3nm at the mean value of the surface roughness Ra at back surface 12 place and be not more than 10nm, preferably, it is not less than 0.4nm and is not more than 5nm, and it is further preferred that it is not less than 0.5nm and is not more than 2nm.It should be noted that when the mean value of the surface roughness Ra at back surface 12 place is not less than 10nm, the local in the step forming epitaxially grown layer of the contact condition between receiver and the back surface 12 of substrate 1 changes (change).Therefore, the Temperature Distribution in substrate 1 becomes uneven, and resultant epitaxial loayer (n -type SiC epitaxial layer 102) quality may reduce.And the problem of the large warpage of the substrate 1 caused from the expansion of the back surface 12 of substrate 1 due to during heating crystal defect occurs, and as formed on substrate 1 semiconductor device step device step in productive rate may reduce.In order to be set to be less than 0.3nm by the mean value of the surface roughness Ra at back surface 12 place, need the surface treatment of high complexity, this causes the cost manufacturing substrate 1 increase and manufacture the reduction of productivity ratio in the process of substrate 1.Such as, in order to the mean value of the surface roughness Ra by back surface 12 place at substrate 1 is set to be less than 0.3nm, need the CMP process using colloidal silica and chemical composition etc., use the normal buff of neutral diamond slurries to realize this sample value because be difficult to utilize.
Although be not more than 3nm in the standard deviation of the surface roughness Ra at back surface 12 place, as mentioned above, preferably, it is not more than 1.5nm, and it is further preferred that it is not more than 0.7nm.By doing like this, the contact condition between the back surface 12 and receiver of substrate 1 can general uniform on whole back surface, and therefore, it is possible to forms even epitaxially grown layer on the front surface 11 of substrate 1.
In addition, the diameter of the back surface 12 of substrate 1 is set to 110mm or larger.By doing like this, can have by using the quantity that large-area substrate 1 increases the semiconductor element (chip) that can be formed on substrate 1.Therefore, it is possible to reduce the cost manufacturing semiconductor element, and the productivity ratio in the step forming semiconductor device can be improved.
It should be noted that and AFM or optical interferometer roughness test device can be utilized to carry out measure surface roughness Ra.The position of the measurement of surface roughness Ra is set to resemble the position from the core interval 10mm of substrate 1 grid, and, the region outside the position getting rid of the distance of the outer peripheral portion 5nm apart from substrate 1 from measurement target region.In addition, when by shown in the diagram in conjunction with substrate (substrate 1 formed by multiple monocrystalline tile substrate 30 is connected to each other) as substrate 1, composition surface 31(bonding part between adjacent monocrystalline tile substrate 30) be not set to direct measuring position, but at the front surface place measure surface roughness Ra of the monocrystalline tile substrate 30 adjacent with composition surface 31.
In superincumbent substrate, the nitrogen concentration in monocrystalline silicon carbide can not higher than 2 × 10 19/ cm 3.In addition, in above-mentioned substrate 1, the nitrogen concentration in above-mentioned monocrystalline silicon carbide can be not less than 4 × 10 18/ cm 3and not higher than 2 × 10 19/ cm 3.And occur from the angle of suppression fault, the nitrogen concentration in monocrystalline silicon carbide can preferably higher than 5 × 10 18/ cm 3.In this case, the resistance of substrate 1 can be lowered to a certain degree, and, the expansion in the fault of Heat Treatment in substrate 1 for the formation of epitaxial loayer can be suppressed, and therefore, it is possible to suppress the warpage of substrate 1.Although should be lowered to be reduced in the nitrogen concentration in monocrystalline silicon carbide at the nitrogen concentration of growing period in atmosphere of carborundum, under such atmospheric condition, polycrystalline type may be introduced in the carborundum of growth.Therefore, viewed from the angle suppressing to introduce polycrystalline type in carborundum substrate 1 and suppress fault expansion, above-mentioned nitrogen concentration is preferably not less than 1 × 10 18/ cm 3and not higher than 2 × 10 19/ cm 3, and be more preferably not less than 4 × 10 18/ cm 3and not higher than 2 × 10 19/ cm 3, and be further preferably not less than 6 × 10 18/ cm 3and not higher than 1.5 × 10 19/ cm 3.In this case, can both be implemented more reliably in the ohmically reduction of substrate 1 and the suppression (that is, the suppression of warpage) of fault expansion.
Preferably, meet relational expression 100≤D/T≤1000 and 0≤Wb/T≤0.2, wherein, D represents the diameter of front surface 11, and T represents the thickness of substrate 1, and Wb represents the warpage of the back surface in above-mentioned substrate 1.In this case, the present invention is applied to relatively large substrate 1 less in warpage, and following more remarkable effect of the present invention: the probability producing defect in the step forming epitaxial loayer or the process of being used for producing the semiconductor devices can be reduced more significantly.
At this, the reason that the lower limit of above-mentioned D/T is set to 100 is because contribute to the disposal of substrate 1 in device technology or the automatic transmission of substrate 1.In addition, the higher limit of D/T be set to the reason of 1000 be because contribute to the reduction in the warpage of substrate 1 and can reduce substrate 1 break occur probability.Although Wb/T is preferably less, but the reason that the higher limit of Wb/T is set to 0.2 is because the homogenizing of underlayer temperature is easy in the step forming epitaxial loayer, and easy by the correction of warpage during vacuum suction, and therefore, contribute to forming fine pattern by photoetching.
It should be noted that the diameter D of substrate 1 such as can be not less than 110mm and be not more than 300mm.In addition, the thickness T of substrate 1 such as can be not less than 500 μm and be not more than 800 μm.And the warpage Wb of the back surface of substrate 1 such as can be not more than 60 μm, is preferably not more than 40 μm, and is more preferably not more than 20 μm.It should be noted that, refer to the value obtained by following manner in this warpage: calculate least square plane from multiple shift values corresponding with the multiple measurement points being expressed as two-dimensional position data, and calculate the distance between the maximum displacement value and least square plane of the side relative to least square plane and the distance between the maximum displacement value and least square plane of opposite side and.
Although can suppress the warpage of substrate 1 with the heavy thickness T of substrate 1, the thickness T being above 800 μm may cause the problem the scarce capacity as carried out absorption substrate 1 by vacuum in the period such as the disposal of substrate 1, the automatic transmission of substrate 1.In addition, the cost for the material of substrate 1 increases.On the other hand, when the thickness T of substrate 1 is less than 500 μm, may be difficult to substrate 1 be disposed into free-standing substrate 1.In addition, the probability occurred that breaks increases, and warpage may be large.And the productive rate of the semiconductor element that the warpage Wb of the substrate 1 more than 60 μm may cause the film quality of the epitaxial loayer formed on substrate 1 to be deteriorated or be formed on substrate 1 reduces.
In above-mentioned substrate 1, the diameter D of front surface can be not less than substrate 125mm and be not more than 300mm.Viewed from the angle forming productivity ratio higher the step of semiconductor element on substrate 1, the diameter D of substrate 1 expects large as far as possible (such as, be as above not less than 110mm, and be more preferably not less than 125mm).On the other hand, when the diameter D of substrate 1 is more than 300mm, needs the process control of high complexity to suppress the warpage of substrate 1, and the reduction in productivity ratio may be caused.
In above-mentioned substrate 1, the crystal structure of the carborundum in a part for front surface 11 can be 4H type, and this part of front surface 11 can comprise and having relative to { 0001} face is not less than 0.1 ° and is not more than the crystal face of the deflecting angle of 10 °.Alternatively, this part of front surface 11 can comprise and having relative to { 000-1} face is not less than 0.01 ° and is not more than the crystal face of the deflecting angle of 6 °.In this case, when by forming epitaxial loayer form semiconductor element on the front surface of substrate 1, the semiconductor element (such as UMOS410) in Figure 5 with good electrical characteristics can be obtained.
In above-mentioned substrate 1, the crystal structure of the carborundum in a part for front surface 11 can be 4H type, and, this part of front surface 11 can comprise have relative to 03-38} face or its back surface be not more than 4 ° the crystal face of deflecting angle.In this case, when forming oxidation film on the front surface 11 of substrate 1 maybe when forming epitaxial loayer and form oxidation film afterwards on its front surface, the oxidation film with good film quality can be obtained.Therefore, such as, when MOSFET is formed as semiconductor element, the MOSFET with good electrical characteristics can be obtained.In addition, a part for front surface 11 can comprise and having relative to { 01-11} face or its back surface are not more than the crystal face of the deflecting angle of 4 °, or have relative to { 01-12} face or its back surface are not more than the crystal face of the deflecting angle of 4 °.In this case, the oxidation film with film quality good similarly can be obtained.
In above-mentioned substrate 1, the crystal structure of the carborundum in a part for front surface 11 can be 4H type, and this part of front surface 11 can comprise and having relative to { 000-1} face is not less than 0.01 ° and is not more than the crystal face of the deflecting angle of 6 °.In this case, when forming semiconductor element by forming epitaxial loayer on the front surface of substrate 1, the semiconductor element (such as UMOS410 in Figure 5 or DMOS420 in the figure 7) with good electrical characteristics can be obtained.
In substrate 1, can on front surface 11 formation process damaged layer, and this technique damaged layer can have the thickness of 10nm, and more preferably, has the thickness being not more than 5nm.Technique damaged layer is the layer that its lattice produced in the front surface of substrate is out of shape due to the processing of such as grinding or polishing.In carborundum, likely on the direction of base surface, cause fault, and technique damaged layer is possible.Existence and the thickness of evaluation process damaged layer can be come by the tem observation in the cross section formed by division etc.By being set to relatively little by the thickness of the technique damaged layer on front surface 11 thus, the epitaxial loayer with good film quality can be formed on front surface 11.In addition, also can on back surface 12 formation process damaged layer, and technique damaged layer can have the thickness being not more than 200nm, and more preferably, has the thickness being not more than 100nm.By being limited in the thickness of the technique damaged layer on back surface 12 in scope as above, the generation of the fault during heating treatment at back surface 12 place of substrate 1 reliably can be suppressed.As a result, the warpage of substrate 1 can be suppressed.
In addition, as shown in Figure 2, substrate 1 can by the crystal formation of a carborundum (SiC), or as shown in Figure 4, it can be the combined substrate (connected structure of monocrystalline tile substrate 30) comprising base substrate 20 and front surface portion, base substrate 20 is used as intensity retaining part, and front surface portion comprises carborundum and is formed on the front surface of base substrate 20.Front surface portion can be such as the connected structure formed by engaging multiple monocrystalline tile substrate 30 of being made up of carborundum.Above-mentioned intensity retaining part need not be made up of monocrystal SiC, as long as it has enough heat resistances and intensity.In addition, should being only made up of monocrystal SiC at least partially of upper surface of front surface portion.
From the angle of heat resistance and intensity, carborundum is preferably used as the material of the base substrate 20 as intensity retaining part.The carborundum used can be any one by the polycrystalline of vapor deposition growth, the sintered body formed by sintering inorganic source material or organic source material and monocrystalline.(upper surface) at least partially that it will form the front surface of the front surface portion of epitaxial loayer should be made up of monocrystal SiC, because form epitaxial loayer in front surface portion.
When substrate 1 is made up of a slice monocrystal SiC, for the manufacture of substrate 1(single crystal SiC substrate) process can comprise such as following step, crystal growth (SiC single crystal ingot shape one-tenths) (S11), ingot are shaped and processing (S12), ingot section (S13) and grinding (S21), the polishing (S22) of substrate that are obtained by section and clean (S30).Meanwhile, to be shaped by crystal growth (being formed of SiC single crystal ingot) (S11), ingot for the manufacture of the process of combinations thereof substrate and processing (S12), ingot are cut into slices (S13), by is formed from the tile being cut monocrystalline tile substrate by the substrate that obtains of cutting into slices and processes (S14), monocrystalline tile substrate to the combination (S15) of the front surface of base substrate and combined substrate grinding (S21), polishing (S22) and clean (S30).
From a different perspective, manufacture and comprise step according to the method for substrate 1 of the present invention: prepare the ingot (crystal growth step (S11) and ingot forming step (S12)) be made up of carborundum; By ingot section being obtained the substrate (slicing step (S13)) of the front surface diameter that there is front surface and back surface and be not less than 110mm; And by the front surface of substrate and back surface polishing (surface treatment step (S20)).In polishing step (surface treatment step (S20)), by controlling resistance coefficient R in polishing step (surface treatment step (S20)), polishing front surface 11 and back surface 12, the mean value of the surface roughness Ra at front surface 11 place is made to be not more than 0.5nm, and the standard deviation of surface roughness Ra is not more than 0.2nm, and make the mean value of the surface roughness Ra at back surface 12 place be not less than 0.3nm and be not more than 10nm, and the standard deviation of surface roughness Ra is not more than 3nm.Thereby, it is possible to reliably obtain according to substrate 1 of the present invention.
The joint method of closed space sublimation method or use binding agent can be used in the combination between intensity retaining part (base substrate 20) and the monocrystalline tile substrate 30 forming front surface portion and the combination between monocrystalline tile substrate 30.Any one of organic binder bond and inorganic binder can be adopted, as long as the intensity of substrate 1 can be kept.In addition, comprise silicon (Si) and carbon (C) and as heating result formed SiC bond, the polymer of such as Polycarbosilane also can be used as binding agent.Because combined substrate is not limited in the orientation or size of crystal growth, the substrate of the front surface with the planar orientation of expectation and the size of expectation can be obtained.In addition, can be little on thickness because the polycrystalline of cheapness or sintered body or the monocrystalline with many dislocation or defect can be used as intensity retaining part (base substrate 20) and form the monocrystal SiC (monocrystalline tile substrate 30) of front surface portion, so the cost of the material of substrate 1 can be reduced, and cheap substrate 1 can be realized.On the other hand, because the substrate 1 be made up of a slice monocrystal SiC does not require as the tile in combined substrate is formed or combines, so can simplify the process for the manufacture of substrate 1.
Semiconductor device according to the invention (UMOS410 or DMOS420) comprises above-mentioned substrate 1, epitaxial loayer (n -type SiC epitaxial layer 102) and electrode (gate electrode 122, source electrode 121).Epitaxial loayer is formed on the front surface 11 of substrate 1, and is made up of carborundum.Electrode (gate electrode 122, source electrode 121) is formed on epitaxial loayer.In this case, can realize obtaining that defect produces probability reduce and suppress the semiconductor device of manufacturing cost.
Method according to manufacture semiconductor device of the present invention comprises step: prepare above-mentioned substrate (S100); The front surface of substrate 1 is formed the epitaxial loayer (n be made up of carborundum -type SiC epitaxial layer 102) (S200); And on epitaxial loayer, form electrode (electrode forming step (S400)).In this case, by using according to substrate 1 of the present invention, reduce the probability that defect produces, and the cost manufacturing semiconductor device can be suppressed.
In the method for above-mentioned manufacture substrate 1 or the method for manufacture semiconductor device, polishing, polishing etc. can be used as the finishing method of the surface roughness Ra for controlling substrate 1.Specifically, preferably in finishing polish in CMP process the front surface 11 of polished substrate 1, to reduce surface roughness and to reduce technique damaged layer.The abrasive particle used in CMP process is preferably made up of the material softer than carborundum, to reduce surface roughness, and reduces technique damaged layer.Specifically, colloidal silica or aerosil are preferably used as the material of abrasive particle.About the condition of solvent used in CMP process, in order to strengthen chemical reaction, pH is not preferably higher than 4 or be not less than 9.5, and pH is not more preferably higher than 2 or be not less than 10.5.In addition, preferably oxidant is added solvent.The oxidant based on chlorine of such as sym-closene or dichloro isocyanide salt, sulfuric acid, nitric acid, hydrogen peroxide solution can be used as oxidant.
In order to be reduced in the surface roughness Ra at front surface 11 place of substrate 1 and distribute, by viscosities il (mPas) and the flow rate of liquid Q(m of the polishing fluid for finishing polish in the face reducing rough surface Ra 3/ s), and the area S(m of polished surface plate 2), polish pressure P(kPa) and peripheral speed V(m/s) the resistance coefficient R(m that represents 2/ s) (the resistance coefficient R expressed by equation R=η × Q × V/S × P) be preferably not less than 3.0 × E-15 and be not more than 1.0 × E-14.By so controlling the resistance coefficient in polishing step between polisher and substrate 1, can while maintaining suitable polishing velocity in suitable scope control surface roughness Ra, and, the change on distributing can be reduced in the face in.Polisher is contemplated to be resin surface plate or emery cloth, such as polyurethane foam, nonwoven fabrics or suede, and specifically, suede type is preferred.
Polishing, polishing etc. can be used in the back surface 12 of polished substrate 1.The polishing of fine diamond abrasive particle is used preferably to be applied to finishing polish.Although CMP process can be reduced in the surface roughness at polished surface place, disadvantageously, processing cost is than more expensive in additive method, or productivity ratio is in processes lower in additive method.Above-mentioned diamond abrasive grain each there is the grain size being preferably not less than 0.1 μm and being not more than 3 μm.The metal watch panel be made up of tin, ashbury metal etc., resin surface plate or emery cloth can be used as the polisher that will be used for polishing.By using metal watch panel, polishing speed can be improved.Alternatively, by using emery cloth as polisher, the surface roughness at polished surface place can be reduced in.In order to be reduced in the surface roughness Ra at the back surface place of substrate and distribute in the face reducing surface roughness Ra, the resistance coefficient R in finishing polish can be not less than 3.0 × E-18 and be not more than 1.0 × E-17.By controlling resistance coefficient R, in the step of polished substrate 1, the change in the face that can be reduced in the surface roughness at polished surface place while maintaining suitable polishing velocity in distribution.
< example 1>
Following manufacture is by the combined substrate of the example of substrate according to the present invention and the semiconductor element comprising combined substrate, and the productive rate of semiconductor element manufactured by checking.
(manufacture of substrate)
Utilize sublimation method to grow monocrystal SiC, form ingot thus.The seed substrate be made up of monocrystalline silicon carbide and the source material powder be made up of carborundum is introduced in by the container that graphite is formed.Have and be used as seed substrate as (0001) face of first type surface and the SiC single crystal substrate of 50mm diameter.Then, when source material powder is heated, silicon carbide sublimation, and crystallization again on seed substrate.At this, while introducing nitrogen as impurity, crystallization is carried out again.Then, when having the crystal expecting size at seed Grown, stop heating, and, the crystal of monocrystalline silicon carbide is taken out from container.Nitrogen concentration in ingot is 1 × E19/cm 3.Then, utilize periphery grinder to grind crystal growth plane, base substrate surface and the periphery of ingot, and obtain the ingot being made up of SiC and being shaped.
Afterwards, by substrate is cut in the section of the ingot of shaping.Section is performed by using multi-wire saw.In order to will { 0338} be set to substrate surface, and tilted in (0001) face of ingot while 54.7 ° from the bearing of trend of line, ingot is arranged in jigsaw device, and experiences slicing step after section.The thickness of the substrate after section is 250 μm.Then, by cutting the periphery of substrate after section, obtain monocrystalline tile substrate, it has quadrangle two-dimensional shapes, and has the wide size of 20mm length × 30mm.
Then, in order to basis of formation substrate, initially, sublimation method is utilized to be formed the ingot be made up of polycrystalline Si C.By ingot is carried out periphery processing, obtain the shaping ingot with 155mm diameter.By utilizing multi-wire saw to be cut into slices by ingot, obtain the polycrystalline substrates with the thickness of 500 μm.This polycrystalline substrates is used as base substrate.
Then, multiple monocrystalline tile substrate (monocrystalline rectangular substrate) is arranged adjacent one another are in base substrate (at the bottom of polycrystalline back lining), and monocrystalline tile substrate is engaged with each other, and utilizes closed space sublimation method monocrystalline tile substrate and base substrate to be engaged with each other.The combined substrate experience periphery processing of acquisition like this, obtains the substrate (combined substrate) with 150mm diameter and 750 μm of thickness thus.
Afterwards, the bottom surface (the back surface side of base substrate) of combined substrate and tiled surface (wherein, the side of the upper surface of exposed single-crystal tile substrate) experience planarization process successively, obtain the substrate being used for epitaxial process thus.Bottom surface is ground by ciamond grinder, and utilizes diamond slurries to carry out polishing afterwards.For realizing the surface roughness Ra from 0.3 to 10nm in scope according to the present invention and being not more than the mirror finish of standard deviation of 3nm, resistance coefficient is set to 1.0 × E-17m 2/ s to 3.0 × E-18m 2/ s.In example 1 to 6, the resistance coefficient during polishing is set to 5.0 × E-17m 2/ s.Traverse feed type grinder is used for grinding, and the Ceramic bond grinding stone with the concentration ratio of specification #600 and 150 is used as grinding stone.Perform polishing in multiple steps.Copper surface plate and tin surfaces plate are used as surface plate.Adopt the diamond slurries of the grain size of 3 μm and 1 μm.
For the processing of tiled surface, after grinding and polishing, perform CMP.The colloidal silica with the average particle size of 50nm is used as the abrasive particle in the slurries of CMP.Slurries are set to pH2, and it is the acid caused because of nitric acid, and hydrogen peroxide solution is used as oxidant.Suede type is used as emery cloth.Resistance coefficient during CMP is set to 1.0 × E-14m within the scope of this invention 2/ s to 3.0 × E-15m 2/ s.In example 3, it is set to 2.0 × E15m 2/ s.
Then, by changing the condition of the planarization process being used for bottom surface and tiled surface, the substrate sample (sample No.1 to 18) of 18 types different in the surface roughness shown in table 1 described below is manufactured.It should be noted that and can find out in table 1 described below, sample No.1 to 4,9,12 and 15 to 18 is according to example of the present invention, and sample No.5 to 8,10,11,13 and 14 is the samples according to comparative example.
(manufacture of semiconductor element)
Semiconductor element (device) is manufactured by using the substrate of each of above-mentioned sample No.1 to 18.The structure of semiconductor element is set to the UMOS structure of the vertical MOSFET of expression one type.The cross section structure of semiconductor element is identical with the cross section structure of semiconductor element shown in Figure 5.
Specifically, n -type SiC epitaxial layer 102 has the thickness of 10 μm.P-type well area 117 has the thickness of 1.5 μm.P +type trap contact extrinsic region 116 has the thickness of 0.2 μm.N +type source extrinsic region has the thickness of 0.4 μm.Groove has the degree of depth of 3 μm and the width of 3 μm.Silicon oxide film is used as the material for gate insulating film 107, and its thickness is set to 40nm.The alloy of Ti, Ni and Al is used as the material for gate electrode 122, and its thickness is set to 0.5 μm.Polysilicon is used as the material for interlayer dielectric 106, and its thickness is set to 0.4 μm.The alloy of Ni and Si is used as the material for source electrode 121.The alloy of Ni and Si is used as the material for drain electrode 124.Before formation back electrode, on thickness, reduce substrate by back-grinding, leave the single crystalline substrate of 100 μm thus.
In addition, the treatment conditions for the formation of element are arranged for each sample, such as forms the step of epitaxial loayer.
(content of inspection and result)
The semiconductor element formed is checked to the productive rate of each sample.Table 1 illustrates result.
Can find out, the productive rate (device yield) of the semiconductor element of 52% is not less than according to each realization of the sample of example of the present invention, and realize the productive rate of semiconductor device lower than 40% according to each of the sample of comparative example, and therefore productive rate is clearly different.In addition, also good in the characteristic of formed semiconductor element according to the sample of example of the present invention.Namely, can find out, by controlling front surface roughness and the mean value of each of back surface roughness and the standard deviation of substrate, good epitaxially grown layer can be formed in most of large-sized substrate, and the warpage of substrate can be suppressed in suitable scope.Therefore, result, according to example of the present invention, suppresses the generation of defect, improves productive rate, and obtain good device property.
< example 2>
Manufacture combined substrate and comprise the semiconductor element of combined substrate, the planar orientation of monocrystalline tile substrate and different in example 1, and the productive rate of semiconductor element manufactured by inspection.
(manufacture of substrate)
Combined substrate is manufactured, except the planar orientation of monocrystalline tile substrate is set to { except 0001} under the condition identical with the condition in example 1.By controlling the planar orientation of monocrystalline tile substrate in the cut direction of section ingot.The thickness of the substrate after section is 250 μm.Then, be used for the processing conditions of planarization process by adjustment, prepare as the sample of example of the present invention and the sample as comparative example outside scope of the present invention.
(manufacture of semiconductor element)
Be used as example and comparative example each in the substrate of sample, substantially form the semiconductor element with UMOS structure in the same manner as in Example 1.
(content of inspection and result)
Same utilization has, and { 0001} is as the combined substrate of the planar orientation in the first type surface of substrate, in the sample of example according to the present invention, because the control of front surface roughness and back surface roughness, good productive rate and device property can be obtained as in example 1.On the other hand, low according to the sample of example according to sample ratio on productive rate of comparative example.
< example 3>
The substrate be made up of a slice monocrystal SiC the example of substrate according to the present invention is manufactured as follows with the semiconductor element comprising this substrate, and, the productive rate of the semiconductor element manufactured by inspection.
(manufacture of substrate)
Utilize sublimation method to grow the monocrystalline of SiC, form ingot thus.There is (0001) face and be used as seed substrate as the SiC single crystal substrate of first type surface and 100mm diameter.Nitrogen concentration is 6 × E18/cm 3.Then, utilize periphery mill to grind the periphery of crystal growth plane, back lining basal surface and ingot, and acquisition is made up of and the ingot be shaped SiC.
Afterwards, substrate is cut by the ingot of sheet slitting forming.Section is performed by using multi-wire saw.Ingot is cut into slices, makes relative to { face that 0001} has 2 ° of deflecting angles is set to the substrate surface after cutting into slices, and obtains the substrate with 110mm diameter.
Afterwards, back surface and the front surface of the substrate after section experience planarization process successively, obtain the substrate being used for epitaxial process thus.Planarization process is being performed with under those the substantially the same treatment conditions in the process of the combined substrate in above-mentioned example 1.Copper surface plate and tin surfaces plate and emery cloth are used for the back surface of polished substrate.Use the abrasive particle in the diamond slurries of the grain size with 3 μm and 0.5 μm.Resistance coefficient is not less than 6.0 × E-18m 2/ s and be not more than 1.0 × E-17m 2/ s.In addition, after the grinding and polishing of the front surface of substrate, as performed CMP example 1.The colloidal silica with the average particle size of 60nm is used as the abrasive particle in the slurries of CMP.Use the emery cloth of non-woven fabric type.Resistance coefficient during CMP is not less than 3.0 × E-15m 2/ s and be not more than 8.0 × E-15m 2/ s.Then, be used for the processing conditions of planarization process by adjustment, manufacture the substrate sample (sample No.1 to 13) of 13 types shown in table 2 as described below.Note, if see in following table 2, sample No.3,4 and 9 to 13 is according to example of the present invention, and sample No.1,2 and 5 to 8 is the samples according to comparative example.
(manufacture of semiconductor element)
Be used as above-mentioned example and comparative example each in the substrate of sample, substantially form the semiconductor element with UMOS structure in the mode identical with in example 1.
(content of inspection and result)
Formed semiconductor element is checked to the productive rate of each sample.Table 2 shows result.
The good device yield as in example 1 can be realized according to the sample of example of the present invention.That is, by controlling front surface roughness and the mean value of each of back surface roughness and the standard deviation of substrate, good epitaxially grown layer can be formed in most of large-sized substrate, and warpage can in suitable scope.As a result, according to example of the present invention, can device yield be improved, and obtain good device property.
< example 4>
In example 3 described above, the substrate be made up of a slice monocrystal SiC the example of substrate according to the present invention is manufactured as follows with the semiconductor element comprising this substrate, and, the productive rate of the semiconductor element manufactured by inspection.
(manufacture of substrate)
Utilize sublimation method to grow the monocrystalline of SiC, form ingot thus.There is (0001) face and be used as seed substrate as the SiC single crystal substrate of first type surface and 100mm diameter.Nitrogen concentration is 6 × E18/cm 3.Then, utilize periphery mill to grind the periphery of crystal growth plane, back lining basal surface and ingot, and acquisition is made up of and the ingot be shaped SiC.
Afterwards, substrate is cut by the ingot of sheet slitting forming.Section is performed by using multi-wire saw.Ingot is cut into slices, makes relative to { face that 000-1} has 1 ° of deflecting angle is set to the substrate surface after cutting into slices, and obtains the substrate with 130mm diameter.
Afterwards, back surface and the front surface of the substrate after section experience planarization process successively, obtain the substrate being used for epitaxial process thus.Planarization process is being performed with under those the substantially the same treatment conditions in the process of the combined substrate in above-mentioned example 1.Copper surface plate and tin surfaces plate and emery cloth are used for the back surface of polished substrate.Use the abrasive particle in the diamond slurries of the grain size with 3 μm and 0.5 μm.Resistance coefficient is not less than 3.0 × E-18m 2/ s and be not more than 8.0 × E-18m 2/ s.In addition, after the grinding and polishing of the front surface of substrate, as performed CMP example 1.The colloidal silica with the average particle size of 30nm is used as the abrasive particle in the slurries of CMP.Use the emery cloth of suede type.Resistance coefficient during CMP is not less than 6.0 × E-15m 2/ s and be not more than 1.0 × E-14m 2/ s.Then, be used for the processing conditions of planarization process by adjustment, manufacture the substrate sample (sample No.1 to 9) of 9 types shown in table 3 as described below.Note, if see in following table 3, sample No.3,4 and 7 to 9 is according to example of the present invention, and sample No.1,2 and 5 to 6 is the samples according to comparative example.
(manufacture of semiconductor element)
Be used as the substrate of the sample in each of above-mentioned example and comparative example, form the semiconductor element of the DMOS structure shown in having in the figure 7.
Specifically, n -type SiC epitaxial layer 102 has the thickness of 10 μm.P-type well area 117 has the thickness of 1.5 μm.P +type trap contact extrinsic region 116 has the thickness of 0.2 μm.N +type source extrinsic region 111 has the thickness of 0.4 μm.Silicon oxide film is used as the material for gate insulating film 107, and its thickness is set to 40nm.The alloy of Ti, Ni and Al is used as the material for gate electrode 122, and its thickness is set to 0.5 μm.Polysilicon is used as the material for interlayer dielectric 106, and its thickness is set to 0.4 μm.The alloy of Ni and Si is used as the material for source electrode 121.The alloy of Ni and Si is used as the material for drain electrode 124.Before formation back electrode, on thickness, reduce substrate by back-grinding, leave the single crystalline substrate of 100 μm thus.
(content of inspection and result)
Formed semiconductor element is checked to the productive rate of each sample.Table 3 shows result.
Table 3
The good device yield as in example 1 can be realized according to the sample of example of the present invention.That is, by controlling front surface roughness and the mean value of each of back surface roughness and the standard deviation of substrate, good epitaxially grown layer can be formed in most of large-sized substrate, and warpage can in suitable scope.As a result, according to example of the present invention, can device yield be improved, and obtain good device property.
It should be understood that the embodiment disclosed herein and example are illustrative and indefinitenesses in each.Scope of the present invention is limited by the clause of claim instead of above-described embodiment and example, and is intended to be included in any amendment in the scope and implication that are equal to the clause of claim.
Industrial usability
The present invention is applied to the substrate, semiconductor device and the manufacture method thereof that comprise carborundum especially valuably.
Reference numerals list
1 substrate; 11 front surfaces; 12 back surfaces; 20 base substrate; 30 monocrystalline tile substrates; 31 composition surfaces; 102.N -type SiC epitaxial layer; 106 interlayer dielectrics; 107 gate insulating films; 111n +type source extrinsic region; 116p +type trap contact extrinsic region; 117p type well area; 121 source electrodes; 122 gate electrodes; 124 drain electrodes; 410UMOS; And, 420DMOS.

Claims (12)

1. one kind has the substrate (1) of front surface (11) and back surface (12), in described substrate (1), and being made up of monocrystalline silicon carbide at least partially of described front surface (11),
Described substrate has: be not more than 0.5nm, the mean value of surface roughness Ra at described front surface (11) place, and the standard deviation of described surface roughness Ra is not more than 0.2nm; Be not less than 0.3nm and be not more than 10nm, the mean value of surface roughness Ra at described back surface (12) place, and the standard deviation of described surface roughness Ra is not more than 3nm; And be not less than the diameter of described front surface (11) of 110mm.
2. substrate according to claim 1, wherein
Nitrogen concentration in described monocrystalline silicon carbide is not higher than 2 × 10 19/ cm 3.
3. substrate according to claim 2, wherein
Nitrogen concentration in described monocrystalline silicon carbide is not less than 4 × 10 18/ cm 3and not higher than 2 × 10 19/ cm 3.
4. the substrate according to any one in claims 1 to 3, wherein
Meet relational expression 100≤D/T≤1000 and 0≤Wb/T≤0.2, wherein, D represents the diameter of described front surface (11), and T represents the thickness of described substrate (1), and Wb represents the warpage of described back surface (12).
5. the substrate according to any one in claims 1 to 3, wherein
Described front surface (11) has and is not less than 125mm and the diameter being not more than 300mm.
6. the substrate according to any one in claims 1 to 3, wherein
Described front surface (11) described at least partially in the crystal structure of carborundum be 4H type, and
Described the comprising at least partially of described front surface (11) has relative to { 0001} face is not less than 0.1 ° and is not more than the crystal face of the deflecting angle of 10 °.
7. the substrate according to any one in claims 1 to 3, wherein
Described front surface (11) described at least partially in the crystal structure of carborundum be 4H type, and
Described the comprising at least partially of described front surface (11) has relative to { 03-38} face is not more than the crystal face of the deflecting angle of 4 °.
8. the substrate according to any one in claims 1 to 3, wherein
Described front surface (11) described at least partially in the crystal structure of carborundum be 4H type, and
Described the comprising at least partially of described front surface (11) has relative to { 000-1} face is not less than 0.01 ° and is not more than the crystal face of the deflecting angle of 6 °.
9. the substrate (1) according to any one in claims 1 to 3, is made up of a slice monocrystalline silicon carbide.
10. a semiconductor device, comprising:
Substrate (1) according to any one in claim 1 to 9;
Epitaxial loayer (102), described epitaxial loayer is made up of carborundum and is formed on the described front surface (11) of described substrate (1); And
At the upper electrode (122,121) formed of described epitaxial loayer (102).
11. 1 kinds of methods manufacturing substrate, comprise the following steps:
Prepare the ingot (S11, S12) be made up of carborundum;
By described ingot is cut into slices, obtain and there is front surface and back surface and the diameter of described front surface is not less than the substrate (S13) of 110mm; And
The described front surface of substrate described in polishing and described back surface (S20), wherein
In described polishing step (S20), by controlling the resistance coefficient in described polishing step (S20), come front surface described in polishing and described back surface, make to be not more than 0.5nm and the standard deviation of described surface roughness Ra is not more than 0.2nm at the mean value of the surface roughness Ra at described front surface place, and make the mean value of the surface roughness Ra at described back surface place be not less than 0.3nm and be not more than 10nm, and the standard deviation of described surface roughness Ra is not more than 3nm.
12. 1 kinds of methods manufacturing semiconductor device, comprise the following steps:
The substrate (S100) of preparation according to any one in claim 1 to 9;
The described front surface of described substrate is formed the epitaxial loayer (S200) be made up of carborundum; And
Form electrode (S400) on said epitaxial layer there.
CN201280030546.0A 2011-08-05 2012-08-02 Substrate, semiconductor device and manufacture method thereof Active CN103608899B (en)

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