JP7421470B2 - Semiconductor substrate manufacturing method and polishing composition set, etc. - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor substrate, and a polishing composition set and other sets preferably used in the manufacturing method. This application claims priority based on Japanese Patent Application No. 2018-68524 filed on March 30, 2018, and the entire content of that application is incorporated herein by reference.

Semiconductor substrate materials made of silicon, gallium nitride, silicon carbide, etc. are usually cut out from ingots and then processed through lapping and polishing processes to form thin semiconductor substrates (semiconductor wafers) with smooth surfaces. Ru. For example, in the production of silicon carbide semiconductor substrates, after lapping with diamond abrasive grains, or instead of lapping, a polishing pad is used to supply a polishing slurry between the polishing pad and the workpiece. Polishing is performed. The manufactured semiconductor substrate is used as a semiconductor device after an epitaxial growth film (epitaxial film) or the like is formed on its front surface. Patent Documents 1 to 5 are cited as documents disclosing this type of conventional technology.

Japanese Patent Application Publication No. 2013-27960 Japanese Patent No. 6011340 Japanese Patent Application Publication No. 2015-205819 Japanese Patent Application Publication No. 2016-64980 Japanese Patent Application Publication No. 2017-81813

In recent years, higher quality shape control has been required for semiconductor substrates such as silicon carbide. For example, in Patent Document 1, the front surface of a silicon carbide single crystal substrate on which a processing damage layer has been formed is polished, and the back surface thereof is etched to improve the surface roughness of each surface. It has been proposed to suppress the warpage of the substrate while adjusting the Furthermore, in Patent Documents 2 to 5, by adjusting the average value and standard deviation of the surface roughness of the front and back surfaces of a silicon carbide single crystal substrate with a diameter of 110 mm or more, it is possible to form a good epitaxial film and prevent warping. It is described that a substrate with suppressed However, as described in the above-mentioned prior art document, if the surface quality of both sides of the substrate is improved to reduce warpage due to internal factors, then when an epitaxial film etc. is formed on the front surface of the substrate, such The influence of substrate deformation stress caused by external factors such as the formed film becomes more apparent. It has become clear that deformation stress caused by such external factors can be a limiting factor in high-level control of substrate shape after substrate manufacturing or in semiconductor devices.

The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a method for manufacturing a semiconductor substrate in which the shape of the substrate after manufacturing can be highly controlled. Another related object is to provide a polishing composition set, a composition set, and a semiconductor substrate manufacturing set used in the above manufacturing method. Yet another related object is to provide a semiconductor substrate whose shape after manufacture is highly controlled.

According to the present specification, a method for manufacturing a semiconductor substrate is provided that includes a back surface processing step of processing the back surface of a wafer-shaped workpiece. A processing strain layer is present on the back surface that has undergone the back surface processing step. The depth of the strained layer existing on the back surface is greater than the depth of the strained layer on the front surface of the semiconductor substrate, or the strained layer does not exist on the front surface. Compressive stress is generated in a workpiece that will become a semiconductor substrate in accordance with the depth of the processed strain layer. By quantitatively utilizing this effect to set the depth of the backside processing strained layer, it is possible to highly control the shape of the semiconductor substrate after manufacturing or in a semiconductor device. For example, it is possible to make a semiconductor substrate with an epitaxial film or the like formed on its front surface more flat by canceling out the compressive stress caused by the film formed on the front surface and the compressive stress of the processed strained layer on the back surface. can. Thereby, for example, the density of defects such as dislocations in the formed film can be reduced, and the quality of the film can be improved.

In a preferred embodiment of the manufacturing method disclosed herein, the back surface processing step is a step (surface roughness reduction step) in which the arithmetic mean surface roughness Ra of the back surface is set to 10 nm or less. In order to make the front surface a higher quality surface or to perform a higher level of shape control, it is desirable that the surface roughness of the back surface be limited. From such a point of view, in the above configuration, processing is intentionally performed so that the depth of the processed strain layer becomes a predetermined value or more while limiting Ra of the back surface of the substrate to 10 nm or less. As a result, the shape of the semiconductor substrate after manufacturing or in a semiconductor device can be more highly controlled, and a higher quality semiconductor substrate can be obtained.

In a preferred embodiment of the manufacturing method disclosed herein, the depth of the strained layer present on the back surface is 0.1 μm or more. By setting the depth of the processed strain layer to 0.1 μm or more, a high level of control over the shape of the semiconductor substrate can be preferably achieved in typical semiconductor devices in which an epitaxial film of a predetermined thickness is formed on the front surface. can do.

In a preferred embodiment of the manufacturing method disclosed herein, the back surface processing step includes a chemical mechanical polishing step. In another preferred embodiment, the back surface processing step includes a lapping step. In yet another aspect, the back surface processing step includes a grinding step. The effects of the technology disclosed herein are preferably exhibited by employing any one of chemical mechanical polishing (CMP), lapping, and grinding as the back surface processing step.

A preferred embodiment of the manufacturing method disclosed herein includes a front surface processing step of processing a front surface of the workpiece. Further, both the front surface processing step and the back surface processing step include a step using abrasive grains. In one aspect, the abrasive grains used in the back surface processing step have a higher hardness than the abrasive grains used in the front surface processing step. In another embodiment, the abrasive grains used in the back surface processing step have a larger particle size than the abrasive grains used in the front surface processing step. By employing the method described above, it is possible to preferably manufacture a substrate in which the depth of the strained layer on the back side is greater than that on the front side.

In a preferred embodiment of the manufacturing method disclosed herein, the semiconductor substrate is a semiconductor substrate made of silicon carbide. The effects of the technology disclosed herein are preferably exhibited in a semiconductor substrate made of silicon carbide.

Moreover, according to this specification, a polishing composition set used in any of the manufacturing methods disclosed herein is provided. This polishing composition set includes a composition Q1 as a back polishing composition used in the back surface processing step, and a composition Q2 as a front surface polishing composition used in the front surface processing step. including. The composition Q1 and the composition Q2 are stored separately from each other. By performing the back surface processing step and the front surface processing step using a polishing composition set having such a configuration, it is possible to suitably produce a semiconductor substrate whose shape after production is highly controlled. The semiconductor substrate may also have high surface quality.

In a polishing composition set according to a preferred embodiment, the backside polishing composition contains abrasive grains A _{and BF} . Further, the front surface polishing composition contains abrasive grains _AFF . The abrasive grains _ABF are alumina particles or green silicon carbide particles, and the abrasive grains _AFF are silica particles or alumina particles. According to the above configuration, the effects of the technology disclosed herein are preferably achieved.

In a polishing composition set according to a preferred embodiment, the backside polishing composition contains a polishing aid _CBF . Further, the front surface polishing composition contains a polishing aid _CFF . The polishing aid _CBF is permanganic acid or a salt thereof, and the polishing aid _CFF is hydrogen peroxide and vanadate. According to the above configuration, in polishing each of the front and back surfaces of the object to be polished, it is possible to achieve a good balance between polishing rate and surface quality.

Further, according to this specification, a composition set for use in any of the manufacturing methods disclosed herein is provided. This composition set includes composition Q3 as a lapping composition used in the back surface processing step, and composition Q4 as a front surface polishing composition used in the front surface processing step. . The composition Q3 and the composition Q4 are stored separately from each other. By performing the back surface processing step and the front surface processing step using a composition set having such a configuration, a semiconductor substrate whose shape after manufacturing is highly controlled can be manufactured with high processing efficiency. The semiconductor substrate may also have high surface quality.

In a composition set according to a preferred embodiment, the lapping composition contains abrasive grains A _{and BF} . Further, the front surface polishing composition contains abrasive grains _AFF . The abrasive grains _ABF are diamond particles, and the abrasive grains _AFF are silica particles or alumina particles. According to the above configuration, the effects of the technology disclosed herein are preferably achieved.

In a composition set according to a preferred embodiment, the front surface polishing composition contains a polishing aid _CFF . Further, the polishing aid _CFF is at least one selected from the group consisting of permanganic acid, permanganate, hydrogen peroxide, and vanadate. According to the above configuration, in polishing the front surface of the object to be polished, it is possible to achieve a good balance between polishing rate and surface quality.

Further, according to this specification, a semiconductor substrate manufacturing set used in any of the manufacturing methods disclosed herein is provided. This set includes grinding abrasive grains used in the back surface processing step, and composition Q5 as a front surface polishing composition used in the front surface processing step. The grinding abrasive grains and the composition Q5 are stored separately from each other. By performing the back surface processing step and the front surface processing step using a set having such a configuration, a semiconductor substrate whose shape after manufacturing is highly controlled can be manufactured with high processing efficiency. Further, the front surface of the semiconductor substrate may have high surface quality.

In a set according to a preferred embodiment, the grinding abrasive grains are diamond particles, and the abrasive grains _AFF are silica particles or alumina particles. According to the above configuration, the effects of the technology disclosed herein are preferably achieved.

In a set according to a preferred embodiment, the front surface polishing composition contains a polishing aid _CFF . The polishing aid _CFF is at least one selected from the group consisting of permanganic acid, permanganate, hydrogen peroxide, and vanadate. According to the above configuration, in polishing the front surface of the object to be polished, it is possible to achieve a good balance between polishing rate and surface quality.

Also provided according to this specification is a semiconductor substrate. This semiconductor substrate has a front surface and a back surface. A process-strained layer is present on the back surface. Further, the depth of the strained layer existing on the back surface is greater than the depth of the strained layer formed on the front surface, or the strained layer does not exist on the front surface. A semiconductor substrate having such a configuration can have a highly controlled shape after manufacturing or in a semiconductor device. For example, an epitaxial film formed on the front surface of the semiconductor substrate described above can be a substrate with excellent flatness after the film is formed.

Hereinafter, preferred embodiments of the present invention will be described. Note that matters other than those specifically mentioned in this specification that are necessary for implementing the present invention can be understood as matters designed by those skilled in the art based on the prior art in the relevant field. The present invention can be implemented based on the content disclosed in this specification and the common general knowledge in the field.

≪Semiconductor substrate≫
The semiconductor substrate disclosed herein has a front surface and a back surface, and a processed strain layer is present on the back surface. Further, the depth of the process-strained layer existing on the back surface is greater than the depth of the process-strained layer on the front surface, or there is no process-strained layer on the front surface of the semiconductor substrate. Here, the front surface of a semiconductor substrate is the surface on which epitaxial films, semiconductor elements, etc. are normally formed, and the back surface of the semiconductor substrate is the surface located on the opposite side from the front surface. . Note that the shape of the semiconductor substrate is not particularly limited, and usually has a disk shape (circular shape when viewed from the top). The semiconductor substrate may have a polygonal shape such as a quadrangle when viewed from the top.

As the constituent material of the semiconductor substrate, any known semiconductor substrate material can be used without particular limitation. Constituent materials of the semiconductor substrate include, for example, single-element semiconductors such as silicon and germanium; II-VI compound semiconductor substrate materials such as cadmium telluride, zinc selenide, cadmium sulfide, cadmium mercury telluride, and zinc cadmium telluride; nitride III-V compound semiconductor substrate materials such as gallium, gallium arsenide, gallium phosphide, indium phosphide, aluminum gallium arsenide, gallium indium arsenide, nitrogen indium gallium arsenide, aluminum gallium indium phosphide; silicon carbide, silicon IV-IV compound semiconductor substrate materials such as germanium chloride; and the like. It may be made of a plurality of these materials. Among these, it is preferable that the semiconductor substrate is made of silicon carbide. Silicon carbide is expected to be a semiconductor substrate material with low power loss and excellent heat resistance, and the practical advantage of highly controlling the shape of the substrate is particularly large. A semiconductor substrate according to a preferred embodiment has a front surface made of a single crystal of silicon carbide.

A semiconductor substrate according to one embodiment is made of a material having a Vickers hardness of 500 Hv or more. By providing a processed strain layer on the back surface of a semiconductor substrate made of such a high hardness material, the shape of the high hardness substrate can be highly controlled. The Vickers hardness of the constituent material of the semiconductor substrate is preferably 700 Hv or more (for example, 1000 Hv or more, typically 1500 Hv or more). Examples of materials having a Vickers hardness of 1500 Hv or higher include diamond, silicon carbide, silicon nitride, titanium nitride, and gallium nitride. The substrate disclosed herein can have a single crystal surface of the above-described material that is mechanically and chemically stable. Among these, the semiconductor substrate surface is preferably made of one of diamond, silicon carbide, and gallium nitride, and more preferably made of silicon carbide. The upper limit of Vickers hardness is not particularly limited, but may be approximately 7000 Hv or less (for example, 5000 Hv or less, typically 3000 Hv or less). In addition, in this specification, Vickers hardness can be measured based on JIS R 1610:2003. The international standard corresponding to the above JIS standard is ISO 14705:2000.

The semiconductor substrate disclosed herein has a processed strain layer on at least the back surface. In this specification, a "processing strained layer" refers to a layered region defined by considering the depth of processing strain (specifically, processing scratches) formed by processing the surface of a semiconductor substrate as the layer thickness, This is a layer (surface layer) that exists on the surface of a semiconductor substrate. The depth of the processed strain layer can be measured by observation using a differential interference microscope and by polishing. Specifically, it is measured by the method described in Examples below.

The depth of the processed strain layer existing on the back surface of the semiconductor substrate is not limited to a specific range, but is relatively determined in relation to the properties of the front surface. For example, the difference (D _BF - D _FF ) between the depth of the strained layer D _FF [μm] on the front surface and the depth D _BF [μm] of the strained layer on the back surface is determined by the difference in the depth of the strained layer From the viewpoint of obtaining the base deformation stress, it is appropriate that the thickness is approximately 0.1 μm or more. In a preferred embodiment, the difference (D _BF −D _FF ) is about 0.2 μm or more, more preferably about 0.3 μm or more, for example about 0.5 μm or more (typically about 0.7 μm or more). It may be approximately 1 μm or more (for example, approximately 1.3 μm or more). The above difference (D _BF −D _FF ) is the difference between a typical semiconductor in which an epitaxial film of a predetermined thickness (for example, about 5 to 50 μm thick, typically about 10 to 30 μm thick) is formed on the front surface. Suitable for devices. In another aspect, the difference (D _BF −D _FF ) is approximately 2 μm or more, for example, may be approximately 3 μm or more, or may be approximately 3.5 μm or more (for example, approximately 3.8 μm or more). good. Such a difference is preferably adopted for a semiconductor substrate whose front surface becomes convex after manufacturing and whose deformation stress is relatively large.

Further, it is appropriate that the difference (D _BF −D _FF ) is, for example, about 10 μm or less. In a preferred embodiment, the difference (D _BF −D _FF ) is approximately 5 μm or less, more preferably approximately 2.5 μm or less (eg, approximately 2 μm or less), such as approximately 1.2 μm or less (typically approximately 1 μm). or less), or approximately 0.7 μm or less (for example, approximately 0.5 μm or less). The above difference (D _BF −D _FF ) is the difference between a typical semiconductor in which an epitaxial film of a predetermined thickness (for example, about 5 to 50 μm thick, typically about 10 to 30 μm thick) is formed on the front surface. Suitable for devices. In another embodiment, the difference (D _BF −D _FF ) is approximately 4.5 μm or less, for example, may be approximately 4 μm or less, or may be approximately 3.5 μm or less. Note that when there is no process-strained layer on the front surface, the difference (D _BF -D _FF ) is determined by setting the process-strained layer depth D _FF to 0 μm.

The depth of the process-strained layer on the back side of the semiconductor substrate is not particularly limited, except that it is greater than the depth on the front side when the process-strained layer is present on the front side. For example, the processing strain layer depth D _BF on the back surface is suitably about 0.1 μm or more, preferably about 0.2 μm or more, more preferably about 0.3 μm or more, for example, about 0.5 μm. or more (typically about 0.7 μm or more), or about 1 μm or more (for example, about 1.3 μm or more). The processed strain layer depth _DBF is defined as the depth DBF of a typical semiconductor device in which an epitaxial film of a predetermined thickness (for example, about 5 to 50 μm thick, typically about 10 to 30 μm thick) is formed on the front surface. suitable. In another aspect, the processed strain layer depth D _BF is approximately 2 μm or more, for example, may be approximately 3 μm or more, or approximately 3.5 μm or more (for example, approximately 3.8 μm or more). The above processing strain layer depth D _BF is preferably adopted for a semiconductor substrate in which the deformation stress that causes the front surface to become convex after manufacturing is relatively large.

Further, it is appropriate that the depth _DBF of the processed strain layer on the back surface is, for example, about 10 μm or less. In a preferred embodiment, the depth _DBF of the strained layer is approximately 5 μm or less, more preferably approximately 2.5 μm or less (e.g., approximately 2 μm or less), and, for example, approximately 1.2 μm or less (typically approximately 1 μm or less). ), or approximately 0.7 μm or less (for example, approximately 0.5 μm or less). The strained layer depth _DBF in the above range is typical for forming an epitaxial film with a predetermined thickness (for example, about 5 to 50 μm thick, typically about 10 to 30 μm thick) on the front surface. Suitable for semiconductor devices. In another embodiment, the depth of the strained layer D _BF is approximately 4.5 μm or less, for example, may be approximately 4 μm or less, or may be approximately 3.5 μm or less.

When a strained layer exists on the front surface of the semiconductor substrate, there is no particular restriction on the depth _DFF of the strained layer on the front surface as long as it is smaller than the depth _DBF of the strained layer on the back surface. For example, the depth D _FF of the processed strain layer on the front surface is suitably less than 10 μm, preferably less than 5 μm, more preferably less than 1 μm, and even more preferably less than 0.3 μm (for example, less than 0.1 μm). It is. The lower limit of the processing strain layer depth _DFF on the front surface is 0 μm or more (for example, more than 0 μm), and may be about 0.1 μm or more. Such a front surface can easily be a high-quality surface, and is suitable for a typical semiconductor device in which an epitaxial film of a predetermined thickness is formed on the front surface.

The arithmetic mean surface roughness Ra of the front surface of the semiconductor substrate disclosed herein is set according to the required surface quality, and is not limited to a specific range. For example, it is appropriate that the above Ra is about 10 nm or less, and in applications that require higher quality surfaces, it is preferably less than 5 nm, more preferably less than 1 nm, even more preferably less than about 0.3 nm, especially Preferably it is less than 0.1 nm (for example less than 0.07 nm, typically about 0.05 nm). The lower limit of Ra of the front surface may be, for example, 0.01 nm or more.

The arithmetic mean surface roughness Ra of the back surface of the semiconductor substrate disclosed herein is not particularly limited, and is usually approximately 20 nm or less. Ra of the back surface according to a preferred embodiment is approximately 10 nm or less (typically less than 10 nm), more preferably less than 5 nm, for example, may be less than 3 nm, may be less than 2 nm, and may be less than 1 nm. (for example, less than 0.3 nm, typically about 0.1 nm). From the viewpoint of productivity and the like, the lower limit of Ra on the back surface may be, for example, about 0.05 nm or more, about 0.5 nm or more, or about 1 nm or more.

Ra of the front surface and the back surface of the semiconductor substrate can be measured using a commercially available atomic force microscope under conditions of a measurement area of 10 μm×10 μm. More specifically, it can be measured by the method described in Examples below.

The longer the length of the semiconductor substrate and the smaller the thickness of the substrate, the greater the influence of deformation such as warping during subsequent processing for semiconductor device manufacturing (formation of epitaxial films, semiconductor elements, etc.). Cheap. The effects of applying the technology disclosed herein to such a semiconductor substrate are preferably exhibited. From this point of view, it is appropriate that the ratio (L/T) of the substrate length (longest length; diameter in the case of a disk shape) L [mm] to the substrate thickness T [mm] be approximately 50 or more. It is preferably about 100 or more, more preferably about 150 or more, still more preferably about 200 or more, and may be about 250 or more, for example. In addition, from the viewpoint of substrate strength and handleability, the upper limit of the ratio (L/T) is, for example, approximately 600 or less, preferably approximately 400 or less, more preferably approximately 300 or less, for example approximately 250. The following may be sufficient.

The length (maximum length; diameter in the case of a disk shape) of the semiconductor substrate disclosed herein is not limited to a specific range. From the viewpoint of obtaining favorable effects from the technology disclosed herein, the length of the substrate is, for example, approximately 20 mm or more, preferably approximately 45 mm or more, more preferably approximately 70 mm or more, for example, approximately It may be 100 mm or more, about 200 mm or more, about 300 mm or more, or about 450 mm or more. The large-diameter semiconductor substrate described above also has excellent production efficiency. Further, the upper limit of the length of the semiconductor substrate is, for example, approximately 500 mm or less, and from the viewpoint of substrate strength and handleability, it is preferably approximately 300 mm or less, more preferably approximately 220 mm or less, and even more preferably approximately It is 120 mm or less (for example, less than 110 mm), for example, it may be about 100 mm or less, or it may be about 80 mm or less.

The thickness of the semiconductor substrate is appropriately set depending on the size (diameter, etc.). The thickness of the substrate is usually about 100 μm or more, suitably about 300 μm or more (for example, about 350 μm or more), and may be about 500 μm or more, for example. Further, the above-mentioned thickness is usually about 1500 μm or less, suitably about 1000 μm or less, preferably about 800 μm or less, for example, about 500 μm or less (typically less than 500 μm). It may be approximately 400 μm or less.

The entire surface of the semiconductor substrate disclosed herein may be warped in an arc shape so that the front surface side is concave due to compressive stress caused by the processed strain layer. By forming a film such as an epitaxial film on the front surface of a semiconductor substrate where such deformation stress exists, the deformation caused by the compressive stress of the film formed on the front surface and the intentionally created back surface can be avoided. This is offset by the compressive stress of the processed strain layer, and the semiconductor substrate can have a highly controlled shape in a semiconductor device. For example, a semiconductor substrate having an epitaxial film or the like formed on its front surface can be made more flat, and the density of defects such as dislocations in the formed film can be reduced and the film quality can be improved.

For the warpage in which the front surface is concave, for example, it is appropriate that the depth of the concave is approximately 0.5 μm or more, preferably approximately 1 μm or more, more preferably approximately 3 μm or more, and still more preferably approximately 5 μm or more. For example, it may be about 6 μm or more, or about 8 μm or more. Further, the upper limit of the depth of the recess is usually less than 50 μm, suitably about 20 μm or less (for example, less than 20 μm), preferably about 15 μm or less, more preferably about 12 μm or less, e.g. It may be approximately 10 μm or less, approximately 8 μm or less, or approximately 6 μm or less. A semiconductor substrate having such a warp is a typical semiconductor device in which an epitaxial film of a predetermined thickness (for example, about 5 to 50 μm thick, typically about 10 to 30 μm thick) is formed on the front surface. It is suitable for

The warpage of the front surface of a semiconductor substrate can be evaluated, for example, as GBIR (Global backside ideal range) in the SEMI (Semiconductor equipment and materials international) standard. In GBIR, the back surface of the wafer is fully attracted to a flat chuck surface, and the back surface is used as a reference surface, and the height from the reference surface is measured for the entire surface of the wafer, and the distance from the highest height to the lowest height is expressed. It is something. GBIR can be measured using a known surface profile measuring device. For example, a surface profile measuring machine "SURFCOM 1500DX" manufactured by Tokyo Seimitsu Co., Ltd. can be used. Specifically, it can be measured by the method described in Examples below.

≪Method for manufacturing semiconductor substrate≫
<Processing object>
Next, a method for manufacturing a semiconductor substrate disclosed herein will be explained. In this manufacturing method, a workpiece is first prepared. Although not particularly limited, the workpiece used is a wafer-shaped object obtained by cutting an ingot of a semiconductor material by a technique such as slicing. As the constituent material of the workpiece, those exemplified as the above-mentioned semiconductor substrate material can be used without particular limitation, and the preferred example of the semiconductor substrate material is also a suitable example of the constituent material of the workpiece. The shape and size of the workpiece (shape and size when viewed from above) are similar to the semiconductor substrate to be manufactured. The thickness of the workpiece is appropriately set so as to obtain the thickness of the semiconductor substrate to be manufactured, so it is not limited to a specific range.

<Back side processing process>
The semiconductor substrate manufacturing method disclosed herein is characterized by including a backside processing step of processing the backside of a wafer-shaped workpiece. Here, the back surface of the object to be processed is the back surface of the semiconductor substrate to be manufactured. The back surface processing step disclosed herein is not limited to a specific step, and is performed by appropriately selecting a known surface processing technique so that a processed strain layer is present on the back surface of the manufactured semiconductor substrate. In addition, when a process-strained layer exists on the front surface of the semiconductor substrate, the back surface is processed so that a process-strained layer having a depth greater than the depth of the process-strained layer on the front surface of the semiconductor substrate exists. The process is carried out. Specifically, the back surface processing step is performed in consideration of the material, structure, thickness, etc. of the formed film such as an epitaxial film provided on the front surface of the manufactured semiconductor substrate. Further, it is preferable that the depth of the strained layer existing on the back surface after the back surface processing step is determined based on the compressive stress that may occur on the front surface of the manufactured semiconductor substrate. Such compressive stress can be determined, for example, by the material, structure, thickness, etc. of a formed film such as an epitaxial film provided on the front surface.

The back surface processing process is not particularly limited, and may be a grinding or polishing process such as a grinding process, a lapping process, or a CMP process. A grinding process, a lapping process, a CMP process, etc. may be carried out individually, or two or more processes may be carried out in combination.

(abrasive grains for back side processing)
The back surface processing process typically includes a process using abrasive grains (eg, a grinding process, a lapping process, a CMP process). The material and properties of the abrasive grains A _{to BF} used in the back surface processing step are not particularly limited. For example, the abrasive grains A _{to BF} can be any of inorganic particles, organic particles, and organic-inorganic composite particles. For example, oxide particles such as silica particles, alumina particles, cerium oxide particles, chromium oxide particles, titanium dioxide particles, zirconium oxide particles, magnesium oxide particles, manganese dioxide particles, zinc oxide particles, iron oxide particles; silicon nitride particles, nitride Substantially composed of any of the following: nitride particles such as boron particles; carbide particles such as silicon carbide particles, green silicon carbide (GC) particles, and boron carbide particles; diamond particles; carbonates such as calcium carbonate and barium carbonate; Examples include abrasive grains. Abrasive grains A _{and BF} may be used alone or in combination of two or more. Among these, diamond particles are preferred from the viewpoint of forming a strained layer.

In this specification, regarding the composition of abrasive grains, "substantially consists of X" or "substantially consists of X" means that the proportion of X in the abrasive grains (purity of X) is It is 90% or more (preferably 95% or more, more preferably 97% or more, still more preferably 98% or more, for example 99% or more) on a standard basis.

In an embodiment in which the front surface processing step described below uses abrasive grains A _FF , the abrasive grains A _BF used in the back surface processing step have a higher hardness than the abrasive grains A _FF used in the front surface processing step. It is preferable. Thereby, it is possible to preferably manufacture a substrate in which the depth of the processed strain layer on the back side is larger than that on the front side. The difference (H _BF - H _FF ) between the Vickers hardness H _{BF (} Hv) of the abrasive grain A BF and the Vickers hardness H _FF (Hv) of the abrasive grain A _FF is not particularly limited, but is, for example, about 100 Hv or more (for example, about 500 Hv). (Typically, it is appropriate to set it to about 700 Hv or more). In another preferred embodiment, the difference (H _BF −H _FF ) is about 1000 Hv or more (for example, about 1200 Hv or more, typically about 1800 Hv or more), more preferably about 3000 Hv or more (for example, about 3500 Hv or more, typical In general, it is approximately 4000 Hv or more). The upper limit of the above difference (H _BF −H _FF ) is not particularly limited, and for example, it is appropriate to set it to about 10,000 Hv or less (for example, about 9,000 Hv or less), and from the viewpoint of the surface smoothness of the back surface, it is preferably about 5,000 Hv or less. (eg, about 4000 Hv or less, typically about 3500 Hv or less), more preferably about 2000 Hv or less (eg, about 1500 Hv or less, typically about 1000 Hv or less).

The hardness of the abrasive grains _ABF is not particularly limited. From the viewpoint of adjusting the depth of the processing strain layer on the back side to a suitable range, the Vickers hardness H _BF (Hv) of the abrasive grains A _BF is, for example, about 1000 Hv or more (for example, about 1200 Hv or more, typically about 1500 Hv or more). ), preferably about 2,000 Hv or more (eg, about 2,200 Hv or more, typically about 2,400 Hv or more), more preferably about 4,000 Hv or more. Further, the Vickers hardness H _BF (Hv) is preferably about 12,000 Hv or less (for example, about 10,000 Hv or less), and preferably about 5,000 Hv or less (for example, about 4,000 Hv or less) from the viewpoint of the surface smoothness of the back surface. , typically about 3000 Hv or less), more preferably about 2500 Hv or less (eg, about 2000 Hv or less, typically about 1700 Hv or less).
The Vickers hardness of the abrasive grains is a value measured based on the above JIS R 1610:2003 for the material used as the abrasive grains.

In an embodiment in which the front surface processing step described below uses abrasive grains A _FF , the abrasive grains A _BF used in the back surface processing step have a larger particle size than the abrasive grains A _FF used in the front surface processing step. Thereby, it is possible to preferably manufacture a substrate in which the depth of the processed strain layer on the back side is larger than that on the front side. In such an embodiment, the ratio of the particle diameter P _BF of the abrasive grains A _BF to the particle diameter P _FF of the abrasive grains A _FF (P _BF /P _FF ) is suitably larger than 1. In a preferred embodiment, the ratio (P _BF /P _FF ) is approximately 2 or more, may be approximately 3 or more (e.g., approximately 4 or more), may be approximately 5 or more, and may be approximately 8 or more (e.g., approximately 4 or more). 9 or more), or approximately 20 or more (for example, 25 or more). The upper limit of the ratio (P _BF /P _FF ) is not particularly limited, and may be approximately 100 or less (for example, 50 or less), approximately 30 or less, approximately 15 or less, or approximately It may be 10 or less (for example, approximately 5 or less).

The particle diameter _PBF of the abrasive grains _ABF is not particularly limited. From the viewpoint of adjusting the depth of the processing strain layer on the back side to a suitable range, it is appropriate that the particle diameter P _BF of the abrasive grains A _BF is approximately 0.05 μm or more, preferably approximately 0.2 μm or more, More preferably, it is approximately 0.3 μm or more, and may be, for example, approximately 0.4 μm or more. In another preferred embodiment, the particle size P _BF of the abrasive grains A _BF is approximately 0.8 μm or more, more preferably approximately 2 μm or more, and even more preferably approximately 2.5 μm or more. Further, the upper limit of the particle diameter _PBF of the abrasive grains _ABF is not particularly limited, and is suitably about 10 μm or less, preferably about 5 μm or less. In another preferred embodiment, the particle diameter P _BF of the abrasive grains A _BF is approximately 2 μm or less, more preferably approximately 1.5 μm or less, and even more preferably approximately 1.2 μm or less. In yet another preferred embodiment, the particle diameter P _BF of the abrasive grains A _BF is approximately 0.7 μm or less, more preferably approximately 0.5 μm or less, and even more preferably approximately 0.3 μm or less.
Note that the particle diameter _PBF of the abrasive grains _ABF mentioned here can be measured by various methods described below. When the abrasive grains _ABF have primary and secondary particle diameters, the value of the secondary particle diameter is defined as the particle diameter _PBF .

(Grinding process)
The back surface processing step according to a preferred embodiment includes a grinding step. In this specification, the "grinding process" refers to a process performed by arranging fixed abrasive grains on a surface plate and pressing the fixed abrasive grains against the surface of the workpiece. Fixed abrasive grains are usually aggregates of abrasive grains hardened with a binder such as vitrified or resinoid, and are also called grinding wheels. Abrasive grains are usually dispersed and fixed in a binder. Further, as the surface plate used in this step, any known or commonly used surface plate can be used. The grinding process is carried out while supplying a machining liquid consisting of an aqueous solution as necessary.

The abrasive grains A to _BF used in the grinding process include one or more of the abrasive grain types for back surface processing exemplified above. Diamond particles are a suitable example of the abrasive grains _ABF used in the grinding process. Further, the content of the abrasive grains A _{to BF} in the fixed abrasive grains is not particularly limited, and an appropriate range is adopted based on common technical knowledge. Note that grinding using a grinding wheel such as a diamond wheel is sometimes referred to as wheel grinding.

The particle diameter _PBF of the abrasive grains _ABF used in the grinding process is not particularly limited. From the viewpoint of adjusting the depth of the process-strained layer on the back surface side to a suitable range, it is appropriate that the particle diameter _PBF of the abrasive grains _ABF used in this step is approximately 0.1 μm or more. In a preferred embodiment, the particle size P _BF of the abrasive grains A _BF is approximately 0.2 μm or more, and may be approximately 0.3 μm or more, for example. In another preferred embodiment, the particle size P _BF of the abrasive grains A _BF is approximately 0.8 μm or more, for example, may be approximately 2 μm or more, or may be approximately 2.5 μm or more. Further, the upper limit of the particle diameter _PBF of the abrasive grains _ABF is not particularly limited, and is suitably about 10 μm or less, preferably about 5 μm or less. In another preferred embodiment, the particle diameter P _BF of the abrasive grains A _BF is approximately 2 μm or less, more preferably approximately 1 μm or less, and still more preferably approximately 0.7 μm or less.

The particle size of the abrasive grains used in the grinding process is the average particle size based on the electrical resistance test method (JIS R6002). The average particle diameter can be determined using, for example, "Multisizer III" manufactured by Beckman Coulter.

Note that when the back surface processing step is composed of a plurality of processing steps including a grinding step, the grinding step may be the final step of the back surface processing step. In that case, there is no machining process after the grinding process in the back surface machining process.

(wrapping process)
The back surface processing step according to a preferred embodiment includes a wrapping step. In this specification, the "lapping process" is performed by placing a carrier (also referred to as a carrier plate) holding an object to be polished between opposing polishing plates and rotating at least one of the polishing plate and the carrier. Refers to the processing process. The polishing surface plate and/or the carrier are rotated so that both rotate relative to each other. The lapping process is typically performed by supplying free abrasive grains (for example, diamond particles) between the polishing surface plate and the workpiece. Free abrasive grains are usually supplied to a workpiece in the form of a liquid composition containing a solvent such as water, which is called a polishing slurry. No polishing pads are used in the lapping process.

The polishing plate used in the lapping process disclosed herein is usually made of metal. Polishing surface plates used for lapping are required to have properties that are easy to process in order to maintain the accuracy of the surface plate surface (the surface facing the workpiece). For this reason, a polishing surface plate in which at least the surface of the surface plate is made of a metal such as cast iron, tin, a tin alloy, copper, or a copper alloy is preferably used. As a polishing surface plate, a surface plate with grooves formed on the surface thereof is sometimes used for the purpose of stably supplying the polishing composition and adjusting the processing pressure. The shape and depth of the grooves are arbitrary, and for example, grooves in a lattice shape or radially can be used.

The abrasive grains A _{to BF} used in the lapping process include one or more of the abrasive grains for back surface processing exemplified above. A suitable example of the abrasive grains _ABF used in this step is diamond grains. The content of abrasive grains A _{to BF} in the lapping composition is not particularly limited, and an appropriate range is adopted based on common technical knowledge. For example, the content of abrasive grains _ABF in the lapping composition is suitably about 1% by weight or more, preferably about 5% by weight or more, and about 50% by weight or less, preferably about 5% by weight or more. It is 30% by weight or less.

The particle size _PBF of the abrasive grains _ABF used in the lapping process is not particularly limited. From the viewpoint of adjusting the depth of the process-strained layer on the back side to a suitable range, it is appropriate that the particle diameter P _BF of the abrasive grains A _BF used in this step is approximately 0.1 μm or more, preferably approximately 0.1 μm or more. It is 0.2 μm or more. In another preferred embodiment, the particle size P _BF of the abrasive grains A _BF is approximately 0.8 μm or more, for example, may be approximately 2 μm or more, or may be approximately 2.5 μm or more. Further, the upper limit of the particle diameter P _BF of the abrasive grains A _BF is not particularly limited, and it is appropriate to set it to about 10 μm or less, preferably about 5 μm or less, more preferably about 2 μm or less, and even more preferably about 1.2 μm. It is as follows. In another preferred embodiment, the particle diameter P _BF of the abrasive grains A _BF is approximately 2 μm or less, more preferably approximately 0.3 μm or less. The particle size of the abrasive grains used in the lapping process can be measured in the same manner as the particle size of the abrasive grains used in the grinding process. The same applies to the embodiments described below.

Note that when the back surface processing step is composed of a plurality of processing steps including a lapping step (for example, a plurality of processing steps including a grinding step), the lapping step may be the final step of the back surface processing step. In that case, there is no processing step after the lapping step in the back surface processing step.

(CMP process)
The back surface processing step according to a preferred embodiment includes a CMP step. As used herein, the term "chemical mechanical polishing (CMP) process" refers to a polishing process performed by using a polishing pad and supplying a polishing slurry between the polishing pad and the workpiece. By employing the CMP process, it is easy to obtain a high-quality back surface.

The CMP step is preferably performed by supplying a polishing slurry (also referred to as polishing liquid) made of a polishing composition as described below to the surface of the workpiece. Specifically, the polishing liquid is supplied to the surface of the workpiece, and the workpiece is polished by a conventional method. For example, a workpiece is set in a general polishing device, and the polishing liquid is supplied to the surface (surface to be polished) of the workpiece through a polishing pad of the polishing device. Typically, while continuously supplying the polishing liquid, a polishing pad is pressed against the back surface of the workpiece and the two are moved relative to each other (for example, rotated).

(Composition for back surface polishing)
The composition for back polishing disclosed herein is not limited to a specific composition, and may have a composition that can cause a strained layer to exist on the back surface that has undergone a back processing step performed using the composition for back polishing, or a composition that can be mainly used. When a strained layer is present on the front surface, a composition is adopted that allows a strained layer having a depth greater than the depth of the strained layer on the front surface to be present on the back surface. Such a back polishing composition includes, for example, abrasive grains _ABF , a solvent such as water, and may further include a polishing aid _CBF such as an oxidizing agent.

As the abrasive grains A _{and BF} for the CMP process on the back surface, one or more of the types of abrasive grains for processing the back surface exemplified above can be used. A preferable example of the abrasive grains _ABF used in this step is alumina particles. One type of alumina particles may be used alone, or two or more types may be used in combination. From the viewpoint of processability, the alumina particles preferably contain α-alumina, and more preferably contain α-alumina as a main component (the component contained in the largest amount among the constituent components). In another preferred embodiment, GC is used as the abrasive grains _ABF .

As the abrasive grains A _{to BF} contained in the back polishing composition, those having an average secondary particle diameter of more than 0.01 μm can be preferably used. From the viewpoint of polishing efficiency, etc., the average secondary particle diameter of the abrasive grains A _BF is preferably 0.05 μm or more, more preferably 0.1 μm or more, even more preferably 0.2 μm or more, particularly preferably 0.3 μm or more. be. By using abrasive grains A _{to BF} having the above average secondary particle diameter, it is easy to adjust the depth of the processing strain layer on the back surface to a suitable range. The upper limit of the average secondary particle diameter of the abrasive grains _ABF is not particularly limited, and it is appropriate to set it to approximately 5 μm or less. For example, from the viewpoint of polishing efficiency and surface quality, abrasive grains _ABF with an average secondary particle size of 0.05 μm or more and 5 μm or less are preferable, abrasive grains A _BF with an average secondary particle size of 0.1 μm or more and 3 μm or less, and 0.3 μm or more and 1 μm or less. The following abrasive grains A and _BF are particularly preferred. For example, abrasive grains A _{to BF} having an average secondary particle diameter of 0.4 μm or more and 0.8 μm or less may be used.

Note that the average secondary particle diameter of the abrasive grains A _{to BF} used in the CMP process is measured based on a laser diffraction scattering method unless otherwise specified. The measurement can be performed using a laser diffraction/scattering particle size distribution analyzer (trade name "LA-950") manufactured by Horiba, Ltd.

The content of abrasive grains A _{and BF} (if multiple types of abrasive grains are included, their total content) in the composition for back polishing is not particularly limited, but is typically 0.1% by weight or more. From the viewpoint of shortening processing time, the content is preferably 0.5% by weight or more, more preferably 1% by weight or more, and even more preferably 3% by weight or more. By including a predetermined amount or more of abrasive grains _ABF , the depth of the processing strain layer on the back surface can be easily adjusted to a suitable range. From the viewpoint of polishing stability and cost reduction, the content of abrasive grains _ABF is usually suitably 20% by weight or less, preferably 15% by weight or less, more preferably 12% by weight or less, and even more preferably It is 10% by weight or less. The technology disclosed herein is preferably in an embodiment in which the content of abrasive grains A _BF in the back polishing composition is, for example, 0.1% by weight or more and 20% by weight or less (preferably 3% by weight or more and 8% by weight or less). can be implemented.

The backside polishing composition disclosed herein preferably includes a polishing aid (typically an oxidizing agent) _CBF . The polishing aid _CBF is a component that enhances the effect of polishing, and is typically water-soluble. Although the polishing aid _CBF is not interpreted to be particularly limited, it exhibits the effect of modifying the surface of the workpiece during polishing (for example, oxidative modification), and weakens the surface of the workpiece, thereby making it difficult to polish. It is thought that grain A _BF contributes to polishing.

As the polishing aid C _BF , peroxides such as hydrogen peroxide; nitric acid compounds such as nitric acid, its salts iron nitrate, silver nitrate, aluminum nitrate, and its complex cerium ammonium nitrate; potassium peroxomonosulfate, peroxodi Persulfuric acid such as sulfuric acid, its salts ammonium persulfate, persulfate compounds such as potassium persulfate; chlorine compounds such as chloric acid and its salts, perchloric acid, and its salt potassium perchlorate; bromate and its salts Bromine compounds such as potassium bromate; iodic acid, its salts ammonium iodate, periodic acid, its salts sodium periodate, potassium periodate, and other iodine compounds; ferric acid, its salts Ferric acids such as potassium ferrate; permanganic acid and its salts such as sodium permanganate and potassium permanganate; chromic acid and its salts such as potassium chromate and potassium dichromate; Vanadate, such as ammonium vanadate, sodium vanadate, sodium metavanadate, potassium vanadate, etc.; Ruthenic acid, such as perruthenic acid or its salt; Molybdic acid, ammonium molybdate, molybdenum, its salt. Examples include molybdic acids such as disodium acid; rhenium acids such as perrhenium or its salts; tungstic acids such as tungstic acid and disodium tungstate, which is a salt thereof. These may be used alone or in an appropriate combination of two or more. Among these, permanganic acid or a salt thereof, peroxide, vanadate or a salt thereof, and periodic acid or a salt thereof are preferable from the viewpoint of polishing efficiency, etc., and sodium permanganate and potassium permanganate are particularly preferable.

In a preferred embodiment, the back polishing composition contains a composite metal oxide as the polishing aid _CBF . Examples of the above-mentioned composite metal oxides include metal nitrates, ferric acids, permanganic acids, chromic acids, vanadic acids, ruthenic acids, molybdic acids, rhenic acids, and tungstic acids. Among these, ferrous acids, permanganic acids, and chromic acids are more preferred, and permanganic acids are even more preferred.

In a further preferred embodiment, the composite metal oxide has a monovalent or divalent metal element (excluding transition metal elements) and a fourth period transition metal element in the periodic table. CMO is used. Preferred examples of the monovalent or divalent metal elements (excluding transition metal elements) include Na, K, Mg, and Ca. Among these, Na and K are more preferred. Preferred examples of transition metal elements in the fourth period of the periodic table include Fe, Mn, Cr, V, and Ti. Among these, Fe, Mn, and Cr are more preferred, and Mn is even more preferred.

When the back polishing composition disclosed herein contains a composite metal oxide (preferably a composite metal oxide CMO) as the polishing aid _CBF , it may further contain a polishing aid _CBF other than the composite metal oxide. Well, it doesn't have to be included. The technology disclosed herein is such that the back polishing composition substantially contains a polishing aid (for example, hydrogen peroxide) other than a composite metal oxide (preferably a composite metal oxide CMO) as _a polishing aid _CBF . It may also be preferably implemented in an embodiment that does not include the above.

The concentration (content) of the polishing aid _CBF in the backside polishing composition is usually 0.1% by weight or more. From the viewpoint of achieving both polishing rate and flatness at a high level and efficiently, the concentration is preferably 0.3% by weight or more, more preferably 0.5% by weight or more (for example, 0.8% by weight or more). In addition, from the viewpoint of improving smoothness, the concentration of the polishing aid _CBF is usually appropriate to be 10% by weight or less, preferably 8% by weight or less, and 6% by weight or less (for example, 5% by weight or less). % by weight or less, or 3% by weight or less).

The composition for back polishing disclosed herein may contain a chelating agent, a thickener, a dispersant, a surface protectant, a wetting agent, a pH adjuster, and a surfactant within a range that does not impair the effects of the technology disclosed herein. , organic acids, organic acid salts, inorganic acids, inorganic acid salts, rust inhibitors, preservatives, antifungal agents, etc., polishing compositions (typically semiconductor substrate polishing compositions, e.g. silicon carbide substrate polishing). If necessary, the composition may further contain known additives that can be used in the composition. The content of the above-mentioned additive may be appropriately set depending on the purpose of addition, and does not characterize the present invention, so a detailed explanation will be omitted.

The pH of the backside polishing composition is usually approximately 8.0 to 12. When the pH of the back polishing composition is within the above range, a practical polishing rate can be easily achieved and handling is easy. The pH of the back polishing composition is preferably 8.0 to 11, more preferably 8.0 to 10, particularly preferably 8.5 to 9.5 (for example, about 9.0).

Note that when the back surface processing step is composed of a plurality of processing steps including a CMP step (for example, a plurality of processing steps including a grinding step and a lapping step), the CMP step may be the final step of the back surface processing step. In that case, there is no processing step after the CMP step in the back surface processing step.

A processed strain layer exists on the back surface of the workpiece (which may be a semiconductor substrate) that has undergone the above-mentioned back surface processing step. Furthermore, when a strained layer exists on the front surface of the workpiece, a strained layer having a depth greater than the depth of the strained layer on the front surface exists on the back surface. This makes it possible to highly control the shape of the semiconductor substrate after manufacturing or in a semiconductor device. Furthermore, the workpiece that has undergone the back surface processing step may have a predetermined surface roughness Ra. The depth of the strained layer existing on the back surface after the back surface processing step, the difference in the depth of the strained layer between the back surface and the front surface, and the Ra of the back surface are the depth D of the strained layer on the back surface of the semiconductor substrate described above. _BF , the difference (D _BF -D _FF ), and the Ra of the back side can take the same values, so a redundant explanation will be omitted.

<Front surface processing process>
The method for manufacturing a semiconductor substrate disclosed herein typically includes a front surface processing step. In the front surface processing step, the front surface of the workpiece is processed. Here, the front surface of the workpiece is a surface that becomes the front surface of a semiconductor substrate to be manufactured. The front surface processing step is typically a step in which the front surface of the workpiece is made into a smooth surface, and more specifically, it is a step in which the front surface of the workpiece is finished into a high-quality surface such as a mirror surface.

The front surface processing step disclosed herein is not limited to a specific configuration, and a known surface processing technique is appropriately selected in consideration of the above-mentioned back surface processing step, and a processed strain layer is formed on the front surface. This is carried out so that there is no strained layer, or a strained layer having a depth smaller than the depth of the strained layer on the back side. The front surface processing process is not particularly limited, but one or more of a grinding process, a lapping process, a CMP process, etc. may be adopted. The details of the grinding process and lapping process that can be carried out in the front surface processing process are as explained in the back surface processing process, and the abrasive grain type and The grinding step and the lapping step in the front surface processing step may be carried out by making the conditions and matters such as hardness and particle size different from those in the back surface processing step.

(Abrasive grains for front surface processing)
The front surface processing step usually includes a step using abrasive grains _AFF . Examples of the abrasive grains _AFF include one or more of the types of abrasive grains for back surface processing exemplified above. Among these, silica particles and alumina particles are preferred.

In one preferred embodiment, the abrasive grains A _FF contain silica abrasive grains (silica particles). The silica abrasive grains can be appropriately selected and used from various known silica particles. Such known silica particles include colloidal silica, dry process silica, and the like. Among them, it is preferable to use colloidal silica. Silica abrasive grains containing colloidal silica can suitably achieve a high polishing rate and good surface accuracy.

The shape (outer shape) of the abrasive grains A _FF (for example, silica abrasive grains) may be spherical or non-spherical. For example, specific examples of non-spherical silica abrasive grains include a peanut shape (namely, the shape of a peanut shell), a cocoon shape, a confetti candy shape, a rugby ball shape, and the like. In the technology disclosed herein, the abrasive grains A _FF (for example, silica abrasive grains) may be in the form of primary particles, or may be in the form of secondary particles in which a plurality of primary particles are associated. Further, abrasive grains in the form of primary particles (for example, silica abrasive grains) and abrasive grains in the form of secondary particles (for example, silica abrasive grains) may be mixed. In one preferred embodiment, at least some of the abrasive grains A _FF (for example, silica abrasive grains) are contained in the polishing composition in the form of secondary particles.

The hardness of the abrasive grains _AFF used in the front surface processing step is not particularly limited. The Vickers hardness H _FF (Hv) of the abrasive grains A _FF is preferably about 200 Hv or more (for example, about 400 Hv or more, typically about 600 Hv or more). In another aspect, the Vickers hardness H _FF (Hv) of the abrasive grains A _FF is, for example, about 1000 Hv or more (eg, about 1200 Hv or more, typically about 1500 Hv or more). In one embodiment, the Vickers hardness H _FF (Hv) is, for example, approximately 2,500 Hv or less (for example, approximately 2,000 Hv or less, typically approximately 1,700 Hv or less) from the viewpoint of keeping the depth of the strained layer at a predetermined value or less. It is preferable. In another aspect, the Vickers hardness H _FF (Hv) is preferably about 1500 Hv or less (for example about 1000 Hv or less, typically about 800 Hv or less). By using abrasive grains with a lower hardness than the front surface of the workpiece, a higher quality surface can be obtained.

As the abrasive grains _AFF (for example, silica abrasive grains), those having an average primary particle diameter (hereinafter sometimes simply referred to as "D1") larger than 5 nm can be preferably employed. From the viewpoint of polishing efficiency, etc., D1 is preferably 15 nm or more, more preferably 20 nm or more, even more preferably 25 nm or more, and particularly preferably 30 nm or more. The upper limit of D1 is not particularly limited, but it is appropriate to set it to approximately 120 nm or less, preferably 100 nm or less, and more preferably 85 nm or less. For example, from the viewpoint of achieving both polishing efficiency and surface quality at a higher level, abrasive grains A _FF (typically silica abrasive grains) with D1 of 12 nm or more and 80 nm or less are preferable, and abrasive grains A _FF (typically silica abrasive grains) with D1 of 15 nm or more and 60 nm or less are preferable. Typically, silica abrasive grains) are preferred.

In addition, in the technology disclosed herein, the average primary particle diameter of abrasive grain A _FF is calculated from the specific surface area (BET value) measured by the BET method, and the average primary particle diameter (nm) = 6000/(true density ( It refers to the particle diameter calculated by the formula: g/cm ³ )×BET value (m ² /g). For example, in the case of silica abrasive grains, the average primary particle size can be calculated from average primary particle size (nm)=2727/BET value (m ² /g). The specific surface area can be measured using, for example, a surface area measuring device manufactured by Micromeritex, trade name "Flow Sorb II 2300".

The average secondary particle diameter (hereinafter sometimes simply referred to as "D2") of the abrasive grains A _FF (for example, silica abrasive grains) is not particularly limited, but from the viewpoint of polishing efficiency etc., it is preferably 20 nm or more, more preferably 20 nm or more. Preferably it is 50 nm or more, more preferably 70 nm or more. In addition, from the viewpoint of obtaining a higher quality surface, the average secondary particle diameter D2 of the abrasive grains A _FF (for example, silica abrasive grains) is suitably 500 nm or less, preferably 300 nm or less, more preferably 200 nm or less, More preferably, it is 130 nm or less, particularly preferably 110 nm or less (for example, 100 nm or less).

In addition, in the technology disclosed herein, the average secondary particle diameter of the abrasive grains A _FF is determined by, for example, the volume average particle diameter (volume It can be measured as the reference arithmetic mean diameter (Mv).

In one preferred embodiment, the front surface processing step includes a CMP step. By employing the CMP process, the semiconductor substrate disclosed herein can be easily obtained, and a high-quality surface can be easily obtained. The CMP process according to a preferred embodiment is performed by supplying a polishing slurry (also referred to as polishing liquid) made of a polishing composition described below to the surface of the workpiece. Specifically, it may be a step of supplying the polishing liquid to the surface of the workpiece and polishing it by a conventional method, similar to the CMP step using the composition for back surface polishing.

(Front surface polishing composition)
The composition for polishing the front surface disclosed herein is not limited to a specific composition, and is prepared so that no strained layer is present on the front surface or the depth is smaller than the depth of the strained layer on the back surface. A composition that can be used as a process-strained layer is employed. Such a polishing composition includes, for example, abrasive grains, a solvent such as water, and may further include a polishing aid _CFF such as an oxidizing agent.

The abrasive grains _AFF used in the CMP process for the front surface include one or more of the abrasive grains for back surface processing exemplified above. Among these, silica particles and alumina particles are preferred, silica particles are more preferred, and colloidal silica is even more preferred. The average primary particle size and average secondary particle size of the preferably used abrasive grains _AFF (for example, silica abrasive grains) are as described above, and a redundant explanation will not be repeated.

The content of abrasive grains A _FF in the front surface polishing composition is approximately 12% by weight or more, for example, in the case of silica abrasive grains. From the viewpoint of polishing efficiency, etc., the content is preferably 15% by weight or more. In some embodiments, the content may be, for example, 20% by weight or more. Further, from the viewpoint of achieving both high polishing rate and surface quality, the content of abrasive grains _AFF is approximately 50% by weight or less in the case of silica abrasive grains, for example. The above content is preferably 40% by weight or less, more preferably 35% by weight or less. In some embodiments, the content may be, for example, 42% by weight or less, typically 38% by weight or less (for example, 35% by weight or less). The technology disclosed herein is, for example, in an embodiment in which the content of silica abrasive grains in the front surface polishing composition is 12% by weight or more and 35% by weight or less (furthermore, 15% by weight or more and 30% by weight or less). It can be preferably implemented.

For example, in the case of alumina abrasive grains, the content of the abrasive grains _AFF in the front surface polishing composition is approximately 0.1% by weight or more. From the viewpoint of polishing efficiency, etc., the content is preferably 0.5% by weight or more. In some embodiments, the content may be, for example, 1% by weight or more. Further, from the viewpoint of achieving both high polishing rate and surface quality, the content of the abrasive grains _AFF is approximately 20% by weight or less in the case of alumina abrasive grains, for example. The content is preferably 15% by weight or less, more preferably 12% by weight or less. In some embodiments, the content may be, for example, 13% by weight or less, typically 10% by weight or less (for example, 8% by weight or less). In the technology disclosed herein, for example, the content of alumina abrasive grains in the front surface polishing composition is 0.1% by weight or more and 20% by weight or less (furthermore, 3% by weight or more and 8% by weight or less). It can be preferably implemented in various embodiments.

Preferably, the front surface polishing composition disclosed herein includes a polishing aid (eg, an oxidizing agent) _CFF . As the polishing aid _CFF , one or more of the polishing aids _CFF exemplified in the composition for back polishing can be used without particular limitation. From the viewpoint of achieving both high polishing rate and surface quality, hydrogen peroxide and vanadate acids are preferred, and it is particularly preferred to use hydrogen peroxide and vanadate acids (for example, sodium metavanadate) in combination.

In a particularly preferred embodiment, the ratio of the content of hydrogen peroxide and vanadate acids (e.g., sodium metavanadate) used together, that is, the ratio of the content C2 of hydrogen peroxide to the content C1 of vanadate acids (C2/C1), is: It is not particularly limited, but it is suitably 0.5 or more and 2 or less on a weight basis, preferably 0.6 or more and 1.9 or less, and more preferably 0.6 or more and 1.5 or less. . By using the above-mentioned compounds in combination at a specific content ratio, it is possible to achieve both polishing rate and surface quality at a higher level. In some embodiments, the ratio (C2/C1) may be, for example, 0.6 or more and 1.2 or less, and typically 0.6 or more and 0.9 or less.

The concentration (content) of the polishing aid _CFF in the front surface polishing composition is usually 0.1% by weight or more. From the viewpoint of achieving both polishing rate and surface quality highly and efficiently, the concentration in a preferred embodiment is 1% by weight or more, more preferably 1.5% by weight or more, still more preferably 2% by weight or more, Particularly preferably, it is 2.5% by weight or more (for example, 2.8% by weight or more). In addition, from the viewpoint of improving smoothness, the concentration of the polishing aid _CFF is usually 10% by weight or less, preferably 8% by weight or less, and 6.5% by weight or less. It is more preferable that the amount is at most 6% by weight, even more preferably at most 6% by weight, and particularly preferably at most 5.5% by weight. In some embodiments, the concentration may be, for example, 4.5% by weight or less, typically 4% by weight or less.

The front surface polishing composition disclosed herein contains a chelating agent, a thickener, a dispersing agent, a surface protective agent, a wetting agent, a pH adjuster, Known additives that can be used in polishing compositions (for example, compositions for polishing silicon carbide substrates), such as surfactants, organic acids, inorganic acids, rust inhibitors, preservatives, and fungicides, may be added as necessary. It may further contain. The content of the above-mentioned additive may be appropriately set depending on the purpose of addition, and does not characterize the present invention, so a detailed explanation will be omitted.

The pH of the front surface polishing composition is usually approximately 2 to 12. When the pH of the front surface polishing composition is within the above range, a practical polishing rate can be easily achieved. The pH of the front surface polishing composition is preferably 3 or more, more preferably 4 or more, and even more preferably 5.5 or more. The upper limit of pH is not particularly limited, but is preferably 12 or less, more preferably 10 or less, and even more preferably 9.5 or less. The above pH is preferably 3 to 11, more preferably 4 to 10, and even more preferably 5.5 to 9.5. The pH of the front surface polishing composition may be, for example, 9 or less, typically 7.5 or less.

Note that when the front surface processing step is composed of a plurality of processing steps including a CMP step, the CMP step may be the final step of the front surface processing step. In that case, there is no processing step after the CMP step in the front surface processing step. Furthermore, in the case where an etching process that does not use abrasive grains is performed in the front surface processing process, this etching process can be performed before or after the CMP process.

In one embodiment, the front surface processing step may include a step of performing preliminary polishing (preliminary polishing step) and a step of performing final polishing (finish polishing step). The preliminary polishing step here is a step of performing preliminary polishing on the workpiece. In one typical aspect, the pre-polishing step is a polishing step that is placed immediately before the final polishing step. The preliminary polishing process may be a one-stage polishing process, or may be a multi-stage polishing process of two or more stages. In addition, the final polishing step referred to herein is a step of performing final polishing on the workpiece that has been subjected to preliminary polishing, and is the last (i.e., the most) of the polishing steps performed using the polishing composition. This refers to the polishing process located downstream). In such a method including a preliminary polishing step and a final polishing step, the above-mentioned front surface polishing composition is typically used in the final polishing step. It may be used in both the preliminary polishing step and the final polishing step.

Furthermore, the front surface processing step disclosed herein may include any other steps in addition to the preliminary polishing step and the final polishing step. Such steps include a grinding step and a lapping step performed before the preliminary polishing step. Further, the front surface processing step disclosed herein may include an additional step (a cleaning step or a polishing step) before the preliminary polishing step or between the preliminary polishing step and the final polishing step.

A processed strain layer does not exist on the front surface of the workpiece (which may be a semiconductor substrate) that has undergone the above-mentioned front surface processing step. Alternatively, when a strained layer exists on the front surface of the workpiece, the depth of the strained layer on the front surface is smaller than the depth of the strained layer on the back surface. This makes it possible to highly control the shape of the semiconductor substrate after manufacturing or in a semiconductor device. Further, the workpiece that has undergone the front surface processing step may have a predetermined surface roughness Ra. The depth and Ra of the strained layer existing on the front surface after the front surface processing process take the same values as the depths _DFF and Ra of the strained layer on the front surface of the semiconductor substrate described above. Therefore, duplicate explanations will be omitted.

Note that the solvent used in the lapping composition and polishing composition (including the composition for back polishing and the composition for front polishing; the same applies hereinafter unless otherwise specified) may contain abrasive grains and optional ingredients. There are no particular limitations as long as the polishing aid can be dispersed. As the solvent, ion-exchanged water (deionized water), pure water, ultrapure water, distilled water, etc. can be preferably used. The lapping composition and polishing composition disclosed herein may further contain an organic solvent (lower alcohol, lower ketone, etc.) that can be uniformly mixed with water, if necessary. Usually, it is preferable that 90% by volume or more of the solvent contained in the above composition is water, and more preferably 95% by volume or more (typically 99 to 100% by volume) is water.

Furthermore, the lapping composition and polishing composition disclosed herein may be of a single-component type or a multi-component type such as a two-component type. For example, a solution A containing some of the constituent components (typically, components other than the solvent) of the polishing composition and a solution B containing the remaining components are mixed to polish the object to be polished. It may be configured to be used for. Furthermore, the lapping composition and polishing composition disclosed herein may be in a concentrated form (i.e., in the form of a concentrated lapping liquid or polishing liquid) before being supplied to the workpiece. good. The lapping composition or polishing composition in such a concentrated form is advantageous from the viewpoint of convenience and cost reduction during manufacturing, distribution, storage, etc. The concentration ratio can be, for example, about 2 to 5 times in terms of volume.
Note that the preparation of the lapping composition and polishing composition may include preparing the lapping liquid and polishing liquid by adding operations such as concentration adjustment (for example, dilution) and pH adjustment. Alternatively, the above-mentioned lapping composition may be used as it is as a lapping liquid, or the above-mentioned polishing composition may be used as it is as a polishing liquid. In the case of a multi-component polishing composition, preparing the polishing liquid includes mixing the agents, diluting one or more agents before the mixing, and diluting one or more agents after the mixing. diluting the mixture, and the like.

Further, in the processing steps disclosed herein, a single-sided grinding device or a single-sided polishing device may be used. In a single-sided grinding device, for example, a holder called a carrier is used to hold the workpiece, and a fixed abrasive grain (grinding wheel) fixed to a surface plate is pressed against one side of the workpiece to make the two relative to each other. One side of the workpiece is ground by moving (for example, rotationally moving). During grinding, a machining fluid consisting of an aqueous solution is normally supplied to the surface of the workpiece. In addition, in single-sided polishing equipment, the workpiece is attached to a ceramic plate with wax, the workpiece is held using a holder called a carrier, and abrasive grains (or polishing composition in the case of polishing) are supplied. At the same time, one side of the workpiece is polished by pressing a surface plate or a polishing pad against one side of the workpiece and relatively moving (for example, rotationally moving) the two.

Furthermore, a double-sided grinding device or a double-sided polishing device can also be used in the processing steps disclosed herein. Double-sided grinding equipment uses a holder called a carrier to hold the workpiece, and presses fixed abrasive grains (grinding wheels) fixed to a surface plate on the opposite side of the workpiece to move them in relative directions. By rotating, both sides of the workpiece are ground simultaneously. During grinding, a machining fluid consisting of an aqueous solution is normally supplied to the surface of the workpiece. In addition, double-sided polishing equipment uses a holder called a carrier to hold the workpiece, and polishes the opposite side of the workpiece while supplying abrasive grains (polishing composition in the case of polishing) from above. By pressing the pads and rotating them in relative directions, both sides of the workpiece are simultaneously polished.

The polishing pad used in the CMP process disclosed herein is not particularly limited. For example, any of non-woven fabric type, suede type, hard polyurethane foam type, those containing abrasive grains, those containing no abrasive grains, etc. may be used.

Workpieces processed by the methods disclosed herein are typically cleaned after polishing. This cleaning can be performed using a suitable cleaning solution. The cleaning liquid to be used is not particularly limited, and any known or commonly used cleaning liquid can be appropriately selected and used.

<Polishing composition set>
The technology disclosed herein may include, for example, providing a polishing composition set as described below. That is, according to the technology disclosed herein, a polishing composition set including composition Q1 and composition Q2 that are stored separately from each other is provided. The composition Q1 may be a back polishing composition (including a concentrate) used in the back processing step disclosed herein. The composition Q2 may be a front surface polishing composition (including a concentrate) used in the front surface processing step disclosed herein. When a multi-stage processing process including a back surface processing step and a front surface processing step is performed using a polishing composition set having such a configuration, a semiconductor substrate whose shape after manufacturing is highly controlled can be suitably manufactured. . Moreover, the obtained semiconductor substrate can have high surface quality.

<Composition set>
The technology disclosed herein may include, for example, providing the following composition set. That is, according to the technology disclosed herein, a composition set including composition Q3 and composition Q4 that are stored separately from each other is provided. The composition Q3 may be a wrapping composition (including a concentrate) used in the back surface processing step disclosed herein. The composition Q4 may be a front surface polishing composition (including a concentrate) used in the front surface processing step disclosed herein. When a multi-stage processing process including a back surface processing step and a front surface processing step is performed using a composition set having such a configuration, a semiconductor substrate whose shape after manufacturing is highly controlled can be manufactured with high processing efficiency. . Moreover, the obtained semiconductor substrate can have high surface quality.

<Set for semiconductor substrate manufacturing>
The technology disclosed herein may include, for example, providing a set for manufacturing a semiconductor substrate as described below. That is, according to the technology disclosed herein, a set for manufacturing a semiconductor substrate including grinding abrasive grains and composition Q5 that are stored separately from each other is provided. The above-mentioned grinding abrasive grains may be grinding abrasive grains used in the back surface processing step disclosed herein. The composition Q5 may be a front surface polishing composition (including a concentrate) used in the front surface processing step disclosed herein. When a multi-stage processing process including a back surface processing step and a front surface processing step is performed using a set of such configurations, a semiconductor substrate whose shape after manufacturing is highly controlled can be manufactured with high processing efficiency. Moreover, the obtained semiconductor substrate can have high surface quality.

Hereinafter, some examples related to the present invention will be described, but the present invention is not intended to be limited to what is shown in the examples. In the following description, "%" is based on weight unless otherwise specified.

<Preparation of polishing composition>
(Preparation example 1)
Polishing composition A was prepared by mixing colloidal silica, sodium metavanadate, hydrogen peroxide, and deionized water. The content of colloidal silica was 23%, the content of sodium metavanadate was 1.9%, and the content of hydrogen peroxide was 1.2%. The pH of the polishing composition was adjusted to 6.5 using potassium hydroxide (KOH). The colloidal silica used was spherical with an average secondary particle diameter of 97 nm.

(Preparation example 2)
Polishing composition B was prepared by mixing alumina abrasive grains (α-alumina, average secondary particle size: 0.5 μm), potassium permanganate (KMnO ₄ ) as a polishing aid, and deionized water. The content of alumina abrasive grains was 6%, and the content of KMnO ₄ was 1.2%. The pH of the polishing composition was adjusted to 9.0 using KOH.

<Example 1 to Example 10>
Processing was performed on the front and back surfaces of the workpiece according to the contents shown in Table 1. The processing conditions are as follows. In the CMP process, polishing compositions A and B were used as slurries A and B, respectively. GC is a slurry containing green silicon carbide particles as abrasive grains. A 3-inch SiC wafer (conductivity type: n-type, crystal type 4H 4° off) was used as the workpiece.

[CMP conditions]
Polishing device: Product name “SPM-11” manufactured by Fujikoshi Machine Industry Co., Ltd.
Polishing pad: “SURFIN 019-3” manufactured by Fujimi Incorporated
Polishing pressure: 300g/ ^cm2
Surface plate rotation speed: 60 rotations/minute Head rotation speed: 40 rotations/minute (forced drive)
Supply rate of polishing liquid: ≧20mL/min (direct flow)
Polishing liquid temperature: 25℃
Polishing time: until Ra becomes constant

[Wrapping conditions]
Polishing device: Single-sided polishing device manufactured by Nippon Engis, model “EJ-380IN”
Polishing surface plate: Copper Polishing pressure: 300g/ ^cm2
Surface plate rotation speed: 70 rotations/minute Head rotation speed: 40 rotations/minute (forced drive)
Abrasive grain concentration in polishing liquid: 10%
Supply rate of polishing liquid: 10mL/min (flowing)
Polishing liquid temperature: 25℃
Polishing time: until Ra becomes constant

[Grinding conditions]
Grinding device: Product name “MHG-2000” manufactured by Shuwa Kogyo Co., Ltd.
Grinding wheel: Diamond wheel (Binding material: Vidrified)
Grinding wheel rotation speed: 2000 rotations/minute Workpiece rotation speed: 200 rotation/minute Grinding time: Until Ra becomes constant

<Measurement of processing strain layer depth>
The depth of the strained layer on the front and back surfaces of the workpiece was measured by observation (observation magnification: 10 to 200 times) using a differential interference microscope (trade name "OPTI PHOTO 300" manufactured by Nikon Corporation) and by polishing. Specifically, the machining scratches are identified using a differential interference microscope, the identified machining scratches are removed by polishing, and the depth equivalent to the polishing allowance required to remove the machining scratches is determined as the depth of the machining strain layer [μm]. And so. The polishing conditions and the method for calculating the polishing removal amount are shown below.
[Policing conditions]
Polishing device: Single-sided polishing device manufactured by Nippon Engis, model “EJ-380IN”
Polishing pad: “SUBA800” manufactured by Nitta Haas
Polishing pressure: 300g/ ^cm2
Surface plate rotation speed: 80 rotations/minute Polishing time: Until processing scratches disappear Head rotation speed: 40 rotations/minute Polishing liquid supply rate: 20mL/minute (flowing)
Polishing liquid temperature: 25℃
Polishing liquid: colloidal silica + vanadate + hydrogen peroxide (pH 8)
[Polishing allowance]
Polishing removal amount [cm] = Difference in weight of SiC wafer before and after polishing [g]/SiC density [g/cm ³ ] (=3.21 g/cm ³ )/Area to be polished [cm ² ] (=19. ^62cm2 )
The measurement results are shown in Table 1.

<Surface roughness Ra>
The surface roughness Ra [nm] of the processed workpiece surface in each example was measured using an atomic force microscope (AFM; trade name "D3100 Nano Scope V", manufactured by Veeco) under the conditions of a measurement area of 10 μm x 10 μm. ] was measured. The results are shown in Table 1.

<Evaluation of board shape>
The degree of warpage (unevenness with respect to the front surface) and the degree [μm] of the semiconductor substrate manufactured by the processing method according to each example were measured using GBIR. For the measurement, a surface shape measuring machine "SURFCOM 1500DX" manufactured by Tokyo Seimitsu Co., Ltd. was used. A warp in which the front surface side is convex is described as "+X μm", and a warp in which the front surface side is concave is described as "-X μm". The results are shown in Table 1.

<Evaluation of substrate shape after film formation>
An epitaxial film was formed on the front surface of a semiconductor substrate manufactured by the processing method according to each example, and the shape of the semiconductor substrate after the epitaxial film was formed was measured using GBIR. An n ^- type SiC layer with a thickness of 30 μm was formed as an epitaxial film. Based on the obtained GBIR measurement results, evaluation was made according to the following criteria. The results are shown in Table 1.
[Evaluation criteria]
◎: GBIR 3μm or less ○: GBIR more than 3μm and 10μm or less △: GBIR more than 10μm and 14μm or less ×: GBIR more than 14μm

As shown in Table 1, in Examples 1 to 3 and Examples 5 to 8, in which there was no process-strained layer on the front surface and a process-strained layer on the back surface, the evaluation results of the semiconductor substrate shape after film formation were was within an excellent or practically acceptable range. In addition, even in a substrate with a process-strained layer on the front surface, in Example 4, where the depth of the process-strained layer on the back surface was larger than that on the front surface, the evaluation results of the semiconductor substrate shape after film formation was good. This effect can be obtained by appropriately setting the method and conditions of the back surface processing step. In particular, in Examples 5, 7, and 8, in which abrasive grains with relatively small particle diameters were used in the grinding process and the lapping process, the evaluation results of the semiconductor substrate shape after film formation were excellent. On the other hand, in Examples 9 and 10 in which no process-strained layer was present on the back surface, the evaluation results of the semiconductor substrate shape after film formation were poor.

Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The techniques described in the claims include various modifications and changes to the specific examples illustrated above.

Claims (19)

A method for manufacturing a semiconductor substrate, comprising a back surface processing step of processing the back surface of a wafer-shaped workpiece, and a front surface processing step of processing the front surface of the workpiece,
A processing strain layer is present on the back surface that has undergone the back surface processing step,
The front surface processing step includes a step of using a front surface polishing composition,
The front surface polishing composition includes a polishing aid _CFF ,
The polishing aid C _FF contains a composite metal oxide,
The depth of the process-strained layer present on the back surface is greater than the depth of the process-strain layer on the front surface of the semiconductor substrate, or no process-strain layer exists on the front surface,
The difference (D _BF −D _FF ) between the processed strain layer depth D _FF [μm] on the front surface and the processed strain layer depth D _BF [μm] on the back surface is 0.3 μm or more and 4.0 μm or less A method for manufacturing a semiconductor substrate. The manufacturing method according to claim 1, wherein the back surface processing step is a step of setting the arithmetic mean surface roughness Ra of the back surface to 10 nm or less. The manufacturing method according to claim 1 or 2, wherein the depth of the strained layer existing on the back surface is 0.1 μm or more. The manufacturing method according to any one of claims 1 to 3, wherein the back surface processing step includes a chemical mechanical polishing step. The manufacturing method according to any one of claims 1 to 3, wherein the back surface processing step includes a lapping step. The manufacturing method according to any one of claims 1 to 3, wherein the back surface processing step includes a grinding step. Both the front surface processing step and the back surface processing step include a step of using abrasive grains,
The manufacturing method according to any one of claims 1 to 6, wherein the abrasive grains used in the back surface processing step have a higher hardness than the abrasive grains used in the front surface processing step. Both the front surface processing step and the back surface processing step include a step of using abrasive grains,
The manufacturing method according to any one of claims 1 to 7, wherein the abrasive grains used in the back surface processing step have a larger particle size than the abrasive grains used in the front surface processing step. 9. The manufacturing method according to claim 1, wherein the semiconductor substrate is a semiconductor substrate made of silicon carbide. A polishing composition set used in the manufacturing method according to any one of claims 7 to 9,
Composition Q1 as a back polishing composition used in the back processing step;
Composition Q2 as a front surface polishing composition used in the front surface processing step,
The composition Q1 and the composition Q2 are stored separately from each other,
The front surface polishing composition includes a polishing aid _CFF ,
The polishing aid C _FF is a polishing composition set containing a composite metal oxide. The back polishing composition contains abrasive grains A _{and BF} ,
The front surface polishing composition contains abrasive grains _AFF ,
The polishing composition set according to claim 10, wherein the abrasive grains _ABF are alumina particles or green silicon carbide particles, and the abrasive grains _AFF are silica particles or alumina particles. The back polishing composition contains a polishing aid _CBF ,
The polishing composition set according to claim 11, wherein the polishing aid _CBF is permanganic acid or a salt thereof, and the polishing aid _CFF is hydrogen peroxide and vanadate. A composition set used in the manufacturing method according to any one of claims 7 to 9,
Composition Q3 as a wrapping composition used in the back surface processing step;
Composition Q4 as a front surface polishing composition used in the front surface processing step,
The composition Q3 and the composition Q4 are stored separately from each other,
The front surface polishing composition includes a polishing aid _CFF ,
The polishing aid C _FF is a composition set containing a composite metal oxide. The lapping composition contains abrasive grains A and _BF ,
The front surface polishing composition contains abrasive grains _AFF ,
The composition set according to claim 13, wherein the abrasive grains _ABF are diamond particles, and the abrasive grains _AFF are silica particles or alumina particles. The composition set according to claim 14, wherein the polishing aid _CFF contains at least one selected from the group consisting of permanganates and vanadates as the composite metal oxide. A semiconductor substrate manufacturing set used in the manufacturing method according to any one of claims 7 to 9,
Grinding abrasive grains used in the back surface processing step;
Composition Q5 as a front surface polishing composition used in the front surface processing step,
The grinding abrasive grains and the composition Q5 are stored separately from each other,
The front surface polishing composition includes a polishing aid _CFF ,
The polishing aid _CFF is a set for manufacturing a semiconductor substrate, and includes a composite metal oxide. 17. The set for manufacturing a semiconductor substrate according to claim 16, wherein the grinding abrasive grains are diamond particles, and the abrasive grains _AFF are silica particles or alumina particles. 18. The set for manufacturing a semiconductor substrate according to claim 17, wherein the polishing aid _CFF contains at least one selected from the group consisting of permanganates and vanadates as the composite metal oxide. A semiconductor substrate having a front surface and a back surface,
A processing strain layer is present on the back surface,
The depth of the process-strained layer present on the back surface is greater than the depth of the process-strain layer on the front surface, or no process-strain layer exists on the front surface,
The difference (D _BF −D _FF ) between the processed strain layer depth D _FF [μm] on the front surface and the processed strain layer depth D _BF [μm] on the back surface is 0.3 μm or more and 4.0 μm or less and
The semiconductor substrate, wherein the arithmetic mean roughness Ra of the back surface of the semiconductor substrate is less than 0.3 nm.