CN103532544B - The low-power consumption of a kind of band gating function is except two-divider - Google Patents
The low-power consumption of a kind of band gating function is except two-divider Download PDFInfo
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- CN103532544B CN103532544B CN201310439516.1A CN201310439516A CN103532544B CN 103532544 B CN103532544 B CN 103532544B CN 201310439516 A CN201310439516 A CN 201310439516A CN 103532544 B CN103532544 B CN 103532544B
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Abstract
The present invention provides the low-power consumption of a kind of band gating function except two-divider, wherein, comprises orthogonal local oscillation signal output terminal, gates clock signals control end and two to clock signal input terminal; Two clocksignals that described clock signal input terminal is inputted by described frequency divider carry out two divided-frequency after carrying out gating and by described orthogonal local oscillation signal output terminal output orthogonal local oscillation signal. By adopt two D-latchs and with principal and subordinate's relation connect, make use of the selection controlling functions of D-latch, meet the requirement of gating so that reach the demand exporting relatively large bandwidth frequency local oscillation signal except two-divider. Be equivalent to be embedded in alternative multi-way switch except in two-divider, therefore the electric current consumed is the electric current except two divided-frequency itself, has lacked the current sinking of multi-way switch own, has reduced power consumption simultaneously.
Description
Technical field
The present invention relates to communication control field, the low-power consumption in particular to a kind of band gating function removes two-divider.
Background technology
It is known that, local oscillation signal is receive and launch the key that signal is frequency spectrum shift in frequency microwave communication, numerary signal is when launching, need to be converted to numerary signal to be mixed to through local oscillation signal again and just can be launched away after radio frequency, with reason when receiving, expecting that the radio frequency received after amplifying, then could be met at back-end processing being converted to numerary signal after local oscillation signal mixing is amplified, general receiving apparatus is that Low Medium Frequency and zero intermediate frequency scheme are better substantially.
Along with the high speed development of the communication technology, channel bandwidth being had higher requirement, new communication system constantly occurs, such as bluetooth, WLAN (wireless local area network), navigation, mobile TV, FM etc. And the transmitter-receiver designed except can in new system except normal operation, also must compatible old system, namely need to support various modes. Local oscillation signal produces to meet relatively large bandwidth. Therefore occurred adopting two frequency multiplication structures to produce local oscillation signal, but the spectrum purity of local oscillation signal is required very high by radio communication system, therefore it be difficult to a design high performance VCO(voltage-controlled oscillator), export again so wide range of frequency simultaneously.
Therefore, broadband local oscillator common in prior art produces circuit as shown in Figure 1, VCO is made up of company the VCO of high and low wave band, carry out the tuning range of covering wide, the difference signal that high and low wave band VCO produces is after the multi-way switch (MUX) of alternative, then produces orthogonal local oscillation signal through two-divider. Owing to VCO is operated in several more than GHz, in order to guaranteed performance, MUX and two-divider all adopt current-mode logic (CML). Fig. 2 show the multi-way switch based on current-mode logic of prior art, this kind of multi-way switch is in order to be operated in several more than GHz, and have corresponding amplification ability, power consumption is at least more than 1mA, in addition multi-way switch due to work frequency higher, therefore the size of pipe and laying out pattern are all worthy of careful study, this block circuit will take no small chip area. Fig. 3 show the two-divider based on current-mode logic of prior art, is used for producing orthogonal local oscillation signal, and its power consumption is also at least at more than 1.5mA. Mobile equipment is more and more focused on reducing power consumption, and in the system of existing broadband, in order to support multi mode multi band, local oscillator generation circuit must increase the chip area of a multi-way switch and the current draw of at least 1mA, and this kind of scheme and the target that we pursue more low-power consumption run in the opposite direction.
Summary of the invention
The technical problem to be solved in the present invention be to provide a kind of support multi mode multi band, wide frequency ranges, compatible high and low power consumption, can be applicable to mobile equipment the low-power consumption of band gating function except two-divider.
In order to solve above technical problem, the present invention provides the low-power consumption of a kind of band gating function except two-divider, wherein, comprises orthogonal local oscillation signal output terminal, gates clock signals control end and two to clock signal input terminal; Two clocksignals that described clock signal input terminal is inputted by described frequency divider carry out two divided-frequency after carrying out gating and by described orthogonal local oscillation signal output terminal output orthogonal local oscillation signal.
Preferably, described frequency divider comprises two D-latchs, and one of them main D-latch and one are from D-latch; Described main D-latch is electrically connected the clock signal input terminal as described frequency divider and receives clocksignal, described main D-latch and the described output terminal output orthogonal local oscillation signal from D-latch with the described signal input terminus from D-latch.
Preferably, in described two D-latchs, each D-latch comprises one couple of difference data input terminus D and DN, gates clock signals control end S, to difference output end Q and QN and two to differential clock signal input terminus CKA_P, CKA_N, CKB_P and CKB_N.
Preferably, the gates clock signals control end of described main D-latch is electrically connected the gates clock signals control end as described frequency divider with the described gates clock signals control end from D-latch; The two of described main D-latch to differential clock signal input terminus and described from the two of D-latch differential clock signal input terminus reversal connection formed described frequency divider two to clock signal input terminal; Described main D-latch difference output rectify connect described from D-latch difference data input terminus, described from D-latch difference data input terminus main described in D-latch difference output end reversal connection; Described frequency divider comprises four orthogonal local oscillation signals output terminal IP, IN, QP and QN, and described main D-latch and the described difference output end from D-latch form four orthogonal local oscillation signals output terminal IP, IN, QP and QN of described frequency divider.
Preferably, in described two D-latchs each D-latch comprise pull-up resistor, the input of the data that are made up of field effect transistor M1 and field effect transistor M2 to pipe, the positive regeeration that is made up of field effect transistor M3 and field effect transistor M4 to pipe, and the clock being made up of field effect transistor M5, field effect transistor M6, field effect transistor M7 and field effect transistor M8 inputs pipe, the gating steering logic being made up of phase inverter and tail tube of current M9.
Preferably, the drain electrode of described field effect transistor M1 and the drain electrode of described field effect transistor M2 are respectively by pull-up resistor electric connection of power supply AVDD, the grid of described field effect transistor M1 is as the difference data input terminus D of described D-latch, the grid of described field effect transistor M2 is as the difference data input terminus DN of described D-latch, and the source electrode of described field effect transistor M1 is electrically connected described field effect transistor M5 and the drain electrode of described field effect transistor M6 with after the source shorted of described field effect transistor M1; The grid of described field effect transistor M3 is electrically connected the drain electrode of described field effect transistor M4, the grid of the electric described field effect transistor M4 that connects of the drain electrode of described field effect transistor M3, the drain electrode of described field effect transistor M3 be electrically connected described field effect transistor M1 drain electrode and as the difference output end Q of described D-latch, the drain electrode of described field effect transistor M4 be electrically connected described field effect transistor M2 drain electrode and as the difference output end QN of described D-latch, the source electrode of described field effect transistor M3 is electrically connected described field effect transistor M7 and the drain electrode of described field effect transistor M8 with after the source shorted of described field effect transistor M3; Described differential clock signal input terminus CKA_P is electrically connected the grid of described field effect transistor M5 through electric capacity C0 after straight coupling, described differential clock signal input terminus CKB_N is electrically connected the grid of described field effect transistor M6 through electric capacity C3 after straight coupling, described differential clock signal input terminus CKA_N is electrically connected the grid of described field effect transistor M7 through electric capacity C1 after straight coupling, and described differential clock signal input terminus CKB_P is electrically connected the grid of described field effect transistor M8 through electric capacity C2 after straight coupling; Tail tube of current M9 source ground, grid meets current offset voltage Bias; Clock gate control end S output difference dividing control signal SP and SN after phase inverter, described SP difference control signal inputs to the grid of described field effect transistor M5 and the grid of described field effect transistor M7 respectively after biasing resistor R4, biasing resistor R5, and described difference control signal SN inputs to the grid of described field effect transistor M6 and the grid of described field effect transistor M8 respectively after biasing resistor R6 and R7.
Preferably, described pull-up resistor is passive resistance, and described pull-up resistor comprises resistance R0 and resistance R1.
Preferably, described pull-up resistor is active resistance.
Preferably, described pull-up resistor comprises the field effect transistor M19, the field effect transistor M20 that are operated in linear resistance district, the source electrode of described field effect transistor M19 is connected power supply AVDD with the source electrode of described field effect transistor M20, the grid of described field effect transistor M19 and the grid ground connection of described field effect transistor M20, the drain electrode of described field effect transistor M19 is electrically connected described field effect transistor M1 and drains, and the drain electrode of described field effect transistor M20 is electrically connected described field effect transistor M2 and drains.
Preferably, described pull-up resistor also comprises field effect transistor M23, field effect transistor M24, described field effect transistor M23 source electrode and drain electrode are connected across between described field effect transistor M19, described field effect transistor M20, described field effect transistor M24 source electrode and drain electrode are connected across between described field effect transistor M19, described field effect transistor M20, the grid of described field effect transistor M23 is electrically connected the grid of described field effect transistor M7, and the grid of described field effect transistor M24 is electrically connected the grid of described field effect transistor M8.
Two clocksignals that clock signal input terminal is inputted by frequency divider carry out two divided-frequency output orthogonal local oscillation signal after carrying out gating so that reach the demand exporting relatively large bandwidth frequency local oscillation signal except two-divider. Be equivalent to be embedded in alternative multi-way switch except in two-divider, therefore the electric current consumed is the electric current except two divided-frequency itself, has lacked the current sinking of multi-way switch own, has greatly reduced power consumption simultaneously.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:
Fig. 1 is the functional block diagram producing local oscillation signal in prior art master;
Fig. 2 is a kind of schematic circuit producing local oscillation signal in prior art master;
Fig. 3 is a kind of schematic circuit producing local oscillation signal in prior art master;
Fig. 4 is the functional block diagram of low-power consumption except the embodiment 1 of two-divider of the band gating function of the present invention;
Fig. 5 is the circuit principle schematic of low-power consumption except the embodiment 1 of two-divider of the band gating function of the present invention;
Fig. 6 is the schematic circuit diagram of low-power consumption except the embodiment 1 of two-divider of the band gating function of the present invention;
Fig. 7 is the schematic circuit diagram of low-power consumption except the embodiment 2 of two-divider of the band gating function of the present invention;
Fig. 8 is the schematic circuit diagram of low-power consumption except the embodiment 3 of two-divider of the band gating function of the present invention.
Embodiment
For enabling above-mentioned purpose, the feature and advantage of the present invention more become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail, makes the above-mentioned of the present invention and other object, Characteristics and advantages will be more clear. Reference numeral identical in whole accompanying drawing indicates identical part. Deliberately do not draw accompanying drawing in proportion, focus on illustrating the purport of the present invention.
Embodiment 1:
As shown in Figure 4, the present invention provides the low-power consumption of a kind of band gating function except two-divider, wherein, comprises orthogonal local oscillation signal output terminal, gates clock signals control end and two to clock signal input terminal; . Two pairs of clock signal input terminals receive high wave band clocksignal and low band clocksignal respectively, two clocksignals that described clock signal input terminal is inputted by described frequency divider carry out two divided-frequency after carrying out gating and by described orthogonal local oscillation signal output terminal output orthogonal local oscillation signal.
As shown in Figure 5, in the present embodiment, described frequency divider comprises two identical D-latchs, one of them main D-latch and one are from D-latch, and in described two D-latchs, each D-latch comprises one couple of difference data input terminus D and DN, gates clock signals control end S, to difference output end Q and QN and two to differential clock signal input terminus CKA_P, CKA_N, CKB_P and CKB_N. The gates clock signals control end of described main D-latch is electrically connected as the described gates clock signals control end S except two-divider with the described gates clock signals end from D-latch; The two of main D-latch to differential clock signal input terminus with two from D-latch to described two clock signal input terminals except two-divider of differential clock signal input terminus positive-negative connected composition, namely together with the CKA_P of main D-latch connects with the CKA_N from D-latch, together with the CKA_N of main D-latch connects with the CKA_P from D-latch, together with the CKB_P of main D-latch connects with the CKB_N from D-latch, together with the CKB_N of main D-latch connects with the CKB_P from D-latch. Described main D-latch difference output is rectified and is connect described from D-latch difference data input terminus, and namely the Q of main D-latch meets the D from D-latch, and the QN of main D-latch meets the DN from D-latch. Described from D-latch difference data input terminus main described in D-latch difference output end reversal connection, namely meet the DN of main D-latch from the Q of D-latch, meet the D of main D-latch from the QN of D-latch. Described frequency divider comprises four orthogonal local oscillation signals output terminal IP, IN, QP and QN, and described main D-latch and the described difference output end from D-latch form four orthogonal local oscillation signals output terminal IP, IN, QP and QN of described frequency divider.
As shown in Figure 6, main D-latch is consistent with from D-latch circuit structure in the present invention, only sets forth its circuit structure with a D-latch. Described D-latch comprises pull-up resistor; The data being made up of field effect transistor M1, field effect transistor M2 input pipe; The positive regeeration being made up of field effect transistor M3, field effect transistor M4 is to pipe; The clock being made up of field effect transistor M5, field effect transistor M6, field effect transistor M7, field effect transistor M8 inputs pipe; Tail tube of current M9; And the gating steering logic being made up of phase inverter.
In the present embodiment, described pull-up resistor is resistance R0, resistance R1, the drain electrode of described field effect transistor M1 and the drain electrode of described field effect transistor M2 are respectively by resistance R0, resistance R1 electric connection of power supply AVDD, the grid of described field effect transistor M1 is as the difference data input terminus D of described D-latch, the grid of described field effect transistor M2 is as the difference data input terminus DN of described D-latch, and the source electrode of described field effect transistor M1 is electrically connected described field effect transistor M5 and the drain electrode of described field effect transistor M6 with after the source shorted of described field effect transistor M1; The grid of described field effect transistor M3 is electrically connected the drain electrode of described field effect transistor M4, the grid of the electric described field effect transistor M4 that connects of the drain electrode of described field effect transistor M3, the drain electrode of described field effect transistor M3 be electrically connected described field effect transistor M1 drain electrode and as the difference output end Q of described D-latch, the drain electrode of described field effect transistor M4 be electrically connected described field effect transistor M2 drain electrode and as the difference output end QN of described D-latch, the source electrode of described field effect transistor M3 is electrically connected described field effect transistor M7 and the drain electrode of described field effect transistor M8 with after the source shorted of described field effect transistor M3; Described differential clock signal input terminus CKA_P is electrically connected the grid of described field effect transistor M5 through electric capacity C0 after straight coupling, described differential clock signal input terminus CKB_N is electrically connected the grid of described field effect transistor M6 through electric capacity C3 after straight coupling, described differential clock signal input terminus CKA_N is electrically connected the grid of described field effect transistor M7 through electric capacity C1 after straight coupling, and described differential clock signal input terminus CKB_P is electrically connected the grid of described field effect transistor M8 through electric capacity C2 after straight coupling; Tail tube of current M9 source ground, grid meets current offset voltage Bias; Clock gate control end S output difference dividing control signal SP after phase inverter, SN, described SP difference control signal inputs to the grid of described field effect transistor M5 and the grid of described field effect transistor M7 respectively after biasing resistor R4, biasing resistor R5, described difference control signal SN, through biasing resistor R6, inputs to the grid of described field effect transistor M6 and the grid of described field effect transistor M8 respectively after R7.
The low-power consumption of the band gating function of the present invention removes two-divider principle of work:
The clocksignal of two pairs of Differential Input, through the control of clock gate control end S, select the clock input expected, when S is lower level, SP is lower level, when SN is high level, 1 corresponding end and 2 end DC levels are lower level, the DC level of 3 ends and 4 ends is high level, namely the grid of described field effect transistor M5 and the grid of described field effect transistor M7 are lower level, the grid of described field effect transistor M6 and the grid of described field effect transistor M8 are high level, and now the clock of frequency divider gating is CKB_P, CKB_N. When S is high level, SP is high level, when SN is lower level, 1 corresponding end and 2 end DC levels are high level, the DC level of 3 ends and 4 ends is lower level, and namely the grid of described field effect transistor M5 and the grid of described field effect transistor M7 are high level, and the grid of described field effect transistor M6 and the grid of described field effect transistor M8 are lower level, now the clock of frequency divider gating is CKA_P, CKA_N.
With gating CKA_P, CKA_N for example, namely 2 D-latchs connected by principal and subordinate's relation are by 2 complementary clock signal C KA_P, and CKA_N triggers. When clocksignal CKA_P end is lower level and CKA_N end is high level, main D-latch is in latch stage, and it latches and exports phase the last week in the data sampled obtain from the output terminal of D-latch; And now it is in sample phase from D-latch, the output of main D-latch is sampled and exports; When CKA_P end is high level and CKA_N end is lower level, main D-latch exchanges operating mode with from D-latch, and main D-latch is switched to sampling pattern by latch mode, and is switched to latch mode from D-latch by sampling pattern. Like this, the half that frequency is input frequency is exported, it is achieved that divide-by-two function. If main D-latch and the output from D-latch all as output signal, obtain four phase orthogonal signals.
Owing to being equivalent to be embedded in two-divider by alternative multi-way switch, therefore the electric current consumed is the electric current of two divided-frequency itself, and multi-way switch no longer current sinking itself, greatly reduces power consumption. In addition, embedding in multi-way switch, a lot of part is public with two-divider, it is only necessary to use several switching tubes, so chip area also reduces.
Embodiment 2:
As shown in Figure 7, the difference of the present embodiment and above-described embodiment 1 is, described pull-up resistor comprises the field effect transistor M19, the field effect transistor M20 that are operated in linear resistance district, the source electrode of described field effect transistor M19 is connected power supply AVDD with the source electrode of described field effect transistor M20, the grid of described field effect transistor M19 and the grid ground connection of described field effect transistor M20, the drain electrode of described field effect transistor M19 is electrically connected described field effect transistor M1 and drains, and the drain electrode of described field effect transistor M20 is electrically connected described field effect transistor M2 and drains.
Owing to the maximum operation frequency of current-mode logic two-divider determines primarily of except the pull-up resistor of two-divider and the RC time delay of load electric capacity composition. Load electric capacity by increasing output buffer (Buffer), can reduce positive regeeration and the size of pipe solved, but increase output buffer and will increase power consumption, runs counter to the original intention reducing power consumption by improving operating frequency. Here mainly through using active resistance as pull-up resistor, reduce the resistance value of pull-up resistor thus reduce power consumption.
Embodiment 3:
As shown in Figure 8, the difference of the present embodiment and above-described embodiment 2 is, described pull-up resistor also comprises field effect transistor M23, field effect transistor M24, described field effect transistor M23 source electrode and drain electrode are connected across between described field effect transistor M19, described field effect transistor M20, described field effect transistor M24 source electrode and drain electrode are connected across between described field effect transistor M19, described field effect transistor M20, the grid of described field effect transistor M23 is electrically connected the grid of described field effect transistor M7, and the grid of described field effect transistor M24 is electrically connected the grid of described field effect transistor M8.
The present embodiment is on the basis making active resistance replacement pull-up resistor with field effect transistor, and the field effect transistor increasing clock control is connected across the two ends of pull-up resistor. Its principle of work is: when the input clock except two-divider gating is CKA_P, CKA_N, namely 1 end and 2 ends are high level. When CKA_P end is high level and CKA_N end is lower level, main D-latch is operated in sampling pattern, when being operated in latch mode from D-latch, the field effect transistor M23 conducting of 2 end controls, field effect transistor M23 is in parallel by the active resistance short circuit of field effect transistor M19, field effect transistor M20 equivalence, and total pull-up resistor is reduced by half. When CKA_P end is lower level and CKA_N end is high level, main D-latch is switched to latch mode, when being switched to sampling pattern from D-latch, the field effect transistor M25 conducting of 1 end control, field effect transistor M25 is in parallel by the active resistance short circuit of field effect transistor M21, field effect transistor M22 equivalence, and total pull-up resistor is reduced by half. When the clock of gating is CKB_P, CKB_N, principle of work is similar with it, no longer describes in detail herein. Total pull-up resistor reduces by half, and the most high frequency making that two divided-frequency works improves, and reduces the power consumption of two-divider accordingly.
By adopt two D-latchs and with principal and subordinate's relation connect, make use of the selection controlling functions of D-latch, meet the requirement of gating so that reach the demand exporting relatively large bandwidth frequency local oscillation signal except two-divider. Be equivalent to be embedded in alternative multi-way switch except in two-divider, therefore the electric current consumed is the electric current except two divided-frequency itself, has lacked the current sinking of multi-way switch own, has greatly reduced power consumption simultaneously.
With the use of active resistance as pull-up resistor, reduce the resistance value of pull-up resistor thus reduce power consumption. Take into account and improved the requirement that operating frequency can reduce again function. The compatibility meeting various frequency band that can be bigger.
Make active resistance with field effect transistor to replace the basis of pull-up resistor increases the field effect transistor of clock control so that pull-up resistor reduces by half in working process, greatly reduces power consumption
Set forth a lot of detail in the above description so that fully understanding the present invention. But above description is only the better embodiment of the present invention, the present invention can implement to be much different from alternate manner described here, and therefore the present invention is not by the disclosed concrete restriction implemented above. Any those skilled in the art are not departing from technical solution of the present invention scope situation simultaneously, all can utilize the Method and Technology content of above-mentioned announcement that technical solution of the present invention is made many possible variations and modification, or be revised as the equivalent embodiment of equivalent variations. Every content not departing from technical solution of the present invention, the technical spirit of foundation the present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (7)
1. the low-power consumption of a band gating function is except two-divider, it is characterised in that, comprise orthogonal local oscillation signal output terminal, gates clock signals control end and two to clock signal input terminal; Two clocksignals that described clock signal input terminal is inputted by described frequency divider carry out two divided-frequency after carrying out gating and by described orthogonal local oscillation signal output terminal output orthogonal local oscillation signal; Described frequency divider comprises two D-latchs, and one of them main D-latch and one are from D-latch; Described main D-latch is electrically connected the clock signal input terminal as described frequency divider and receives clocksignal, described main D-latch and the described output terminal output orthogonal local oscillation signal from D-latch with the described signal input terminus from D-latch; In described two D-latchs, each D-latch comprises one couple of difference data input terminus D and DN, gates clock signals control end S, to difference output end Q and QN and two to differential clock signal input terminus CKA_P, CKA_N, CKB_P and CKB_N; The gates clock signals control end of described main D-latch is electrically connected the gates clock signals control end as described frequency divider with the described gates clock signals control end from D-latch; The two of described main D-latch to differential clock signal input terminus and described from the two of D-latch differential clock signal input terminus reversal connection formed described frequency divider two to clock signal input terminal; Described main D-latch difference output rectify connect described from D-latch difference data input terminus, described from D-latch difference data input terminus main described in D-latch difference output end reversal connection; Described frequency divider comprises four orthogonal local oscillation signals output terminal IP, IN, QP and QN, and described main D-latch and the described difference output end from D-latch form four orthogonal local oscillation signals output terminal IP, IN, QP and QN of described frequency divider.
2. the low-power consumption of band gating function according to claim 1 is except two-divider, it is characterized in that, in described two D-latchs each D-latch comprise pull-up resistor, the input of the data that are made up of field effect transistor M1 and field effect transistor M2 to pipe, the positive regeeration that is made up of field effect transistor M3 and field effect transistor M4 to pipe, and the clock being made up of field effect transistor M5, field effect transistor M6, field effect transistor M7 and field effect transistor M8 inputs pipe, the gating steering logic being made up of phase inverter and tail tube of current M9.
3. the low-power consumption of band gating function according to claim 2 is except two-divider, it is characterized in that, the drain electrode of described field effect transistor M1 and the drain electrode of described field effect transistor M2 are respectively by pull-up resistor electric connection of power supply AVDD, the grid of described field effect transistor M1 is as the difference data input terminus D of described D-latch, the grid of described field effect transistor M2 is as the difference data input terminus DN of described D-latch, and the source electrode of described field effect transistor M1 is electrically connected described field effect transistor M5 and the drain electrode of described field effect transistor M6 with after the source shorted of described field effect transistor M1; The grid of described field effect transistor M3 is electrically connected the drain electrode of described field effect transistor M4, the grid of the electric described field effect transistor M4 that connects of the drain electrode of described field effect transistor M3, the drain electrode of described field effect transistor M3 be electrically connected described field effect transistor M1 drain electrode and as the difference output end Q of described D-latch, the drain electrode of described field effect transistor M4 be electrically connected described field effect transistor M2 drain electrode and as the difference output end QN of described D-latch, the source electrode of described field effect transistor M3 is electrically connected described field effect transistor M7 and the drain electrode of described field effect transistor M8 with after the source shorted of described field effect transistor M3; Described differential clock signal input terminus CKA_P is electrically connected the grid of described field effect transistor M5 through electric capacity C0 after straight coupling, described differential clock signal input terminus CKB_N is electrically connected the grid of described field effect transistor M6 through electric capacity C3 after straight coupling, described differential clock signal input terminus CKA_N is electrically connected the grid of described field effect transistor M7 through electric capacity C1 after straight coupling, and described differential clock signal input terminus CKB_P is electrically connected the grid of described field effect transistor M8 through electric capacity C2 after straight coupling; Tail tube of current M9 source ground, grid meets current offset voltage Bias; Clock gate control end S output difference dividing control signal SP and SN after phase inverter, described SP difference control signal inputs to the grid of described field effect transistor M5 and the grid of described field effect transistor M7 respectively after biasing resistor R4, biasing resistor R5, and described difference control signal SN inputs to the grid of described field effect transistor M6 and the grid of described field effect transistor M8 respectively after biasing resistor R6 and R7.
4. the low-power consumption of band gating function according to claim 3 is except two-divider, it is characterised in that, described pull-up resistor is passive resistance, and described pull-up resistor comprises resistance R0 and resistance R1.
5. the low-power consumption of band gating function according to claim 3 is except two-divider, it is characterised in that, described pull-up resistor is active resistance.
6. the low-power consumption of band gating function according to claim 5 is except two-divider, it is characterized in that, described pull-up resistor comprises the field effect transistor M19 and field effect transistor M20 that are operated in linear resistance district, the source electrode of described field effect transistor M19 is connected power supply AVDD with the source electrode of described field effect transistor M20, the grid of described field effect transistor M19 and the grid ground connection of described field effect transistor M20, the drain electrode of described field effect transistor M19 is electrically connected described field effect transistor M1 and drains, and the drain electrode of described field effect transistor M20 is electrically connected described field effect transistor M2 and drains.
7. the low-power consumption of band gating function according to claim 6 is except two-divider, it is characterized in that, described pull-up resistor also comprises field effect transistor M23 and field effect transistor M24, described field effect transistor M23 source electrode and drain electrode are connected across between described field effect transistor M19 and field effect transistor M20, described field effect transistor M24 source electrode and drain electrode are connected across between described field effect transistor M19 and field effect transistor M20, the grid of described field effect transistor M23 is electrically connected the grid of described field effect transistor M7, and the grid of described field effect transistor M24 is electrically connected the grid of described field effect transistor M8.
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