CN105207626B - A kind of collapsible linear transconductance upconverter - Google Patents
A kind of collapsible linear transconductance upconverter Download PDFInfo
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- CN105207626B CN105207626B CN201510706256.9A CN201510706256A CN105207626B CN 105207626 B CN105207626 B CN 105207626B CN 201510706256 A CN201510706256 A CN 201510706256A CN 105207626 B CN105207626 B CN 105207626B
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Abstract
The present invention relates to a kind of collapsible linear transconductance upconverter, includes high linearity intermediate frequency transconductance circuit, double flat weighing apparatus local oscillator switch and load circuit；The present invention is foldable structure, and electric current caused by transconductance stage is copied into local oscillator switch through current mirror, is reduced to three from four so as to which local oscillator to be switched to the transistor size of place branch road stacking, has relaxed voltage margin.Transconductance stage realizes the voltage with high linearity-electric current translation function by the negative-feedback circuit based on amplifier.Simultaneously in order to ensure the voltage margin of transconductance stage, the bias voltage at mutual conductance resistance both ends has been moved up a gate source voltage by the linear transconductance circuit compared to input voltage.The uppermixing circuit can be operated in compared with low supply voltage, and has the characteristics of high linearity.
Description
Technical field
The present invention relates to a kind of mutual conductance upconverter, accurately say, be a kind of collapsible linear transconductance upconverter.
Background technology
Radio frequency transmitter circuitry must generally possess the higher linearity to ensure that output regeneration frequency spectrum is controlled in zone of reasonableness
Within.The linearity of upconverter is to the linearity important of whole transmitting chain, therefore to the upconverter linearity
Optimize particularly significant.Most basic upconverter is achieved in that on the basis of gilbert mixer structure, by that will bear
Carry resistance and replace with the realization of LC filter networks.The structure can realize up-conversion and filter function simultaneously.Yet with gill
The transconductance stage of Bert structure is only made up of difference MOS to pipe, and its linearity can not be effectively ensured.
In view of the input signal of upconverter is located at low frequency or Mid Frequency, therefore strengthen transconductance stage using negative-feedback
The linearity.Common implementation is that the super source based on amplifier follows structure.The structure by making respectively in differential input end
With voltage follower, connected between the output end of differential voltage follower by resistance.In the presence of voltage follower, input
Voltage signal is copied to resistance both ends so as to produce the electric current of high linearity.This method can realize the input mutual conductance of High Linear,
It has been obviously improved the linearity of upconverter.But the structure is laminated 4 transistors between power supply to ground so that it is difficult to should
Use the application scenario of low supply voltage.In order to meet while high linearity is realized to low supply voltage and low-power consumption
It is required that the present invention proposes a kind of collapsible linear transconductance upconverter structure.Electric current caused by transconductance stage is passed through electricity by the structure
Stream mirror is injected into local oscillator switching stage, improves voltage margin problem.It is of the invention sharp simultaneously in order to ensure the voltage margin of transconductance stage
The bias voltage at mutual conductance resistance both ends a gate source voltage has been moved up into compared to input voltage with negative-feedback circuit.The uppermixing
Circuit can be operated in compared with low supply voltage, and has the characteristics of high linearity.
The content of the invention
Technical problem：It is an object of the invention to provide on a kind of high linearity suitable for low supply voltage application scenario
Frequency converter.
Technical scheme：The object of the invention is realized by the following method：
The upconverter is switched by transconductance stage, local oscillator and load is formed.Transconductance circuit is super using feedback loop construction
Level source follows structure, by input voltage complete copy to mutual conductance resistance both ends, so as to ensure that the higher linearity.While in order to
The voltage margin of transconductance stage and low-side current mirror is improved, after resistance both end voltage is shifted into a gate source voltage in feedback branch
It is fed to error amplifier.Electric current caused by transconductance stage is injected into double flat weighing apparatus local oscillator switch after the duplication and amplification of current mirror,
Frequency conversion effect through local oscillator switch produces up-conversion signal and harmonic mixing product, positioned at the LC bandpass filtering networks of load end
Harmonic mixing product is filtered out, exports pure up-conversion signal.
The concrete structure of circuit is as follows：Its structure can mainly be divided into linear transconductance level and double flat weighing apparatus local oscillator switch and load
Three modules of level, linear transconductance level include：Input signal just the first PMOS PM1 of termination grid, PM1 source electrode connect the 14th
PMOS PM14 drain electrode, the grid that PM14 source electrode meets supply voltage VDD, PM14 meet bias voltage Vbp1；Second PMOS
PM2 source electrode connects PM0 drain electrode, and PM2 grid connects the 4th PMOS PM4 grid；PM1 drain electrode connects the 14th NMOS tube
NM14 drain electrode, NM14 grid and drain electrode short circuit, NM14 source ground GND；PM2 drain electrode connects the first NMOS tube NM1's
Drain electrode, NM1 grid connect NM0 grid, NM1 source ground；PM4 grid and drain electrode are connected to the second NMOS tube NM2 together
Drain electrode, NM2 grid connects bias voltage Vbn1, NM2 source ground；3rd PMOS PM3 source electrode connects power supply, PM3's
Grid meets Vbp1, and PM3 drain electrode connects the 5th PMOS PM5 source electrode and PM4 source electrode simultaneously；PM5 grid connects PM2 leakage
Pole, PM5 drain electrode connect the 3rd NMOS tube NM3 drain and gate, NM3 source ground simultaneously；3rd resistor R3 positive termination
PM4 source electrode.
Negative input signal terminates the 7th PMOS PM7 grid, and PM7 source electrode meets the 6th PMOS PM6 drain electrode, PM6
Source electrode connect supply voltage VDD, PM7 grid and meet bias voltage Vbp1；8th PMOS PM8 source electrode connects PM6 drain electrode,
PM8 grid connects the tenth PMOS PM10 grid；PM7 drain electrode connects the 4th NMOS tube NM4 drain electrode, NM4 grid and leakage
It is extremely short to connect, NM4 source ground；PM8 drain electrode connects the 5th NMOS tube NM5 drain electrode, and NM5 grid meets NM4 grid, NM5
Source ground；PM10 grid and drain electrode are connected to the 6th NMOS tube NM6 drain electrode together, and NM6 grid connects bias voltage
Vbn1, NM6 source ground；9th PMOS PM9 source electrode connects power supply, and PM9 grid meets Vbp1, and PM9 drain electrode connects simultaneously
11st PMOS PM11 source electrode and PM10 source electrode；PM11 grid connects PM8 drain electrode, and PM11 drain electrode connects the 7th simultaneously
NMOS tube NM7 drain and gate, NM7 source ground；3rd resistor R3 negative terminal connects PM10 source electrode.
Double flat weighing apparatus local oscillator switch and load stage include：8th NMOS tube NM8 source ground, grid connect NM3 grid；The
Nine NMOS tube NM9 source ground, grid connect NM7 grid；NM8 drain electrode connects the tenth NMOS tube NM10 source electrode and the 11st
NMOS tube NM11 source electrode, NM9 drain electrode connect the 12nd NMOS tube NM12 source electrode and the 13rd NMOS tube NM13 source electrode；
The drain electrode that NM10 drain electrode meets output signal negative terminal OUTN, NM11 together with NM13 drain electrode connects output together with NM12 drain electrode
Signal anode OUTP；The grid that NM10 grids and NM12 grid meet local oscillation signal negative terminal LO-, NM11 and NM13 connects local oscillation signal
Anode LO+；12nd PMOS PM12 source electrode connects power supply, and grid connects the 13rd PMOS PM13 grid；First resistor R1
Positive pole PM12 and PM13 grid is connected to together with second resistance R2 positive pole, R1 negative pole is connected to together with PM12 drain electrode
OUTN, R2 negative pole are connected to OUTP together with PM13 drain electrode；First inductance L1 positive pole meets OUTN, and L1 negative pole meets OUTP；
First electric capacity C1 positive pole meets OUTP, and C1 negative pole meets OUTN；
Beneficial effect：A kind of described high-linearity upper mixer suitable for low supply voltage application scenario of the present invention
There is the features such as input amplitude of oscillation is big, and the linearity is high simultaneously.
Brief description of the drawings：
Fig. 1 is the high linearity low-voltage up-converter circuits figure of the present invention；
Fig. 2 is the two tone test figure of conventional gilbert's upconverter；
Fig. 3 is the two tone test figure of upconverter of the present invention.
Embodiment：
The upconverter is switched by transconductance stage, local oscillator and load is formed.Transconductance circuit is super using feedback loop construction
Level source follows structure, by input voltage complete copy to source-degeneration resistance both ends, so as to ensure that the higher linearity.Mutual conductance
Level caused by electric current by current mirror be injected into local oscillator switch, through local oscillator switch frequency conversion effect produce up-conversion signal and
Harmonic mixing product, the LC bandpass filtering networks positioned at load end filter out harmonic mixing product, export pure up-conversion signal.
Its structure can mainly be divided into linear transconductance level and double flat weighing apparatus local oscillator switch and three modules of load stage.
Specifically, linear transconductance level includes：Input signal just the first PMOS PM1 of termination grid, PM1 source electrode connect
14th PMOS PM14 drain electrode, the grid that PM14 source electrode meets supply voltage VDD, PM14 meet bias voltage Vbp1；Second
PMOS PM2 source electrode connects PM0 drain electrode, and PM2 grid connects the 4th PMOS PM4 grid；PM1 drain electrode connects the 14th
NMOS tube NM14 drain electrode, NM14 grid and drain electrode short circuit, NM14 source ground GND；PM2 drain electrode connects the first NMOS tube
NM1 drain electrode, NM1 grid connect NM0 grid, NM1 source ground；PM4 grid and drain electrode are connected to the 2nd NMOS together
Pipe NM2 drain electrode, NM2 grid connect bias voltage Vbn1, NM2 source ground；3rd PMOS PM3 source electrode connects power supply,
PM3 grid meets Vbp1, and PM3 drain electrode connects the 5th PMOS PM5 source electrode and PM4 source electrode simultaneously；PM5 grid connects
PM2 drain electrode, PM5 drain electrode connect the 3rd NMOS tube NM3 drain and gate, NM3 source ground simultaneously；3rd resistor R3's
Positive termination PM4 source electrode.
Negative input signal terminates the 7th PMOS PM7 grid, and PM7 source electrode meets the 6th PMOS PM6 drain electrode, PM6
Source electrode connect supply voltage VDD, PM7 grid and meet bias voltage Vbp1；8th PMOS PM8 source electrode connects PM6 drain electrode,
PM8 grid connects the tenth PMOS PM10 grid；PM7 drain electrode connects the 4th NMOS tube NM4 drain electrode, NM4 grid and leakage
It is extremely short to connect, NM4 source ground；PM8 drain electrode connects the 5th NMOS tube NM5 drain electrode, and NM5 grid meets NM4 grid, NM5
Source ground；PM10 grid and drain electrode are connected to the 6th NMOS tube NM6 drain electrode together, and NM6 grid connects bias voltage
Vbn1, NM6 source ground；9th PMOS PM9 source electrode connects power supply, and PM9 grid meets Vbp1, and PM9 drain electrode connects simultaneously
11st PMOS PM11 source electrode and PM10 source electrode；PM11 grid connects PM8 drain electrode, and PM11 drain electrode connects the 7th simultaneously
NMOS tube NM7 drain and gate, NM7 source ground；3rd resistor R3 negative terminal connects PM10 source electrode.
Double flat weighing apparatus local oscillator switch and load stage include：8th NMOS tube NM8 source ground, grid connect NM3 grid；The
Nine NMOS tube NM9 source ground, grid connect NM7 grid；NM8 drain electrode connects the tenth NMOS tube NM10 source electrode and the 11st
NMOS tube NM11 source electrode, NM9 drain electrode connect the 12nd NMOS tube NM12 source electrode and the 13rd NMOS tube NM13 source electrode；
The drain electrode that NM10 drain electrode meets output signal negative terminal OUTN, NM11 together with NM13 drain electrode connects output together with NM12 drain electrode
Signal anode OUTP；The grid that NM10 grids and NM12 grid meet local oscillation signal negative terminal LO-, NM11 and NM13 connects local oscillation signal
Anode LO+；12nd PMOS PM12 source electrode connects power supply, and grid connects the 13rd PMOS PM13 grid；First resistor R1
Positive pole PM12 and PM13 grid is connected to together with second resistance R2 positive pole, R1 negative pole is connected to together with PM12 drain electrode
OUTN, R2 negative pole are connected to OUTP together with PM13 drain electrode；First inductance L1 positive pole meets OUTN, and L1 negative pole meets OUTP；
First electric capacity C1 positive pole meets OUTP, and C1 negative pole meets OUTN；
The principle Analysis of the circuit is as follows：The upconverter of the present invention is fully differential structure, with left side difference channel
Exemplified by, PM14, PM1, PM2, NM14 and NM1 constitute error amplifier.Input intermediate-freuqncy signal positive pole connects the error amplifier
Positive input terminal, the anode of mutual conductance resistance is connected to the negative pole of error amplifier through level shift circuit.The output of error amplifier
End is connected to mutual conductance resistance by the follower being made up of PM5 and PM3.In the presence of negative-feedback circuit, transconductance circuit both ends
Voltage strictly follow the change of input difference voltage, so as to which input voltage to be converted into the electric current for flowing through the resistance.Due to PM3
For constant current source, therefore caused electric current all copies to NM8 through NM3, into local oscillator switching stage.Local oscillator switch weighs for double flat
Construction of switch, alternate conduction and shut-off in the presence of fully differential local oscillation signal, transconductance stage electric current is replaced into switch polarity and produced
Raw up-conversion current production；Useful signal is filtered out through load end LC frequency-selective networks in parallel.
Level shift circuit is made up of displacement pipe PM4 and current source NM2, and NM2 ensure that the electric current for flowing through PM4 is constant, from
And fix PM4 gate source voltage.Therefore the bias voltage at mutual conductance resistance both ends has moved up a VGS compared to input voltage, delays
With lower section PM5 and NM3 voltage margin.
Fig. 2 show the two tone test comparison diagram of conventional gilbert's upconverter and upconverter of the present invention.From figure
As can be seen that in the case that power output is located at 0dBm nearby, the IM3 of traditional gilbert's upconverter is higher than -30dBm,
And the IM3 of the upconverter of the present invention is then less than -50dBm, the higher linearity is embodied.
The foregoing is only the present invention better embodiment, protection scope of the present invention not using above-mentioned embodiment as
Limit, as long as equivalent modification that those of ordinary skill in the art are made according to disclosed content or change, should all include power
In protection domain described in sharp claim.
Claims (2)
1. a kind of collapsible linear transconductance upconverter, include linear transconductance level and double flat weighing apparatus local oscillator switch and load stage, electric current
The linear transconductance stage of signal replicates and is injected into after amplifying double flat weighing apparatus local oscillator switch, becomes in the frequency conversion effect generation through local oscillator switch
Frequency signal and harmonic mixing product, then filter out harmonic mixing product by load end, export pure up-conversion signal, its
It is characterised by：The linear transconductance level includes the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th
PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS, the 9th PMOS, the tenth PMOS, the 11st PMOS,
14 PMOSs, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube,
7th NMOS tube, the 14th NMOS tube and 3rd resistor, input signal are just terminating the grid of the first PMOS, the first PMOS
Source electrode connects the drain electrode of the 14th PMOS, and the source electrode of the 14th PMOS meets supply voltage Vdd, and the grid of the 14th PMOS connects
Bias voltage Vbp1；The source electrode of second PMOS connects the drain electrode of the 14th PMOS, and the grid of the second PMOS meets the 4th PMOS
The grid of pipe；The drain electrode of first PMOS connects the drain electrode of the 14th NMOS tube, the grid of the 14th NMOS tube and the short circuit that drains, the
The source ground GND of 14 NMOS tubes；The drain electrode of second PMOS connects the drain electrode of the first NMOS tube, and the grid of the first NMOS tube connects
NM0 grid, the source ground of the first NMOS tube；The grid of 4th PMOS and drain electrode are connected to the leakage of the second NMOS tube together
Pole, the grid of the second NMOS tube connect bias voltage Vbn1, the source ground of the second NMOS tube；The source electrode of 3rd PMOS connects electricity
Source, the grid of the 3rd PMOS meet Vbp1, and the drain electrode of the 3rd PMOS connects the source electrode and the 4th PMOS of the 5th PMOS simultaneously
Source electrode；The grid of 5th PMOS connects the drain electrode of the second PMOS, and the drain electrode of the 5th PMOS connects the 3rd NMOS tube simultaneously
Drain and gate, the source ground of the 3rd NMOS tube；The source electrode of the PMOS of positive termination the 4th of 3rd resistor；
Negative input signal terminates the grid of the 7th PMOS, and the source electrode of the 7th PMOS connects the drain electrode of the 6th PMOS, and the 6th
The source electrode of PMOS meets supply voltage Vdd, and the grid of the 7th PMOS connects the negative terminal of input signal；The source electrode of 8th PMOS connects
The drain electrode of 6th PMOS, the grid of the 8th PMOS connect the grid of the tenth PMOS；The drain electrode of 7th PMOS connects the 4th
The drain electrode of NMOS tube, the grid and drain electrode short circuit of the 4th NMOS tube, the source ground of the 4th NMOS tube；The drain electrode of 8th PMOS
The drain electrode of the 5th NMOS tube is connect, the grid of the 5th NMOS tube connects the grid of the 4th NMOS tube, the source ground of the 5th NMOS tube；The
The grid of ten PMOSs and drain electrode are connected to the drain electrode of the 6th NMOS tube together, and the grid of the 6th NMOS tube meets bias voltage Vbn1,
The source ground of 6th NMOS tube；The source electrode of 9th PMOS connects power supply, and the grid of the 9th PMOS meets bias voltage Vbp1, the
The drain electrode of nine PMOSs connects the source electrode of the 11st PMOS and the source electrode of the tenth PMOS simultaneously；The grid of 11st PMOS connects
The drain electrode of 8th PMOS, the drain electrode of the 11st PMOS connect the drain and gate of the 7th NMOS tube simultaneously, the 7th NMOS tube
Source ground；The negative terminal of 3rd resistor connects the source electrode of the tenth PMOS.
2. upconverter according to claim 1, it is characterised in that：The double flat weighing apparatus local oscillator switch and load stage include：
8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, the tenth
Two PMOSs, the 13rd PMOS, first resistor, second resistance, 3rd resistor, the first inductance and the first electric capacity, the 8th NMOS
The source ground of pipe, grid connect the grid of the 3rd NMOS tube；The source ground of 9th NMOS tube, grid connect the grid of the 7th NMOS tube
Pole；The drain electrode of 8th NMOS tube connects the source electrode of the tenth NMOS tube and the source electrode of the 11st NMOS tube, and the drain electrode of the 9th NMOS tube connects
The source electrode of 12nd NMOS tube and the source electrode of the 13rd NMOS tube；The drain electrode and the drain electrode one of the 13rd NMOS tube of tenth NMOS tube
Rise and connect output signal negative terminal, the drain electrode of the 11st NMOS tube connects output signal anode together with the drain electrode of the 12nd NMOS tube；The
Ten NMOS tube grids and the grid of the 12nd NMOS tube connect the grid of local oscillation signal negative terminal, the 11st NMOS tube and the 13rd NMOS tube
Pole connects local oscillation signal anode；The source electrode of 12nd PMOS connects power supply, and grid connects the grid of the 13rd PMOS；First resistor
Positive pole is connected to the grid of the 12nd PMOS and the 13rd PMOS together with the positive pole of second resistance, the negative pole of first resistor with
The drain electrode of 12nd PMOS is connected to signal negative terminal together, and the negative pole of second resistance is connected to together with the drain electrode of the 13rd PMOS
Output signal anode；The positive pole of first inductance connects output signal negative terminal, and negative pole connects output signal anode；The positive pole of first electric capacity connects
Output signal anode, negative pole connect output signal negative terminal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510706256.9A CN105207626B (en) | 2015-10-27 | 2015-10-27 | A kind of collapsible linear transconductance upconverter |
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| CN201510706256.9A CN105207626B (en) | 2015-10-27 | 2015-10-27 | A kind of collapsible linear transconductance upconverter |
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| CN105207626B true CN105207626B (en) | 2017-11-28 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| ITUB20160238A1 (en) * | 2016-01-22 | 2017-07-22 | St Microelectronics Srl | CORRESPONDING VOLTAGE-CURRENT CONVERTER, EQUIPMENT AND PROCEDURE |
| CN106899273B (en) * | 2016-12-27 | 2019-01-29 | 广州智慧城市发展研究院 | A kind of linear transconductance conversion circuitry |
| CN107231130B (en) * | 2017-05-24 | 2020-06-30 | 东南大学 | Up-converter based on transconductance tube local oscillator switch fusion structure |
| CN109282856B (en) * | 2018-11-13 | 2021-12-31 | 中国电子科技集团公司第四十七研究所 | Single-chip sensor capable of detecting temperature/voltage/current signals simultaneously |
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|---|---|---|---|---|
| CN101257282A (en) * | 2007-03-01 | 2008-09-03 | 晨星半导体股份有限公司 | Frequency mixer |
| CN101707475A (en) * | 2009-11-04 | 2010-05-12 | 捷顶微电子（上海）有限公司 | High-linearity upper frequency mixer with controllable output voltage and frequency mixing method |
| CN101873102A (en) * | 2010-04-30 | 2010-10-27 | 北京利云技术开发公司 | Up-conversion frequency mixer with high linearity and suitable for low-voltage work |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4559498B2 (en) * | 2008-02-28 | 2010-10-06 | 株式会社日立製作所 | Active mixer circuit and receiving circuit and millimeter wave communication terminal using the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257282A (en) * | 2007-03-01 | 2008-09-03 | 晨星半导体股份有限公司 | Frequency mixer |
| CN101707475A (en) * | 2009-11-04 | 2010-05-12 | 捷顶微电子（上海）有限公司 | High-linearity upper frequency mixer with controllable output voltage and frequency mixing method |
| CN101873102A (en) * | 2010-04-30 | 2010-10-27 | 北京利云技术开发公司 | Up-conversion frequency mixer with high linearity and suitable for low-voltage work |
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