CN102739173B - A kind of trsanscondutance amplifier, resistance, inductance and filter - Google Patents

Abstract

This application discloses a kind of trsanscondutance amplifier, resistance, inductance and filter, the trsanscondutance amplifier of the application adopts three groups of source degeneracy differential amplifiers to form, wherein one group of amplifier is by the 7th PMOS, 8th PMOS, 5th PMOS and the 6th PMOS composition, second group of amplifier is by the 9th PMOS, tenth PMOS, 11 PMOS and the 12 PMOS composition, 3rd group of amplifier is by the 17 PMOS, 18 PMOS, 19 PMOS and the 20 PMOS composition, the output interconnection of three groups of amplifiers, thus the mode of current subtraction can be utilized to eliminate cubic term harmonic wave, thus realize the low-power consumption high linearity of trsanscondutance amplifier.And then simulate by described trsanscondutance amplifier the resistance, inductance and the circuit that is made up of described resistance and/or inductance that obtain and also can realize low-power consumption high linearity.

Description

A kind of trsanscondutance amplifier, resistance, inductance and filter

Technical field

The application relates to circuit field, particularly relates to a kind of trsanscondutance amplifier, resistance, inductance and filter.

Background technology

Along with the communication technology, especially the develop rapidly of mobile communication technology and computing technique, as a key modules in Modern receivers especially zero intermediate frequency receiver, transconductance-capacitor (Gm-C) filter can carry out the filtering process of signal after the mixer, the signal that variable gain amplifier for rear class provides scattering frequency spectrum less, can effectively at variable gain amplifier (VGA, VariableGainAmplifier), analog/digital converter (ADC, Analog-to-DigitalConverter) preliminary treatment signal before, can prevent again the variable gain amplifier of rear class due to out of band signal excessive and saturated.

In mobile digital video broadcast system, be positioned at the Gm-C filter of receiver intermediate-frequency section, need the input signal that process is larger, require that filter ensures the higher linearity when power consumption is very low.

Summary of the invention

In view of this, the technical problem that the application will solve is, provides a kind of trsanscondutance amplifier, resistance, inductance and filter, and filter can be made to ensure the higher linearity when power consumption is very low.

For this reason, the embodiment of the present application adopts following technical scheme:

A kind of trsanscondutance amplifier, comprising:

The grid of the first NMOS tube connects the tuning voltage input of trsanscondutance amplifier; The source ground of the first NMOS tube, the drain electrode of drain electrode connection second PMOS;

Second PMOS, the 3rd PMOS, the 4th PMOS, the 13 PMOS, the 14 PMOS, the 15 PMOS, the grid of the 16 PMOS, source electrode are connected respectively; And the grid of the second PMOS is connected with the drain electrode of the second PMOS; The source electrode of the second PMOS connects the power voltage input terminal of trsanscondutance amplifier;

The drain electrode of the 3rd PMOS connects the source electrode of the drain electrode of the 5th PMOS, the source electrode of the 6th PMOS and the 7th PMOS respectively;

The drain electrode of the 4th PMOS connects the source electrode of the source electrode of the 5th PMOS, the drain electrode of the 6th PMOS and the 8th PMOS respectively;

The drain electrode of the 13 PMOS connects the source electrode of the 9th PMOS, the source electrode of the 11 PMOS and the drain electrode of the 12 PMOS respectively;

The drain electrode of the 14 PMOS connects the source electrode of the tenth PMOS, the drain electrode of the 11 PMOS and the source electrode of the 12 PMOS respectively;

The drain electrode of the 15 PMOS connects the drain electrode of the 17 PMOS, the source electrode of the 18 PMOS and the source electrode of the 19 PMOS respectively;

The drain electrode of the 16 PMOS connects the source electrode of the 17 PMOS, the drain electrode of the 18 PMOS and the source electrode of the 20 PMOS respectively;

The grid of the 6th PMOS, the grid of the 8th PMOS, the grid of the 9th PMOS and the grid of the 11 PMOS are all connected with the normal phase input end of trsanscondutance amplifier;

The grid of the grid of the tenth PMOS, the grid of the 12 PMOS, the grid of the 18 PMOS and the 19 PMOS is all connected with the negative-phase input of trsanscondutance amplifier;

The grid of the 5th PMOS, the grid of the 7th PMOS, the grid of the 17 PMOS and the equal ground connection of grid of the 20 PMOS;

The grid of the 21 NMOS tube is connected with the grid of the 22 NMOS tube, and connects the common mode feedback voltage end of trsanscondutance amplifier; The source electrode of the 21 NMOS tube and the source ground of the 22 NMOS tube;

The drain electrode of the 7th PMOS, the drain electrode of the 9th PMOS, the drain electrode of the 19 PMOS and the drain electrode of the 21 NMOS tube are all connected with the negative output of trsanscondutance amplifier;

The drain electrode of the 8th PMOS, the drain electrode of the tenth PMOS, the drain electrode of the 20 PMOS and the drain electrode of the 22 NMOS tube are all connected with the positive output end of trsanscondutance amplifier.

Also comprise: the source electrode of the 23 PMOS and the source electrode of the 24 PMOS connect the power voltage input terminal of trsanscondutance amplifier; The grid of the 23 PMOS is connected biased electrical pressure side with the grid of the 24 PMOS;

The drain electrode of the 23 PMOS connects the source electrode of the 25 PMOS and the source electrode of the 26 PMOS respectively; The drain electrode of the 24 PMOS connects the source electrode of the 27 PMOS and the source electrode of the 28 PMOS respectively;

The grid of the 25 PMOS connects the positive output end of trsanscondutance amplifier, the drain electrode of drain electrode connection the 30 NMOS tube and the drain electrode of the 28 PMOS;

The grid of the 26 PMOS is connected reference voltage end with the grid of the 27 PMOS, and drain electrode connects the drain electrode of the 27 PMOS and the drain electrode of the 29 NMOS tube respectively;

The grid of the 28 PMOS connects the negative output of trsanscondutance amplifier;

The grid of the 29 NMOS tube is connected common mode feedback voltage end with drain electrode; The source ground of the 29 NMOS tube;

The grid of the 30 NMOS tube is connected with drain electrode, source ground.

A kind of resistance, comprises trsanscondutance amplifier according to claim 1, wherein,

The negative output of trsanscondutance amplifier is connected with the common mode feedback voltage end of trsanscondutance amplifier;

The positive output end of trsanscondutance amplifier is connected with the negative-phase input of trsanscondutance amplifier, and the tie point of this connection is as the first end of resistance;

The negative-phase input of trsanscondutance amplifier is as the second end of resistance.

A kind of resistance, comprises trsanscondutance amplifier according to claim 2, wherein,

The normal phase input end of trsanscondutance amplifier is connected with the negative output of trsanscondutance amplifier, and the tie point of this connection is as the first end of described resistance;

The negative-phase input of trsanscondutance amplifier is connected with the positive output end of trsanscondutance amplifier, and the tie point of this connection is as the second end of described resistance.

A kind of inductance, comprises two trsanscondutance amplifiers according to claim 1, is respectively the first trsanscondutance amplifier and the second trsanscondutance amplifier, wherein,

The negative output of the first trsanscondutance amplifier is connected with the common mode feedback voltage end of the first trsanscondutance amplifier; The negative output of the second trsanscondutance amplifier is connected with the common mode feedback voltage end of the second trsanscondutance amplifier;

The first end of inductance by the first capacity earth, and is connected with the positive output end of the first trsanscondutance amplifier, the normal phase input end of the second trsanscondutance amplifier respectively; Second end of inductance is connected with the normal phase input end of the first trsanscondutance amplifier, the positive output end of the second trsanscondutance amplifier respectively;

The negative-phase input ground connection of the first trsanscondutance amplifier, the negative-phase input ground connection of the second trsanscondutance amplifier.

A kind of filter, comprises the trsanscondutance amplifier described in any one of claim 1 to 2, and/or, the resistance described in any one of claim 3 to 4, and/or, inductance according to claim 5.

Also comprise phase-locked loop tuner, wherein,

The output of voltage controlled oscillator connects the first input end of phase frequency detector, and the second input of phase frequency detector receives reference frequency signal; The output of phase frequency detector is by the input of charge pump linkloop filter, and the output of loop filter connects the tuning voltage input in the input of voltage controlled oscillator and filter respectively.

Technique effect for technique scheme is analyzed as follows:

The trsanscondutance amplifier of the application adopts three groups of source degeneracy differential amplifiers to form, wherein one group of amplifier is by the 7th PMOS, 8th PMOS, 5th PMOS and the 6th PMOS composition, second group of amplifier is by the 9th PMOS, tenth PMOS, 11 PMOS and the 12 PMOS composition, 3rd group of amplifier is by the 17 PMOS, 18 PMOS, 19 PMOS and the 20 PMOS composition, the output interconnection of three groups of amplifiers, thus the mode of current subtraction can be utilized to eliminate cubic term harmonic wave, thus realize the low-power consumption high linearity of trsanscondutance amplifier, and then can make to use the filter of described trsanscondutance amplifier to ensure the higher linearity when power consumption is very low.

Accompanying drawing explanation

Fig. 1 is the application's trsanscondutance amplifier first embodiment schematic diagram;

Fig. 2 is the application's common mode feedback circuit structure schematic diagram;

Fig. 3 is the application's resistance first embodiment schematic diagram;

Fig. 4 is the first embodiment schematic diagram of the application's inductance;

Fig. 5 is the application's resistance the 3rd embodiment schematic diagram;

Fig. 6 is a kind of 7 rank elliptic filter structural representations of the application;

Fig. 7 is the application's filter first embodiment schematic diagram;

Fig. 8 is the application's filter second embodiment schematic diagram;

The simplification circuit structure diagram that Fig. 9 is trsanscondutance amplifier described in the application.

Embodiment

Below, the realization of the application's trsanscondutance amplifier, resistance, inductance and filter is described with reference to the accompanying drawings.

Fig. 1 is the application's trsanscondutance amplifier structural representation, and as described in Figure 1, this trsanscondutance amplifier comprises:

The grid of the first NMOS tube M1 connects the tuning voltage input VTUNE of trsanscondutance amplifier; The source ground of the first NMOS tube M1, the drain electrode of drain electrode connection second PMOS M2;

Second PMOS M2, the 3rd PMOS M3, the 4th PMOS M4, the 13 PMOS M13, the 14 PMOS M14, the 15 PMOS M15, the grid of the 16 PMOS M16, source electrode are connected respectively; And the grid of the second PMOS M2 is connected with the drain electrode of the second PMOS M2; The source electrode of the second PMOS M2 connects the power voltage input terminal VC of trsanscondutance amplifier;

The drain electrode of the 3rd PMOS M3 connects the source electrode of the drain electrode of the 5th PMOS M5, the source electrode of the 6th PMOS M6 and the 7th PMOS M7 respectively;

The drain electrode of the 4th PMOS M4 connects the source electrode of the source electrode of the 5th PMOS M5, the drain electrode of the 6th PMOS M6 and the 8th PMOS M8 respectively;

The drain electrode of the 13 PMOS M13 connects the source electrode of the 9th PMOS M9, the source electrode of the 11 PMOS M11 and the drain electrode of the 12 PMOS M12 respectively;

The drain electrode of the 14 PMOS M14 connects the source electrode of the tenth PMOS M10, the drain electrode of the 11 PMOS M11 and the source electrode of the 12 PMOS M12 respectively;

The drain electrode of the 15 PMOS M15 connects the drain electrode of the 17 PMOS M17, the source electrode of the 18 PMOS M18 and the source electrode of the 19 PMOS M19 respectively;

The drain electrode of the 16 PMOS M16 connects the source electrode of the 17 PMOS M17, the drain electrode of the 18 PMOS M18 and the source electrode of the 20 PMOS M20 respectively;

The grid of the 6th PMOS M6, the grid of the 8th PMOS M8, the grid of the 9th PMOS M9 and the grid of the 11 PMOS M11 are all connected with the normal phase input end VINP of trsanscondutance amplifier;

The grid of the grid of the tenth PMOS M10, the grid of the 12 PMOS M12, the grid of the 18 PMOS M18 and the 19 PMOS M19 is all connected with the negative-phase input VINN of trsanscondutance amplifier;

The grid of the 5th PMOS M5, the grid of the 7th PMOS M7, the grid of the 17 PMOS M17 and the equal ground connection of grid of the 20 PMOS M20;

The grid of the 21 NMOS tube M21 is connected with the grid of the 22 NMOS tube M22, and connects the common mode feedback voltage end VCMFB of trsanscondutance amplifier; The source electrode of the 21 NMOS tube M21 and the source ground of the 22 NMOS tube M22;

The drain electrode of the drain electrode of the 7th PMOS M7, the drain electrode of the 9th PMOS M9, the drain electrode of the 19 PMOS M19 and the 21 NMOS tube M21 is all connected with the negative output VOUTN of trsanscondutance amplifier;

The drain electrode of the 8th PMOS M8, the drain electrode of the tenth PMOS M10, the drain electrode of the 20 PMOS M20 and the drain electrode of the 22 NMOS tube M22 are all connected with the positive output end VOUTP of trsanscondutance amplifier.

Trsanscondutance amplifier structure shown in Fig. 1 adopts three groups of source degeneracy differential amplifiers to form, wherein one group of amplifier is by the 7th PMOS M7, 8th PMOS M8, 5th PMOS M5 and the 6th PMOS M6 forms, second group of amplifier is by the 9th PMOS M9, tenth PMOS M10, 11 PMOS M11 and the 12 PMOS M12 forms, 3rd group of amplifier is by the 17 PMOS, 18 PMOS, 19 PMOS and the 20 PMOS composition, the output interconnection of three groups of amplifiers, thus the mode of current subtraction can be utilized to eliminate cubic term harmonic wave, thus realize the low-power consumption high linearity of trsanscondutance amplifier.

And then described trsanscondutance amplifier is applied to filter, such as, in Gm-C filter time, the low-power consumption high linearity of filter can be realized.

Trsanscondutance amplifier shown in Fig. 1 is in practical application scene, when needing trsanscondutance amplifier to realize double-width grinding Single-end output, then the negative output of trsanscondutance amplifier can be connected with the common mode feedback voltage end VCMFB of trsanscondutance amplifier, realizes the double-width grinding Single-end output of trsanscondutance amplifier.

Or, in practical application scene, when needing trsanscondutance amplifier to realize the output of double-width grinding both-end, generally need to control the common mode electrical level of the trsanscondutance amplifier shown in Fig. 1, also namely the voltage of the common mode feedback voltage end VCMFB of trsanscondutance amplifier is controlled, now, trsanscondutance amplifier shown in Fig. 1 may further include common mode feedback circuit as shown in Figure 2, form another kind of trsanscondutance amplifier structure, as shown in Figure 2, described common mode feedback circuit comprises:

The source electrode of the 23 PMOS M23 and the source electrode of the 24 PMOS M24 connect the power voltage input terminal VC of trsanscondutance amplifier; The grid of the 23 PMOS M23 is connected the biased electrical pressure side VBIAS of trsanscondutance amplifier with the grid of the 24 PMOS M24;

The drain electrode of the 23 PMOS M23 connects the source electrode of the 25 PMOS M25 and the source electrode of the 26 PMOS M26 respectively; The drain electrode of the 24 PMOS M24 connects the source electrode of the 27 PMOS M27 and the source electrode of the 28 PMOS M28 respectively;

The grid of the 25 PMOS M25 connects the positive output end VOUTP of trsanscondutance amplifier, the drain electrode of drain electrode connection the 30 NMOS tube M30 and the drain electrode of the 28 PMOS M28;

The grid of the 26 PMOS M26 is connected the reference voltage end VREF of trsanscondutance amplifier with the grid of the 27 PMOS M27, drain electrode connects the drain electrode of the 27 PMOS M27 and the drain electrode of the 29 NMOS tube M29 respectively;

The grid of the 28 PMOS M28 connects the negative output VOUTN of trsanscondutance amplifier;

The grid of the 29 NMOS tube M29 is connected the common mode feedback voltage end VCMFB of trsanscondutance amplifier with drain electrode; The source ground of the 29 NMOS tube M29;

The grid of the 30 NMOS tube M30 is connected with drain electrode, source ground.

For the circuit shown in Fig. 1 and Fig. 2, the voltage that the tuning voltage input VTUNE of trsanscondutance amplifier inputs can be a certain constant voltage, or, also can be the adjustable voltage in a certain scope, concrete voltage value can be determined according to applied environment in actual applications, does not limit here.

General, described biased electrical pressure side VBIAS can connect the grid of the second PMOS M2, and the voltage of biased electrical pressure side VBIAS is changed with the voltage value of tuning voltage input VTUNE; Or can be also the voltage that bias voltage end VBIAS inputs a certain fixed value, concrete voltage value can be determined according to applied environment in actual applications, does not limit here.

General, can input the voltage of a certain fixed value for reference voltage end VREF, concrete voltage value can be determined according to applied environment in actual applications, does not limit here.

Power voltage input terminal VC generally connects the power supply of trsanscondutance amplifier, for powering for each device in trsanscondutance amplifier.

Wherein, when using resistance or inductance as needed in circuit such as filter in actual applications, the trsanscondutance amplifier shown in above-mentioned Fig. 1 or Fig. 1 and Fig. 2 can be used to combine the simulation that the trsanscondutance amplifier obtained carries out resistance or inductance.

Concrete, in the application scenarios needing the trsanscondutance amplifier using double-width grinding Single-end output, can the trsanscondutance amplifier artifical resistance shown in Fig. 1 or inductance be passed through, make the resistance in circuit and inductance become active device from passive device; The trsanscondutance amplifier being illustrated in figure 4 Fig. 1 simulates the electric resistance structure schematic diagram obtained, and the trsanscondutance amplifier being illustrated in figure 5 Fig. 1 simulates the induction structure schematic diagram obtained;

In the application scenarios needing the trsanscondutance amplifier using double-width grinding both-end to export, can combine by Fig. 1 and Fig. 2 the trsanscondutance amplifier artifical resistance or inductance that obtain; Be illustrated in figure 6 Fig. 1 and Fig. 2 to combine the trsanscondutance amplifier obtained and simulate the electric resistance structure schematic diagram obtained.

As shown in Figure 3, trsanscondutance amplifier is simulated the electric resistance structure obtained and is comprised:

Trsanscondutance amplifier gm, described trsanscondutance amplifier gm can use the structure shown in Fig. 1 to realize;

In addition, this resistance also comprises:

The negative output of trsanscondutance amplifier gm is connected (not shown) with the common mode feedback voltage end of trsanscondutance amplifier gm;

The positive output end of trsanscondutance amplifier gm is connected with the negative-phase input of trsanscondutance amplifier gm, and the tie point of this connection is as the first end of resistance;

The normal phase input end of trsanscondutance amplifier gm is as the second end of resistance.

Wherein, this resistance can as earth resistance or floating earth resistance, and when having one end ground connection in the first end of resistance described in Fig. 3 and the second end, when the other end connects other devices, this resistance is earth resistance; When the first end of resistance is all connected other devices with the second end, this resistance is floating earth resistance.

Fig. 4 simulates the inductance obtained for the trsanscondutance amplifier shown in Fig. 1, and as shown in Figure 4, this inductance comprises:

Trsanscondutance amplifier shown in two Fig. 1, is respectively the first trsanscondutance amplifier gm1 and the second trsanscondutance amplifier gm2, wherein,

The negative output of the first trsanscondutance amplifier gm1 is connected (not shown) with the common mode feedback voltage end of the first trsanscondutance amplifier gm1; The negative output of the second trsanscondutance amplifier gm2 is connected (not shown) with the common mode feedback voltage end of the second trsanscondutance amplifier gm2;

The first end of described inductance by the first electric capacity C1 ground connection, and is connected with the positive output end of the first trsanscondutance amplifier gm1, the normal phase input end of the second trsanscondutance amplifier gm2 respectively; Second end of inductance is connected with the normal phase input end of the first trsanscondutance amplifier gm1, the positive output end of the second trsanscondutance amplifier gm2 respectively;

The negative-phase input ground connection of the first trsanscondutance amplifier gm1, the negative-phase input ground connection of the second trsanscondutance amplifier gm2.

Fig. 5 is that trsanscondutance amplifier simulates the resistance schematic diagram obtained, and comprising:

Trsanscondutance amplifier gm, this trsanscondutance amplifier can combine by Fig. 1 and Fig. 2 the trsanscondutance amplifier obtained and realize;

This resistance also comprises:

The normal phase input end of trsanscondutance amplifier gm is connected with the negative output of trsanscondutance amplifier gm, and the tie point of this connection is as the first end of described resistance;

The negative-phase input of trsanscondutance amplifier gm is connected with the positive output end of trsanscondutance amplifier gm, and the tie point of this connection is as the second end of described resistance.

Resistance shown in above Fig. 3 ~ Fig. 5 and inductance are active device, in actual applications can passive resistance in corresponding replacement circuit and passive inductance, such as in 7 rank elliptic filter structures shown in Fig. 6, namely resistance R1 and R2 that the resistance shown in Fig. 3 or Fig. 5 realizes in Fig. 6 can be used, and do not use passive resistance, use the inductance in Fig. 4 to realize inductance L 1 in Fig. 6, L2, L3, and do not use passive inductance.Due to the low-power consumption high linearity of trsanscondutance amplifier wherein, therefore, ensure that low-power consumption and the high linearity of described resistance and the inductance realized by described trsanscondutance amplifier, and then relative to using the circuit of passive resistance and/or inductance, such as filter, the characteristic such as cut-off frequency, the linearity comprising described resistance and the/filter of inductance, not with the impact of the factor such as temperature, process corner, makes filter power consumption low and the linearity is high.

Certainly, the filter shown in Fig. 6 is only citing, and the resistance of the application and inductance can also be applied to other filters, even other comprise in the circuit structure of resistance and/or inductance, the power consumption of these circuit can be reduced equally, improve the linearity.

For the filter comprising resistance described in the application and/or inductance, described filter may further include: phase-locked loop tuner, and as shown in Figure 7, described phase-locked loop tuner can comprise:

The output of voltage controlled oscillator 810 connects the first input end of phase frequency detector 820, and the second input of phase frequency detector 820 receives reference frequency signal; The output of phase frequency detector 820 is by the input of charge pump 830 linkloop filter 840, and the output of loop filter 840 connects the tuning voltage input VTUNE of each trsanscondutance amplifier in the input of voltage controlled oscillator 810 and filter respectively.

Described voltage controlled oscillator 810 is for generation of a signal source.The frequency of oscillation of described voltage controlled oscillator 810 changes with filter cutoff frequency change.

Trsanscondutance amplifier described in the embodiment of the present application forms two non-damping integrators, connects into positive feedback form, just constitutes described voltage controlled oscillator 810.Its frequency of oscillation is along with the various characteristics of trsanscondutance amplifier, and such as gain bandwidth product, common-mode rejection ratio etc. changes, thus is followed the tracks of by its output voltage frequency and reflect trsanscondutance amplifier and overall filter cut-off frequency characteristic.

Phase frequency detector 820 compares at numeric field for the frequency of the output signal that exported by voltage controlled oscillator 810 and reference frequency signal and phase place, exports a succession of digital high-low signal, is controlled the charging and discharging of charge pump 830 by described digital high-low signal.

Charge pump 830 carries out charging and discharging under controlling in the output signal of phase frequency detector 820, concrete, be that digital signal is converted to analog signal, then by this analog signal by feeding back to voltage controlled oscillator 810 after loop filter 840 filtering, form Closed loop operation.

The analog signal smoothing filtering of loop filter 840 for exporting charge pump 830.

Can reduce by described filtering the burr of analog signal and signal jitter that charge pump 830 exports, thus reduce phase noise, promote the accuracy of whole phase-locked loop tuning circuit.

Wherein, described voltage controlled oscillator 810, phase frequency detector 820, charge pump 830 and loop filter 840 constitute phase-locked loop tuner, the tuning of input voltage in tuning voltage input VTUNE can be realized in trsanscondutance amplifier, and then under less consumption conditions, ensures the precision of tuning precision and filter cutoff frequency.

Such as, described phase-locked loop tuner specifically can be realized by the structure shown in Fig. 8, wherein:

The output of voltage controlled oscillator connects the first input end of multiplier, second input of multiplier receives reference frequency signal, the output of multiplier connects the input of low pass filter, first output of low pass filter connects the input of voltage controlled oscillator, and the second output of low pass filter connects the tuning voltage input of each trsanscondutance amplifier in filter.Loop filter 840 is realized by described low pass filter, and described phase frequency detector 820, charge pump 830 are realized by described multiplier.

Finally, the principle can eliminating cubic term harmonic wave for the trsanscondutance amplifier shown in Fig. 1 is described:

To simplify the analysis, the transconductance amplifier circuit shown in Fig. 1 is reduced to circuit diagram structure as shown in Figure 9.Wherein each little module represents one group of differential amplifier in trsanscondutance amplifier, and the numerical value on it represents the relative scale size of its mutual conductance.

Because input signal is made up of difference mode signal and common-mode signal components, as seen from Figure 9, wherein an input end grounding of two differential amplifiers, known by deriving, due to the cross-couplings connected mode exported, integrated circuit still can use as a full-differential circuits.

Suppose size of current and flow to as shown in Figure 1, the output current i that trsanscondutance amplifier is total _ofor:

i _o＝i ₀₁-i ₀₂-i ₀₃(1)

Wherein, i _orepresent total output current of trsanscondutance amplifier, due to the trsanscondutance amplifier employing in Fig. 1 is double-width grinding both-end output form, the total current i of output _obe three differences exporting branch current, i _o1represent the half of first group of amplifier output current that the 7th PMOS M7 and the 8th PMOS M8 is formed, i _o2represent the half of second group of amplifier output current that the 9th PMOS M9 and the tenth PMOS M10 is formed; i _o3represent the half of second group of amplifier output current that the 19 PMOS M9 and the 20 PMOS M10 is formed; Here the output current of definition three amplifiers is the feasibilities in order to mathematically prove high linearity.

Suppose that metal-oxide-semiconductors all in circuit all works in saturation region, then according to leakage current saturation region formula:

i _d＝K(v _g-v _s-V _th) ²(2)

$K=\frac{1}{2}{\mathrm{\μC}}_{ox}\left(\frac{W}{L}\right)---\left(3\right)$

Wherein, i _drepresent the drain electrode output current of single metal-oxide-semiconductor; K represents the current coefficient of metal-oxide-semiconductor under certain technique, and it is the parameter determined by the breadth length ratio W/L of technique and metal-oxide-semiconductor, as long as technique and breadth length ratio are determined, it is exactly a definite value; Vg refers to the grid voltage of metal-oxide-semiconductor; Vs refers to the source voltage of metal-oxide-semiconductor; Vth refers to the threshold voltage of metal-oxide-semiconductor, and it is also the parameter determined by technique; W represents the width of metal-oxide-semiconductor, and L represents the length of metal-oxide-semiconductor; μ is carrier mobility, C _oxfor unit area gate oxidation district electric capacity.

According to g _mwith the relation of direct current saturation voltage:

g _m＝2KV _dssat(4)

$V_{dssat}=V_g-V_s-V_{th}=\sqrt{\frac{I_d}{2K}}---\left(5\right)$

Wherein, W represents the width of metal-oxide-semiconductor, and L represents the length of metal-oxide-semiconductor; V _dssatrepresent the direct current saturation voltage of metal-oxide-semiconductor, in FIG, each root metal-oxide-semiconductor has its direct current saturation voltage, and this direct current saturation voltage can affect the operating state (saturation region, linear zone, sub-threshold region, cut-off region) of every root metal-oxide-semiconductor, and then affects the properties of trsanscondutance amplifier.

Process for simplifying the analysis, adopts Taylor series at v _in=0 by v _inexpansion can obtain

$i_0=\underset{n=0}{\Σ}{G}_{M(2n+1)}\·{v_{in}}^{2n+1}---\left(6\right)$

Wherein $G_{Mj}=\frac{g_m}{2^{2(j-1)}{V_{dssat}}^{j-1}}---\left(7\right);$

Definition source degeneracy factor $N_{r1,2}=G_{M1}\·\frac{1}{g_{m5,6,11,12,17,18}},$ Wherein for working in the equivalent resistance of dark triode region five PMOS M5, the 6th PMOS M6, the 11 PMOS M11, the 12 PMOS M12, the 17 PMOS M17, the 18 PMOS M18.Formula (6) and formula (7) substitution (1) are carried out Simplified analysis can obtain (only considering once item and cubic term):

$\begin{array}{c}{i}_o=\frac{G_{M1}}{G_{M1}\frac{1}{g_{5,6,11,12,17,18}}+1}\left(\frac{3}{7}\right(\frac{v_{in}}{2}+v_{cm})-\frac{3}{7}(-\frac{v_{in}}{2}+v_{cm})-\frac{1}{7}{v}_{in})\\ -\frac{G_{M3}}{{(G_{M1}\frac{1}{g_{5,6,11,12,17,18}}+1)}^4}(\frac{3}{7}{\left(\frac{v_{in}}{2}+v_{cm}\right)}^3-\frac{3}{7}{\left(-\frac{v_{in}}{2}+v_{cm}\right)}^3-\frac{1}{7}{v_{in}}^3)\\ -\frac{G_{M5}+\frac{1}{g_{5,6,11,12,17,18}}(G_{M1}{G}_{M5}-3{G_{M3}}^2)}{{(G_{M1}\frac{1}{g_{5,6,11,12,17,18}}+1)}^7}(\frac{3}{7}{\left(\frac{v_{in}}{2}+v_{cm}\right)}^5-\frac{3}{7}{\left(-\frac{v_{in}}{2}+v_{cm}\right)}^5-\frac{1}{7}{v_{in}}^5)\end{array}---\left(8\right)$

Abbreviation can obtain:

$\begin{array}{c}{i}_o=\frac{2}{7}\frac{G_{M1}}{(G_{M1}\frac{1}{g_{5,6,11,12,17,18}}+1)}{v}_{in}\\ -\frac{6}{7}\frac{G_{M3}}{{(G_{M1}\frac{1}{g_{5,6,11,12,17,18}}+1)}^4}{v}_{in}{v_{cm}}^2\\ +\frac{13}{112}\frac{G_{M5}+\frac{1}{g_{5,6,11,12,17,18}}(G_{M1}{G}_{M5}-3{G_{M3}}^2)}{{(G_{M1}\frac{1}{g_{5,6,11,12,17,18}}+1)}^7}{v_{in}}^5\end{array}$

Under deep submicron process, v _cmmuch smaller than 1, then the triple-frequency harmonics item of trsanscondutance amplifier can be similar to elimination, and only remaining less quintuple harmonics component, total harmonic distortion (THD) will reduce greatly.Total harmonic distortion can be similar to as follows:

$THD=\frac{13(G_{M5}+\frac{1}{g_{5,6,11,12,17,18}}(G_{M1}{G}_{M5}-3{G_{M3}}^2\left)\right)}{28G_{M1}{(1+G_{M1}\frac{1}{g_{m5,6,11,12,17,18}})}^6}{v_{in}}^4.$

Known based on above analysis, the trsanscondutance amplifier shown in Fig. 1 can be similar to eliminates triple-frequency harmonics item, improves THD.And then, the high linearity can be ensured under low-power consumption.

In addition, the trsanscondutance amplifier of the embodiment of the present application, is formed by the source degeneracy trsanscondutance amplifier cross-couplings of three different proportions, can under deep-submicron CMOS process condition, realize the very high linearity with lower consumption conditions, its linearity is very little with changes in environmental conditions.

The trsanscondutance amplifier of the embodiment of the present application and/or resistance and/or inductance, can be applicable in various existing circuit, especially filter, such as, in Gm-C filter, to meet the receiver system requirement that especially zero intermediate frequency reciver system linear degree is high; In addition, described trsanscondutance amplifier can also be applied in mobile video Signal transmissions and switched-capacitor circuit, meets both requirements to high linearity.And, when being applied in Gm-C filter, tuning precision and filter cutoff frequency precision can be ensured under less consumption conditions.

The element of transconductance amplifier circuit all adopts CMOS transistor, does not use other elements such as resistance, thus can reach coupling in good sheet.

In addition, the trsanscondutance amplifier of the embodiment of the present application, under deep sub-micron CMOS standard process, can adapt to lower supply voltage, meets current low voltage CMOS trend, and lower supply voltage contributes to promoting the trsanscondutance amplifier linearity.

The above is only the preferred implementation of the application; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the protection range of the application.

Claims (7)

1. a trsanscondutance amplifier, is characterized in that, comprising:

The grid of the first NMOS tube connects the tuning voltage input of trsanscondutance amplifier; The source ground of the first NMOS tube, the drain electrode of drain electrode connection second PMOS;

Second PMOS, the 3rd PMOS, the 4th PMOS, the 13 PMOS, the 14 PMOS, the 15 PMOS, the grid of the 16 PMOS, source electrode are connected respectively; And the grid of the second PMOS is connected with the drain electrode of the second PMOS; The source electrode of the second PMOS connects the power voltage input terminal of trsanscondutance amplifier;

The drain electrode of the 3rd PMOS connects the source electrode of the drain electrode of the 5th PMOS, the source electrode of the 6th PMOS and the 7th PMOS respectively;

The drain electrode of the 4th PMOS connects the source electrode of the source electrode of the 5th PMOS, the drain electrode of the 6th PMOS and the 8th PMOS respectively;

The drain electrode of the 13 PMOS connects the source electrode of the 9th PMOS, the source electrode of the 11 PMOS and the drain electrode of the 12 PMOS respectively;

The drain electrode of the 14 PMOS connects the source electrode of the tenth PMOS, the drain electrode of the 11 PMOS and the source electrode of the 12 PMOS respectively;

The drain electrode of the 15 PMOS connects the drain electrode of the 17 PMOS, the source electrode of the 18 PMOS and the source electrode of the 19 PMOS respectively;

The drain electrode of the 16 PMOS connects the source electrode of the 17 PMOS, the drain electrode of the 18 PMOS and the source electrode of the 20 PMOS respectively;

The grid of the 6th PMOS, the grid of the 8th PMOS, the grid of the 9th PMOS and the grid of the 11 PMOS are all connected with the normal phase input end of trsanscondutance amplifier;

The grid of the grid of the tenth PMOS, the grid of the 12 PMOS, the grid of the 18 PMOS and the 19 PMOS is all connected with the negative-phase input of trsanscondutance amplifier;

The grid of the 5th PMOS, the grid of the 7th PMOS, the grid of the 17 PMOS and the equal ground connection of grid of the 20 PMOS;

The grid of the 21 NMOS tube is connected with the grid of the 22 NMOS tube, and connects the common mode feedback voltage end of trsanscondutance amplifier; The source electrode of the 21 NMOS tube and the source ground of the 22 NMOS tube;

The drain electrode of the 7th PMOS, the drain electrode of the 9th PMOS, the drain electrode of the 19 PMOS and the drain electrode of the 21 NMOS tube are all connected with the negative output of trsanscondutance amplifier;

The drain electrode of the 8th PMOS, the drain electrode of the tenth PMOS, the drain electrode of the 20 PMOS and the drain electrode of the 22 NMOS tube are all connected with the positive output end of trsanscondutance amplifier.

2. trsanscondutance amplifier according to claim 1, is characterized in that, also comprises:

The source electrode of the 23 PMOS and the source electrode of the 24 PMOS connect the power voltage input terminal of trsanscondutance amplifier; The grid of the 23 PMOS is connected biased electrical pressure side with the grid of the 24 PMOS;

The drain electrode of the 23 PMOS connects the source electrode of the 25 PMOS and the source electrode of the 26 PMOS respectively; The drain electrode of the 24 PMOS connects the source electrode of the 27 PMOS and the source electrode of the 28 PMOS respectively;

The grid of the 25 PMOS connects the positive output end of trsanscondutance amplifier, the drain electrode of drain electrode connection the 30 NMOS tube and the drain electrode of the 28 PMOS;

The grid of the 26 PMOS is connected reference voltage end with the grid of the 27 PMOS, and drain electrode connects the drain electrode of the 27 PMOS and the drain electrode of the 29 NMOS tube respectively;

The grid of the 28 PMOS connects the negative output of trsanscondutance amplifier;

The grid of the 29 NMOS tube is connected common mode feedback voltage end with drain electrode; The source ground of the 29 NMOS tube;

The grid of the 30 NMOS tube is connected with drain electrode, source ground.

3. a resistance, is characterized in that, comprises trsanscondutance amplifier according to claim 1, wherein,

The negative output of trsanscondutance amplifier is connected with the common mode feedback voltage end of trsanscondutance amplifier;

The positive output end of trsanscondutance amplifier is connected with the negative-phase input of trsanscondutance amplifier, and the tie point of this connection is as the first end of resistance;

The normal phase input end of trsanscondutance amplifier is as the second end of resistance.

4. a resistance, is characterized in that, comprises trsanscondutance amplifier according to claim 2, wherein,

The normal phase input end of trsanscondutance amplifier is connected with the negative output of trsanscondutance amplifier, and the tie point of this connection is as the first end of described resistance;

The negative-phase input of trsanscondutance amplifier is connected with the positive output end of trsanscondutance amplifier, and the tie point of this connection is as the second end of described resistance.

5. an inductance, is characterized in that, comprises two trsanscondutance amplifiers according to claim 1, is respectively the first trsanscondutance amplifier and the second trsanscondutance amplifier, wherein,

The negative output of the first trsanscondutance amplifier is connected with the common mode feedback voltage end of the first trsanscondutance amplifier; The negative output of the second trsanscondutance amplifier is connected with the common mode feedback voltage end of the second trsanscondutance amplifier;

The first end of inductance by the first capacity earth, and is connected with the positive output end of the first trsanscondutance amplifier, the normal phase input end of the second trsanscondutance amplifier respectively; Second end of inductance is connected with the normal phase input end of the first trsanscondutance amplifier, the positive output end of the second trsanscondutance amplifier respectively;

The negative-phase input ground connection of the first trsanscondutance amplifier, the negative-phase input ground connection of the second trsanscondutance amplifier.

6. a filter, is characterized in that, comprises the trsanscondutance amplifier described in any one of claim 1 to 2, and/or, the resistance described in any one of claim 3 to 4, and/or, inductance according to claim 5.

7. filter as claimed in claim 6, is characterized in that, also comprise phase-locked loop tuner, wherein,

The output of voltage controlled oscillator connects the first input end of phase frequency detector, and the second input of phase frequency detector receives reference frequency signal; The output of phase frequency detector is by the input of charge pump linkloop filter, and the output of loop filter connects the tuning voltage input in the input of voltage controlled oscillator and filter respectively.