CN104201992B - Dual-loop compensation orthogonal signal source phase noise restraining circuit based on lock-in amplifier - Google Patents
Dual-loop compensation orthogonal signal source phase noise restraining circuit based on lock-in amplifier Download PDFInfo
- Publication number
- CN104201992B CN104201992B CN201410442837.1A CN201410442837A CN104201992B CN 104201992 B CN104201992 B CN 104201992B CN 201410442837 A CN201410442837 A CN 201410442837A CN 104201992 B CN104201992 B CN 104201992B
- Authority
- CN
- China
- Prior art keywords
- phase
- input
- output
- signal source
- pass filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a dual-loop compensation orthogonal signal source phase noise restraining circuit based on a lock-in amplifier. An output orthogonal component of a quarter frequency divider is connected with the input side of a phase sensitive detector, and the output side of the phase sensitive detector is connected with the input negative terminal of an integrator. The output side of a half Vos measuring circuit is connected with the input positive terminal of the integrator. The output side of the integrator is connected with the input side of a #1 low pass filter. The output side of the low pass filter is connected the negative terminal of a comparator, and the output side of the comparator is connected with the input side of a phase frequency detector. The cophase component output side of the quarter frequency divider is connected with the input side of the phase frequency detector, the output side of the phase frequency detector is connected with the input side of a #2 low pass filter, the output side of the #2 low pass filter is connected with the input side of a voltage-controlled oscillator, and the output side of the voltage-controlled oscillator is connected with the input side of the quarter frequency divider. A signal source is connected with the input side of the phase sensitive detector, the input side of the half Vos measuring circuit and the input side of the comparator. The dual-loop compensation orthogonal signal source phase noise restraining circuit compensates for the phase offset caused by phase noise, and can effectively restrain the phase noise and ensure the eddy measuring accuracy.
Description
Technical field
The present invention relates to experimental apparatus Automatic control and measure field is and in particular to a kind of bicyclic based on lock-in amplifier
Compensate suppression orthogonal signalling source phase noise circuit.
Background technology
In eddy current detection field, easily flooded by noise because detection signal is faint, orthogonal lock-in amplifier need to be adopted
The amplitude of detection signal and phase place.System needs the exciting signal source of configuring high-frequency rate degree of stability；Also need to same with signal source simultaneously
The orthogonal signalling of frequency are as reference signal.Signal source is made up of semiconductor device and electronic component, can be subject to electronic device temperature drift,
Aging and circuit noise impact produces phase noise, causes signal source phase jitter, thus causing signal source and orthogonal reference
Phase offset between signal, the certainty of measurement of impact eddy detection system.
The method that signal source produces orthogonal signalling adopts digital phase-locked loop (PLL), and PLL is phase feedback control system,
Under loop-locking state, loop phase difference very little and be in the linear zone of phase characteristic all the time, there is narrow-band filtering characteristic, and right
Noise has certain rejection ability.This monocyclic circuit solve only tracking and partial noise suppression.In the accurate survey of EDDY CURRENT
In amount system, the phase noise of orthogonal reference signal need to be suppressed further, its certainty of measurement of such guarantee.
Content of the invention
In order to solve the above problems, it is an object of the invention to provide a kind of just suppressed based on the bicyclic compensation of lock-in amplifier
Hand over signal source phase noise circuit, this circuit incorporates modern control technology and Technique of Weak Signal Detection, application Phase Demodulation completes
The measurement of signal source phase noise；Application linear control theory is realized loop negative feedback control and signal source phase noise is caused
Phase pushing figure be compensated for, be a kind of suppression of the bicyclic compensation based on lock-in amplifier orthogonal signalling source phase noise electricity
Road.
The purpose of the present invention is achieved through the following technical solutions：
A kind of bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier, is characterized in that：This circuit bag
Include comparator, #1 low pass filter, integrator, 1/2VosMeasuring circuit, phase sensitive detection, phase frequency detector, #2 low pass filter,
Voltage controlled oscillator, 1/4 frequency divider, 1/4 frequency divider output orthogonal component is connected with phase sensitive detection input, and phase sensitive detection exports and amasss
Device input negative terminal is divided to be connected；1/2VosMeasuring circuit output is connected with integrator input positive terminal；Integrator output and #1 low-pass filtering
Device input is connected；Low pass filter output is connected with comparator negative terminal, and comparator output is connected with phase frequency detector input；1/4
The output of frequency divider in-phase component is connected with phase frequency detector input, and the output of phase frequency detector phase demodulation and #2 low pass filter input phase
Even, the output of #2 low pass filter is connected with voltage controlled oscillator input, and voltage controlled oscillator output is connected with 1/4 frequency divider input；Letter
Number source and phase sensitive detection, 1/2VosMeasuring circuit is connected with the input of comparator.
In the present invention, phase sensitive detection includes analog switch and logic control signal.If us(t)=Usmsin(ωt+Δθ)+
VOS, wherein Δ θ is phase pushing figure and its value very little, and phase sensitive detection carries out quadrature component measurement to signal source, and measurement phase place is inclined
Shifting amount level and signal source direct current offset VosLevel, its value is ua(t)=(UsmVr/π)·sinΔθ+1/2·Vos=k1+1/
2Vos, k in formula1=(UsmVr/π)·sinΔθ≈(UsmVr/π)·Δθ.
1/2VosMeasuring circuit includes：Resistance R1、R2、R3、C1With electric capacity C2；Resistance R1With R2Resistance is equal, realizes 1/2Vos
Sampling；R3、C1And C2Composition low-pass filter circuit, obtains 1/2VosValue.Integrator includes：Operational amplifier, R4And C3；1/2Vos
Measuring circuit output is connected with integrator anode, phase sensitive detection output is connected with integrator negative terminal, using integrator input difference
Circuit for eliminating signal source 1/2Vos, R4And C3Construct time constant of integrator τ1=R4C3.#1 low pass filter it include R5With
C4；R5And C4Construct #1 low pass filter, its timeconstantτ2=R5C4.Comparator includes：Signal source output is defeated with comparator
Enter anode be connected, #1 low pass filter output level be connected with comparator input negative terminal, adjust export square-wave signal rising edge phase
Position and as PLL reference signal, its adjustment sensitivity be k2, it is directly proportional to signal source amplitude.#2 low pass filter includes：R7、R8
And C7；R7、R8And C7Construct the RC proportional-integral filter of #2 low pass filter, its transmission function is (1+s τ4)/(1+sτ3),
τ in formula3=(R7+R8)C7, τ4=R8C7.
1/4 frequency divider includes：Trigger, is produced the clock signal of 90 ° of phase shifts, just obtains using 1/4 frequency dividing logic circuit
Hand over reference signal.Phase noise measurement is θ with compensating ring transmission functioni(s)/θs(s)=s (s+1/ τ2)/(s2+s/τ2+k1k2/τ1
τ2), constitute " 1 type " second order control, adjust loop parameter τ1、τ2、k1And k2, realize the existing phase bit of control system
Nargin has extremely narrow bandwidth again, can effectively suppression loop noise it is ensured that orthogonal reference signal phase noise is sufficiently small.
In the present invention, on the basis of digital phase-locked loop (PLL), between signal source and PLL insertion phase noise measurement with
Compensate ring.Lock-in amplifier is loop core, is made up of with low pass filter phase sensitive detection, and measurement signal source phase noise causes
Phase pushing figure level and signal source direct current offset VosLevel；Integrator realizes the compensation of signal source DC offset and phase place is inclined
Shifting amount level amplifies and filtering；Comparator circuit compensates to signal source phase pushing figure.The control of invention circuit is bicyclic all to adopt
With feedback controling mode, constitute " 1 type " second order control, the existing certain phase margin of control system has extremely narrow bandwidth again,
Effectively phase noise can be suppressed it is ensured that eddy current measurement precision.
Specifically include：Comparator unit, input signal source us(t) and phase pushing figure level ufT () is compared
To square-wave pulse ui(t), ufT () can be adjusted to square wave rising edge phase place；Phase frequency detector unit, uiT () joins as PLL
Examine signal and in-phase component urT 0 ° of () is entered line phase in phase frequency detector and is relatively obtained phase discrimination signal ud(t)；#2 low-pass filtering
Device unit, udT () obtains DC level u after low-pass filteringc(t)；Voltage control oscillator unit, ucT () adjusts voltage controlled oscillator
Oscillation output signal frequency and phase place；1/4 divider unit, carries out 4 frequency dividings to voltage controlled oscillator output frequency signal, utilizes 1/
4 frequency dividing logic circuits produce the clock signal of 90 ° of phase shifts, i.e. orthogonal reference signal ur(t)；Phase sensitive detection unit, with reference to orthogonal
Component urT () 90 ° of injection phase-sensitive detection circuit inputs are used for measurement signal source quadrature component ua(t), i.e. phase pushing figure and direct current
Skew 1/2VosSum；1/2VosMeasuring unit, records us(t) direct current offset 1/2Vos；Integrator unit, using structure integrator
Operational amplifier input difference circuit offset 1/2Vos, and amplify phase pushing figure；#1 low pass filter unit, phase offset
Amount signal obtains DC level u after low-pass filteringfT (), for adjusting PLL reference signal phase place.
Present invention application modern control technology and Technique of Weak Signal Detection, with lock-in amplifier as core, measurement signal
Source phase noise, and the phase pushing figure that phase noise causes is compensated for.Bicyclic all adopt feedback controling mode, can be effective
Suppression phase noise is it is ensured that eddy current measurement precision.For realizing foregoing circuit, 1/4 frequency divider output orthogonal component input phase sensitivity
Detection, phase sensitive detection measurement signal source phase noise, by 1/2VosMeasuring circuit measurement signal source direct current offset, integrator disappears
Except signal source direct current offset, and phase pushing figure level is amplified and filters, then after the filtering of filtered device, output is added to ratio
Compared with device, for adjusting output square-wave signal rising edge phase place so as to phase noise is sufficiently small.Comparator exports reference signal and 1/
4 frequency divider in-phase components are input to PLL phase frequency detector, and after phase demodulation output low-pass filtered device filtering, DC level input is voltage-controlled
Agitator adjusts the phase and frequency of signal, and output signal inputs 1/4 frequency divider and obtains orthogonal reference signal.
By the present invention, phase pushing figure is caused to be measured in real time signal source phase noise, phase pushing figure level
It is added to comparator input terminal to output impulse phase adjustment, compensate ring after closed loop control it is ensured that PLL input reference signal
Phase noise is sufficiently small.By PLL follow the tracks of ring, can meet for eddy current signal measurement orthogonal reference signal have sufficiently small
Phase noise.Apply this invention, be greatly improved the precision of eddy current measurement.
Brief description
Fig. 1 is circuit structure block diagram of the present invention；
Fig. 2 is phase noise measurement and compensation loop circuit figure；
Fig. 3 is digital phase-locked loop PLL circuit figure；
Fig. 4 is present system block diagram.
Specific embodiment
Referring to the drawings inventive embodiments are illustrated.
A kind of bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier, Fig. 1 is circuit knot of the present invention
Structure block diagram, including：Comparator 1, #1 low pass filter 2, integrator 3,1/2VosMeasuring circuit 4, phase sensitive detection 5, phase frequency detector
6th, #2 low pass filter 7, voltage controlled oscillator 8,1/4 frequency divider 9.Wherein, comparator 1, #1 low pass filter 2, integrator 3,1/
2VosMeasuring circuit 4, phase sensitive detection 5 constitute phase noise measurement and compensate ring；Phase frequency detector 6, #2 low pass filter 7, voltage-controlled
Agitator 8,1/4 frequency divider 9 constitute digital phase-locked loop.
When being embodied as, constitute phase noise measurement with compensate ring such as Fig. 2,1/4 frequency divider 9 output orthogonal component input and
Phase sensitive detection 5 input is connected, and signal source is connected with phase sensitive detection 5 input, and phase sensitive detection 5 output comprises the 1/2V of signal sourceosElectricity
Gentle phase pushing figure level, is connected with integrator 3 input negative terminal, signal source and 1/2VosMeasuring circuit 4 input is connected, and 1/
2VosMeasuring circuit 4 exports 1/2VosLevel is connected with integrator 3 input positive terminal, using integrator 3 input difference circuit for eliminating letter
Number source 1/2Vos, integrator 3 phase pushing figure level is amplified and filter output with #1 low pass filter 2 input be connected, than
It is connected with signal source compared with the input of device 1 anode, #1 low pass filter 2 output phase pushing figure level inputs phase with comparator 1 negative terminal
Even, phase pushing figure level is added to comparator 1 input negative terminal to adjust output square-wave signal rising edge phase place so as to phase offset
Amount is sufficiently small, and comparator 1 is exported and is connected with phase frequency detector 6 input.
Constitute digital phase-locked loop PLL such as Fig. 3, comparator 1 output reference signal is connected with phase frequency detector 6 input, 1/4 point
The output of frequency device 9 in-phase component is connected with phase frequency detector 6 input, and the output of phase frequency detector 6 phase demodulation is inputted with #2 low pass filter 7
It is connected, DC level output after #2 low pass filter 7 filtering is connected with voltage controlled oscillator 8 input, adjusts voltage controlled oscillator 8 phase place
And frequency, the input of voltage controlled oscillator 8 output frequency signal and 1/4 frequency divider 9 is connected, 1/4 frequency divider 9 output orthogonal signal, together
Phase component is connected with phase frequency detector 6 input, and quadrature component is connected with phase sensitive detection 5 input.
As shown in Fig. 2 phase sensitive detection 5 it include：Analog switch (74HC4053) and logic control signal.If us(t)=
Usmsin(ωt+Δθ)+VOS, wherein Δ θ is phase pushing figure and its value very little, and phase sensitive detection 5 carries out orthogonal point to signal source
Measurement, measurement phase pushing figure level and signal source direct current offset VosLevel, its value is ua(t)=(UsmVr/π)·sinΔθ
+1/2·Vos=k1+1/2Vos, k in formula1=(UsmVr/π)·sinΔθ≈(UsmVr/π)·Δθ.
1/2VosMeasuring circuit 4 it include：Resistance R1、R2、R3, electric capacity C1And C2.Resistance R1With R2Resistance is equal, realizes 1/
2VosSampling；R3、C1And C2Composition low-pass filter circuit, obtains 1/2VosValue.
Integrator 3 it include：Operational amplifier (OP400), R4And C3.1/2VosMeasuring circuit 4 output is with integrator 3 just
End is connected, phase sensitive detection 5 is exported and is connected with integrator 3 negative terminal, using integrator 3 input difference circuit for eliminating signal source 1/2Vos,
R4And C3Construct integrator 3 timeconstantτ1=R4C3.
#1 low pass filter 2 it include R5And C4.R5And C4Construct #1 low pass filter 2, its timeconstantτ2=R5C4.
Comparator 1 it include：Comparator (LT1011) and R6.Signal source output is connected with comparator 1 input positive terminal, #1 is low
Bandpass filter 2 output level is connected with comparator 1 input negative terminal, adjusts output square-wave signal rising edge phase place and as PLL ginseng
Examine signal, its adjustment sensitivity is k2, it is directly proportional to signal source amplitude.
As shown in figure 3, phase frequency detector 6 it include：Integrated circuit (74HC4053) and related elements composition.
#2 low pass filter 7 it include：Resistance R7、R8With electric capacity C7.R7、R8And C7Construct the RC of #2 low pass filter 7
Proportional-integral filter, its transmission function is (1+s τ4)/(1+sτ3), τ in formula3=(R7+R8)C7, τ4=R8C7.
Voltage controlled oscillator 8 it include：Integrated circuit (74HC4053) and related elements composition.
1/4 frequency divider 9 it include：Trigger (74HC109) and related elements composition.Produced using 1/4 frequency dividing logic circuit
The clock signal of raw 90 ° of phase shifts, obtains orthogonal reference signal.
On the basis of foregoing circuit structured flowchart, thus obtain a kind of bicyclic compensation suppression letter based on lock-in amplifier
System block diagram such as Fig. 4 of number source phase noise circuit.Phase noise measurement with compensate ring transmission function beConstitute " 1 type " second order control, adjust loop parameter τ1、τ2、k1And k2, can achieve
The existing certain phase margin of control system has extremely narrow bandwidth again, can effectively suppression loop noise it is ensured that orthogonal reference signal phase
Position noise is sufficiently small.
Claims (8)
1. a kind of bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier, is characterized in that：This circuit includes
Comparator (1), #1 low pass filter (2), integrator (3), 1/2VosMeasuring circuit (4), phase sensitive detection (5), phase frequency detector
(6), #2 low pass filter (7), voltage controlled oscillator (8), 1/4 frequency divider (9), 1/4 frequency divider (9) output orthogonal component and phase sensitivity
Detection (5) input is connected, and phase sensitive detection (5) output is connected with integrator (3) input negative terminal；1/2VosMeasuring circuit (4) output with
Integrator (3) input positive terminal is connected；Integrator (3) output is connected with #1 low pass filter (2) input；#1 low pass filter (2)
Output is connected with comparator (1) negative terminal, and comparator (1) output is connected with phase frequency detector (6) input；1/4 frequency divider (9) homophase
Component output is connected with phase frequency detector (6) input, and the output of phase frequency detector (6) phase demodulation and #2 low pass filter (7) input phase
Even, #2 low pass filter (7) output is connected with voltage controlled oscillator (8) input, and voltage controlled oscillator (8) exports and 1/4 frequency divider (9)
Input is connected；Signal source and phase sensitive detection (5), 1/2VosMeasuring circuit (4) is connected with the input of comparator (1).
2. the bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier according to claims 1, its
Feature is：Phase sensitive detection (5) includes analog switch and logic control signal.
3. the bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier according to claims 1, its
Feature is：Integrator (3) includes：Operational amplifier, R4And C3；1/2VosMeasuring circuit output is connected with integrator anode, phase sensitivity
Detection output is connected with integrator negative terminal, using integrator input difference circuit for eliminating signal source 1/2Vos, R4And C3Construct long-pending
Divide device timeconstantτ1=R4C3.
4. the bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier according to claims 1, its
Feature is：#1 low pass filter it include R5And C4；R5And C4Construct #1 low pass filter, its timeconstantτ2=R5C4.
5. the bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier according to claims 1, its
Feature is：Comparator (1) includes：Signal source output be connected with comparator input positive terminal, #1 low pass filter output level with than
It is connected compared with device input negative terminal, adjusts output square-wave signal rising edge phase place and as PLL reference signal, its adjustment sensitivity is
k2, it is directly proportional to signal source amplitude.
6. the bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier according to claims 1, its
Feature is：#2 low pass filter includes：Resistance R7、R8With electric capacity C7；R7、R8And C7The RC ratio constructing #2 low pass filter is amassed
Filter-divider, its transmission function is (1+s τ4)/(1+sτ3), τ in formula3=(R7+R8)C7, τ4=R8C7.
7. the bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier according to claims 1, its
Feature is：1/4 frequency divider includes：Trigger, is produced the clock signal of 90 ° of phase shifts, obtains orthogonal using 1/4 frequency dividing logic circuit
Reference signal.
8. the bicyclic compensation suppression signal source phase noise circuit based on lock-in amplifier according to claims 1, its
Feature is：Phase noise measurement is θ with compensating ring transmission functioni(s)/θs(s)=s (s+1/ τ2)/(s2+s/τ2+k1k2/τ1τ2),
Constitute " 1 type " second order control, adjust loop parameter τ1、τ2、k1And k2, realize the existing phase bit of control system abundant
Degree again has extremely narrow bandwidth, can effectively suppression loop noise it is ensured that orthogonal reference signal phase noise is sufficiently small.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410442837.1A CN104201992B (en) | 2014-09-02 | 2014-09-02 | Dual-loop compensation orthogonal signal source phase noise restraining circuit based on lock-in amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410442837.1A CN104201992B (en) | 2014-09-02 | 2014-09-02 | Dual-loop compensation orthogonal signal source phase noise restraining circuit based on lock-in amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104201992A CN104201992A (en) | 2014-12-10 |
| CN104201992B true CN104201992B (en) | 2017-02-15 |
Family
ID=52087236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410442837.1A Active CN104201992B (en) | 2014-09-02 | 2014-09-02 | Dual-loop compensation orthogonal signal source phase noise restraining circuit based on lock-in amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104201992B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107436144B (en) * | 2016-05-26 | 2020-10-16 | 中科芯未来微电子科技成都有限公司 | Circuit for automatically eliminating quadrature error of gyroscope |
| TWI571641B (en) * | 2016-06-14 | 2017-02-21 | 國立交通大學 | Phase noise measurement circuit |
| CN108933596B (en) * | 2018-07-26 | 2024-01-30 | 四川知微传感技术有限公司 | Clock phase shift circuit based on analog phase-locked loop |
| CN109765423B (en) * | 2019-02-14 | 2024-04-02 | 南京工业职业技术学院 | Digital measuring method and measuring device for voltage of overhead line system with compensation |
| CN111130660B (en) * | 2019-12-16 | 2022-04-19 | 天津津航计算技术研究所 | Phase noise measuring probe circuit |
| CN110988510B (en) * | 2019-12-18 | 2022-08-30 | 北京无线电计量测试研究所 | Phase noise detection method and device based on radio over fiber |
| CN113765516B (en) * | 2021-09-10 | 2024-01-12 | 中国航空工业集团公司西安飞行自动控制研究所 | MEMS resonator closed-loop control method and control structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101652970A (en) * | 2007-04-11 | 2010-02-17 | 日本电气株式会社 | Orthogonal cross polarization interference compensating device, demodulator, receiving station, and method of compensating cross polarization interference |
| CN102045036A (en) * | 2011-01-27 | 2011-05-04 | 中山大学 | Digital phase lock amplifier |
| CN102739173A (en) * | 2012-06-21 | 2012-10-17 | 中国科学院微电子研究所 | Transconductance amplifier, resistor, inductor and filter |
-
2014
- 2014-09-02 CN CN201410442837.1A patent/CN104201992B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101652970A (en) * | 2007-04-11 | 2010-02-17 | 日本电气株式会社 | Orthogonal cross polarization interference compensating device, demodulator, receiving station, and method of compensating cross polarization interference |
| CN102045036A (en) * | 2011-01-27 | 2011-05-04 | 中山大学 | Digital phase lock amplifier |
| CN102739173A (en) * | 2012-06-21 | 2012-10-17 | 中国科学院微电子研究所 | Transconductance amplifier, resistor, inductor and filter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104201992A (en) | 2014-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104201992B (en) | Dual-loop compensation orthogonal signal source phase noise restraining circuit based on lock-in amplifier | |
| CN101873130B (en) | Pll with loop bandwidth calibration circuit | |
| US8953668B2 (en) | Method and circuit of clock and data recovery with built in jitter tolerance test | |
| US9112652B2 (en) | Locking detection circuit for CDR circuits | |
| CN107040257A (en) | Bandwidth of phase lock loop controls circuit and method | |
| EP2878081A1 (en) | System and method of determining an oscillator gain | |
| CN101498761B (en) | Test method for step response performance of phase-locked loop system | |
| CN103873049B (en) | Radiofrequency signal measuring device and its application method | |
| CN101567689B (en) | Phase-locked loop based on equivalent phase demodulation frequency | |
| CN105959001B (en) | Become frequency domain all-digital phase-locked loop and locking phase control method | |
| Hwang et al. | A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock | |
| Tyagi et al. | Frequency estimation based on moving-window DFT with fractional bin-index for capacitance measurement | |
| CN104467825B (en) | A method of based on Clean-up digital servo-control loop self-adaptive quick lock in crystal oscillator | |
| CN108616272A (en) | A kind of high-precision low jitter time frequency signal switching device | |
| EP2639590B1 (en) | Wide range, high resolution frequency monitor | |
| TWI432743B (en) | Apparatus and method for judging signal energy | |
| CN107741523B (en) | Time domain signal measuring device based on PLL | |
| CN107543960A (en) | A kind of high stability crystal oscillator measurement apparatus | |
| CN203747794U (en) | CDR locking and detecting circuit | |
| CN104410414B (en) | Signal control device and method based on the relaxation time | |
| CN102843114B (en) | The zero phase-shift RC low pass filter that bandwidth is adjustable | |
| CN116165434B (en) | Rapid measuring method and device for quartz crystal resonant frequency | |
| Shuang et al. | Research and implementation of clock recovery method based on software PLL | |
| CN101242183B (en) | A method, device and phase locked ring for getting oscillator control signal | |
| CN104883186A (en) | Phase-locked loop circuit used for frequency counter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190531 Address after: 210000 Xumu Road, Zhetang Town, Lishui District, Nanjing City, Jiangsu Province Patentee after: Jiangsu Smart-Tech Co., Ltd. Address before: 210016 No. 1 Yangshan North Road, Xianlin University City, Nanjing, Jiangsu Province Patentee before: Nanjing Institute of Industry Technology |
|
| TR01 | Transfer of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Phase noise suppression circuit of quadrature signal source with double loop compensation based on lock-in amplifier Effective date of registration: 20211221 Granted publication date: 20170215 Pledgee: Jiangsu bank Limited by Share Ltd. Lishui branch Pledgor: JIANGSU SMART-TECH Co.,Ltd. Registration number: Y2021980015713 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |