CN103514061B - 用于错误校正的装置和方法 - Google Patents

用于错误校正的装置和方法 Download PDF

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Publication number
CN103514061B
CN103514061B CN201210420962.3A CN201210420962A CN103514061B CN 103514061 B CN103514061 B CN 103514061B CN 201210420962 A CN201210420962 A CN 201210420962A CN 103514061 B CN103514061 B CN 103514061B
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Prior art keywords
filter coefficients
detector
noise
count value
decoder
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Chinese (zh)
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CN103514061A (zh
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韩洋
杨少华
张帆
李宗旺
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Avago Technologies International Sales Pte Ltd
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Avago Technologies Fiber IP Singapore Pte Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6331—Error control coding in combination with equalisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1142—Decoding using trapping sets
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3723—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using means or methods for the initialisation of the decoder

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
CN201210420962.3A 2012-06-26 2012-10-29 用于错误校正的装置和方法 Active CN103514061B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/533,207 2012-06-26
US13/533,207 US8781033B2 (en) 2012-06-26 2012-06-26 Apparatus and method for breaking trapping sets

Publications (2)

Publication Number Publication Date
CN103514061A CN103514061A (zh) 2014-01-15
CN103514061B true CN103514061B (zh) 2016-01-27

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US (1) US8781033B2 (enExample)
EP (1) EP2706694A3 (enExample)
JP (1) JP5670411B2 (enExample)
KR (1) KR101482824B1 (enExample)
CN (1) CN103514061B (enExample)
TW (1) TWI484762B (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8869010B1 (en) * 2011-03-09 2014-10-21 Marvell International Ltd. Controlling decoder iterations based on measurements of physical variables
US9098105B2 (en) * 2012-08-24 2015-08-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Dynamic Y-buffer size adjustment for retained sector reprocessing
US9116822B2 (en) * 2012-12-07 2015-08-25 Micron Technology, Inc. Stopping criteria for layered iterative error correction
US9362954B1 (en) * 2013-03-15 2016-06-07 Seagate Technology Llc Digital communications channel
US9202519B2 (en) 2014-03-28 2015-12-01 Avago Technologies General Ip (Singapore) Pte. Ltd. Adaptive calibration of noise predictive finite impulse response filter based on decoder convergence
KR20180009558A (ko) 2016-07-19 2018-01-29 삼성전자주식회사 저밀도-패리티 체크 코드를 이용하는 디코더 및 이를 포함하는 메모리 컨트롤러
KR102582326B1 (ko) * 2018-09-20 2023-09-26 에스케이하이닉스 주식회사 에러 정정 회로 및 이의 동작 방법
KR102592870B1 (ko) * 2018-10-12 2023-10-24 에스케이하이닉스 주식회사 에러 정정 회로 및 이의 동작 방법
KR102606829B1 (ko) 2019-01-09 2023-11-27 에스케이하이닉스 주식회사 Ldpc 디코더, 반도체 메모리 시스템 및 그것의 동작 방법
US12175363B2 (en) 2020-07-27 2024-12-24 Microchip Technology Inc. Regression neural network for identifying threshold voltages to be used in reads of flash memory devices
US12393846B2 (en) 2020-08-20 2025-08-19 Microchip Technology Inc. Partitionable neural network for solid state drives
US12493778B2 (en) 2020-12-15 2025-12-09 Microchip Technology Inc. Method and apparatus for performing a neural network operation
US12014068B2 (en) 2021-04-27 2024-06-18 Microchip Technology Inc. System and method for double data rate (DDR) chip-kill recovery
US11934696B2 (en) 2021-05-18 2024-03-19 Microchip Technology Inc. Machine learning assisted quality of service (QoS) for solid state drives
CN117480732B (zh) * 2021-09-28 2025-05-02 微芯片技术股份有限公司 具有陷阱块管理的ldpc解码
US12273194B2 (en) * 2021-10-20 2025-04-08 Telefonaktiebolaget Lm Ericsson (Publ) Iterative guessing random additive noise decoding (GRAND) in the presence of bursty channels
US11953987B1 (en) * 2022-09-16 2024-04-09 Western Digital Technologies, Inc. Trained states equalizer in a read channel

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101416394A (zh) * 2006-03-31 2009-04-22 Nxp股份有限公司 用于a/d转换器的校准电路和方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11026A (en) * 1854-06-06 Sofa-bedstead
US5757821A (en) * 1996-07-22 1998-05-26 Telefonaktiebolaget Lm Ericsson Method and apparatus for detecting communication signals having unequal error protection
US7088793B1 (en) * 2002-04-17 2006-08-08 Rockwell Collins, Inc. Equalizer for complex modulations in very noisy environments
US7522678B2 (en) * 2002-04-18 2009-04-21 Infineon Technologies Ag Method and apparatus for a data-dependent noise predictive viterbi
KR20050026320A (ko) * 2003-09-09 2005-03-15 삼성전자주식회사 데이터 재생 장치 및 방법
KR101418467B1 (ko) * 2008-08-15 2014-07-10 엘에스아이 코포레이션 니어 코드워드들의 ｒａｍ 리스트-디코딩
JP5506828B2 (ja) 2009-03-05 2014-05-28 エルエスアイ コーポレーション 繰り返し復号器のための改良ターボ等化方法
US8407550B2 (en) * 2009-08-14 2013-03-26 Mitsubishi Electric Research Laboratories, Inc. Method and system for decoding graph-based codes using message-passing with difference-map dynamics
US8312359B2 (en) * 2009-09-18 2012-11-13 Lsi Corporation Branch-metric calibration using varying bandwidth values
US8578253B2 (en) * 2010-01-04 2013-11-05 Lsi Corporation Systems and methods for updating detector parameters in a data processing circuit
US8898537B2 (en) * 2010-03-17 2014-11-25 The Royal Institution For The Advancement Of Learning/Mcgill University Method and system for decoding
KR101152482B1 (ko) 2010-11-08 2012-06-01 성균관대학교산학협력단 고속 부호율-적응 저밀도 패리티 코드를 이용한 복호화 방법 및 이러한 방법을 사용하는 부/복호화 장치
US8806309B2 (en) * 2011-06-13 2014-08-12 Silicon Motion Inc. Method for controlling message-passing algorithm based decoding operation by referring to statistics data of syndromes of executed iterations and related control apparatus thereof
US8880986B2 (en) * 2012-05-30 2014-11-04 Lsi Corporation Systems and methods for improved data detection processing

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101416394A (zh) * 2006-03-31 2009-04-22 Nxp股份有限公司 用于a/d转换器的校准电路和方法

Also Published As

Publication number Publication date
JP2014007724A (ja) 2014-01-16
TW201401789A (zh) 2014-01-01
EP2706694A2 (en) 2014-03-12
TWI484762B (zh) 2015-05-11
CN103514061A (zh) 2014-01-15
KR101482824B1 (ko) 2015-01-14
KR20140001069A (ko) 2014-01-06
US8781033B2 (en) 2014-07-15
JP5670411B2 (ja) 2015-02-18
EP2706694A3 (en) 2014-08-06
US20130343495A1 (en) 2013-12-26

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