CN103490768A - Phase difference value switching circuit - Google Patents
Phase difference value switching circuit Download PDFInfo
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- CN103490768A CN103490768A CN201310381544.2A CN201310381544A CN103490768A CN 103490768 A CN103490768 A CN 103490768A CN 201310381544 A CN201310381544 A CN 201310381544A CN 103490768 A CN103490768 A CN 103490768A
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Abstract
The invention discloses a phase difference value switching circuit which is provided with NMOS tubes (MD1 and MD2). Source electrodes and grid electrodes of the NMOS tubes (MD1 and MD2) are respectively connected with a direct-current bias VAA. A drain electrode of the NMOS tube MD1 is connected with source electrodes of a first MOS tube and a second MOS tube. Grid electrodes of the first MOS tube and the second MOS tube are connected with input signals (CK1P and CK2P) respectively. The drain electrode of the NMOS tube MD2 is connected with source electrodes of a third MOS tube and a fourth MOS tube. Grid electrodes of the third MOS tube and the fourth MOS tube are connected with input signals (CK2N and CK1N) respectively. Drain electrodes of the first MOS tube and the fourth MOS tube are connected with control words IW1. Drain electrodes of the second MOS tube and the third MOS tube are connected with control words IW2. A resistor is arranged between the grid electrode of the NMOS tube MD1 and the direct-current bias, and a resistor is arranged between the grid electrode of the NMOS tube MD2 and the direct-current bias. According to the phase difference value switching circuit, the output amplitude of oscillation is limited, the output is rapidly returned to the direct-current bias, the phase difference value switching circuit is suitable for a high-speed circuit, and meanwhile the certain linearity is ensured.
Description
Technical field
The present invention relates to a kind of difference circuit, relate in particular to a kind of phase difference value change-over circuit.
Background technology
The phase difference value circuit, refer to a kind of circuit, according to two out of phase signals of input, produces the circuit of a phase place in the middle of two input signal phase places.
A kind of existing differential phase difference circuit shown in accompanying drawing 2, the weight of described control word IW1 and IW2 difference control inputs signal CK1 and CK2, and can adjust the signal of output and the difference between this two signals according to control word.As very large as IW1, when IW2 is very little, output just and CK1 very similar, as very large as IW2, when IW1 is very little, output just and CK2 very similar, if IW1=IW2 exports the median that is about CK1 and CK2.Be output as the NMOS pipe (MD1, MD2) of a diode connection shown in Fig. 2, concerning small-signal analysis, the NMOS pipe of diode connection can be approximately a resistance; Concerning large-signal, NMOS pipe (MD1, MD2) is set up the biasing of a direct current, and output signal range will be near this DC offset voltage; The amplitude of oscillation of output is little, gets back to direct current biasing fast, is applicable to high speed circuit.But, during due to large-signal, the NMOS pipe of diode connection non-linear, cause the linearity variation of the phase place of output.Be not suitable for using in high-precision difference circuit.
Another kind of existing phase difference value circuit shown in accompanying drawing 2, circuit adopts resistance to be responsible for as output, no matter be large-signal or small-signal, exports all more linearly, and the amplitude of oscillation of output is large.But, in order to produce suitable direct current biasing output voltage, the resistance of resistance and bias current product are restricted, therefore the bandwidth of output is restricted, and is not suitable for high speed circuit.
Summary of the invention
Technical problem to be solved by this invention is that a kind of phase difference value change-over circuit that can be applicable to high speed circuit is provided.
In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions: a kind of phase difference value change-over circuit, there is NMOS pipe MD1, MD2, described NMOS pipe MD1, the source electrode of MD2 all is connected direct current biasing VAA with grid, the drain electrode of described NMOS pipe MD1 connects the source electrode of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor is connected respectively input signal CK1P, CK2P, the drain electrode of described NMOS pipe MD2 connects the source electrode of the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, the grid of the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is connected respectively input signal CK2N, CK1N, the drain electrode of described the first metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is connected control word IW1, the drain electrode of the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor is connected control word IW2, described NMOS pipe MD1, respectively be provided with a resistance between the grid of MD2 and direct current biasing.
Compared with prior art, usefulness of the present invention is: the amplitude of oscillation of this phase difference value circuit limitations output, and make output get back to fast direct current biasing, be applicable to high speed circuit, guaranteed certain linearity simultaneously.
the accompanying drawing explanation:
Below in conjunction with accompanying drawing, the present invention is further described.
Fig. 1, Fig. 2 are existing phase difference value electrical block diagrams;
Fig. 3 is a kind of phase difference value converting circuit structure of the present invention schematic diagram.
In figure: 1, resistance; 2, the first metal-oxide-semiconductor; 3, the second metal-oxide-semiconductor; 4, the 3rd metal-oxide-semiconductor; 5, the 4th metal-oxide-semiconductor.
embodiment:
Below in conjunction with the drawings and the specific embodiments, describe the present invention:
A kind of phase difference value circuit shown in Fig. 3, there is NMOS pipe MD1, MD2, described NMOS pipe MD1, the source electrode of MD2 all is connected direct current biasing VAA with grid, the drain electrode of described NMOS pipe MD1 connects the source electrode of the first metal-oxide-semiconductor 2 and the second metal-oxide-semiconductor 3, the grid of the first metal-oxide-semiconductor 2 and the second metal-oxide-semiconductor 3 is connected respectively input signal CK1P, CK2P, the drain electrode of described NMOS pipe MD2 connects the source electrode of the 3rd metal-oxide-semiconductor 4 and the 4th metal-oxide-semiconductor 5, the grid of the 3rd metal-oxide-semiconductor 4 and the 4th metal-oxide-semiconductor 5 is connected respectively input signal CK2N, CK1N, the drain electrode of described the first metal-oxide-semiconductor 2 and the 4th metal-oxide-semiconductor 5 is connected control word IW1, the drain electrode of the second metal-oxide-semiconductor 3 and the 3rd metal-oxide-semiconductor 4 is connected control word IW2, described NMOS pipe MD1, respectively be provided with a resistance 1 between the grid of MD2 and direct current biasing VAA.
Concrete, in low frequency, the grid of managing MD1, MD2 due to NMOS does not have direct current, and the characteristic of the NMOS pipe of this connection and the NMOS pipe of diode connection is the same.In high frequency, buffer action and the grid of NMOS pipe MD1, MD2 and the electric capacity between source electrode due to resistance 1, cause the grid of NMOS pipe MD1, MD2 will follow source electrode, keep certain voltage, thereby guarantee that certain electric current flows through this pipe, charges to output, thereby the amplitude of oscillation of restriction output, make output get back to fast direct current biasing, be applicable to high speed circuit, guaranteed certain linearity simultaneously.
It is emphasized that: above is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, any simple modification, equivalent variations and modification that every foundation technical spirit of the present invention is done above embodiment, all still belong in the scope of technical solution of the present invention.
Claims (1)
1. a phase difference value change-over circuit, there is NMOS pipe (MD1, MD2), described NMOS pipe (MD1, MD2) source electrode all is connected direct current biasing (VAA) with grid, the drain electrode of described NMOS pipe (MD1) connects the source electrode of the first metal-oxide-semiconductor (2) and the second metal-oxide-semiconductor (3), the first metal-oxide-semiconductor (2) is connected respectively input signal (CK1P with the grid of the second metal-oxide-semiconductor (3), CK2P), the drain electrode of described NMOS pipe (MD2) connects the source electrode of the 3rd metal-oxide-semiconductor (4) and the 4th metal-oxide-semiconductor (5), the 3rd metal-oxide-semiconductor (4) is connected respectively input signal (CK2N with the grid of the 4th metal-oxide-semiconductor (5), CK1N), the drain electrode of described the first metal-oxide-semiconductor (2) and the 4th metal-oxide-semiconductor (5) is connected control word (IW1), the drain electrode of the second metal-oxide-semiconductor (3) and the 3rd metal-oxide-semiconductor (4) is connected control word (IW2), it is characterized in that: described NMOS pipe (MD1, MD2) respectively be provided with a resistance (1) between grid and direct current biasing (VAA).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310381544.2A CN103490768A (en) | 2013-08-29 | 2013-08-29 | Phase difference value switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310381544.2A CN103490768A (en) | 2013-08-29 | 2013-08-29 | Phase difference value switching circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103490768A true CN103490768A (en) | 2014-01-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310381544.2A Pending CN103490768A (en) | 2013-08-29 | 2013-08-29 | Phase difference value switching circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030179027A1 (en) * | 2002-03-22 | 2003-09-25 | Kizer Jade M. | Locked loop with dual rail regulation |
| CN1761184A (en) * | 2004-10-12 | 2006-04-19 | 美国博通公司 | High speed clock and data recovery system |
| CN203504527U (en) * | 2013-08-29 | 2014-03-26 | 苏州苏尔达信息科技有限公司 | Phase difference switching circuit |
-
2013
- 2013-08-29 CN CN201310381544.2A patent/CN103490768A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030179027A1 (en) * | 2002-03-22 | 2003-09-25 | Kizer Jade M. | Locked loop with dual rail regulation |
| CN1761184A (en) * | 2004-10-12 | 2006-04-19 | 美国博通公司 | High speed clock and data recovery system |
| CN203504527U (en) * | 2013-08-29 | 2014-03-26 | 苏州苏尔达信息科技有限公司 | Phase difference switching circuit |
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Application publication date: 20140101 |