CN203504527U

CN203504527U - Phase difference switching circuit

Info

Publication number: CN203504527U
Application number: CN201320529317.5U
Authority: CN
Inventors: 刘雄
Original assignee: SUZHOU SUERDA INFORMATION TECHNOLOGY Co Ltd
Current assignee: SUZHOU SUERDA INFORMATION TECHNOLOGY Co Ltd
Priority date: 2013-08-29
Filing date: 2013-08-29
Publication date: 2014-03-26
Anticipated expiration: 2023-08-29

Abstract

The utility model relates to a phase difference switching circuit which is provided with NMOS transistors (MD1 and MD2). Source electrodes and grid electrodes of the NMOS transistors (MD1 and MD2) are both connected with a direct current bias VAA, a drain electrode of the NMOS transistor MD1 is connected with source electrodes of a first MOS transistor and a second MOS transistor, grid electrodes of the first MOS transistor and the second MOS transistor are respectively connected with input signals (CK1P and CK2P), a drain electrode of the NMOS transistor MD2 is connected with source electrodes of a third MOS transistor and a fourth MOS transistor, grid electrodes of the third MOS transistor and the fourth MOS transistor are respectively connected with input signals (CK2N and CK1N), drain electrodes of the first MOS transistor and the fourth MOS transistor are connected with a control word IW1, drain electrodes of the second MOS transistor and the third MOS transistor are connected with a control word IW2, and a resistor is arranged between the grid electrode of the NMOS transistor MD1 and the direct current bias and between the grid electrode of the NMOS transistor MD2 and the direct current bias. According to the phase difference switching circuit, the outputted swinging amplitude is limited, the output is rapidly returned to the direct current bias, the phase difference switching circuit is applicable to a high-speed circuit, and certain linearity is guaranteed.

Description

Phase difference value change-over circuit

Technical field

The utility model relates to a kind of difference circuit, relates in particular to a kind of phase difference value change-over circuit.

Background technology

Phase difference value circuit, refers to a kind of circuit, according to two out of phase signals of input, produces the circuit of a phase place in the middle of two input signal phase places.

A kind of existing differential phase difference circuit shown in accompanying drawing 2, the weight of described control word IW1 and IW2 difference control inputs signal CK1 and CK2, and can adjust the signal of output and the difference between this two signals according to control word.As very large in IW1, when IW2 is very little, output just and CK1 very similar, as very large in IW2, when IW1 is very little, output just and CK2 very similar, if IW1=IW2 exports the median that is about CK1 and CK2.The NMOS pipe (MD1, MD2) that is output as a diode connection shown in Fig. 2, concerning small-signal analysis, the NMOS pipe of diode connection can be approximately a resistance; Concerning large-signal, NMOS pipe (MD1, MD2) is set up the biasing of a direct current, and output signal range will be near this DC offset voltage; The amplitude of oscillation of output is little, gets back to direct current biasing fast, is applicable to high speed circuit.But during due to large-signal, the NMOS pipe of diode connection non-linear, causes the linearity variation of the phase place of output.Be not suitable for using in high-precision difference circuit.

Another kind of existing phase difference value circuit shown in accompanying drawing 2, circuit adopts resistance to be responsible for as output, no matter be large-signal or small-signal, exports all more linearly, and the amplitude of oscillation of output is large.But in order to produce suitable direct current biasing output voltage, the resistance of resistance and bias current product are restricted, therefore the bandwidth of output is restricted, and is not suitable for high speed circuit.

Summary of the invention

Technical problem to be solved in the utility model is that a kind of phase difference value change-over circuit that can be applicable to high speed circuit is provided.

In order to solve the problems of the technologies described above, the utility model is achieved through the following technical solutions: a kind of phase difference value change-over circuit, there is NMOS pipe MD1, MD2, described NMOS pipe MD1, the source electrode of MD2 is all connected direct current biasing VAA with grid, the drain electrode of described NMOS pipe MD1 connects the source electrode of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor is connected respectively input signal CK1P, CK2P, the drain electrode of described NMOS pipe MD2 connects the source electrode of the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, the grid of the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is connected respectively input signal CK2N, CK1N, the drain electrode of described the first metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is connected control word IW1, the drain electrode of the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor is connected control word IW2, described NMOS pipe MD1, between the grid of MD2 and direct current biasing, be respectively provided with a resistance.

Compared with prior art, usefulness of the present utility model is: the amplitude of oscillation of this phase difference value circuit limitations output, and make output get back to fast direct current biasing, be applicable to high speed circuit, guaranteed certain linearity simultaneously.

accompanying drawing explanation:

Below in conjunction with accompanying drawing, the utility model is further illustrated.

Fig. 1, Fig. 2 are existing phase difference value electrical block diagrams;

Fig. 3 is the utility model phase difference value converting circuit structure schematic diagram.

In figure: 1, resistance; 2, the first metal-oxide-semiconductor; 3, the second metal-oxide-semiconductor; 4, the 3rd metal-oxide-semiconductor; 5, the 4th metal-oxide-semiconductor.

embodiment:

Below in conjunction with the drawings and the specific embodiments, the utility model is described in detail:

A kind of phase difference value circuit shown in Fig. 3, there is NMOS pipe MD1, MD2, described NMOS pipe MD1, the source electrode of MD2 is all connected direct current biasing VAA with grid, the drain electrode of described NMOS pipe MD1 connects the source electrode of the first metal-oxide-semiconductor 2 and the second metal-oxide-semiconductor 3, the grid of the first metal-oxide-semiconductor 2 and the second metal-oxide-semiconductor 3 is connected respectively input signal CK1P, CK2P, the drain electrode of described NMOS pipe MD2 connects the source electrode of the 3rd metal-oxide-semiconductor 4 and the 4th metal-oxide-semiconductor 5, the grid of the 3rd metal-oxide-semiconductor 4 and the 4th metal-oxide-semiconductor 5 is connected respectively input signal CK2N, CK1N, the drain electrode of described the first metal-oxide-semiconductor 2 and the 4th metal-oxide-semiconductor 5 is connected control word IW1, the drain electrode of the second metal-oxide-semiconductor 3 and the 3rd metal-oxide-semiconductor 4 is connected control word IW2, described NMOS pipe MD1, between the grid of MD2 and direct current biasing VAA, be respectively provided with a resistance 1.

Concrete, in low frequency, the grid of managing MD1, MD2 due to NMOS does not have direct current, and the characteristic of the NMOS pipe of this connection and the NMOS pipe of diode connection is the same.In high frequency, buffer action and the grid of NMOS pipe MD1, MD2 and the electric capacity between source electrode due to resistance 1, cause the grid of NMOS pipe MD1, MD2 will follow source electrode, keep certain voltage, thereby guarantee that certain electric current flows through this pipe, charges to output, thereby the amplitude of oscillation of restriction output, make output get back to fast direct current biasing, be applicable to high speed circuit, guaranteed certain linearity simultaneously.

It is emphasized that: be only preferred embodiment of the present utility model above, not the utility model is done to any pro forma restriction, any simple modification, equivalent variations and modification that every foundation technical spirit of the present utility model is done above embodiment, all still belong in the scope of technical solutions of the utility model.

Claims

1. a phase difference value change-over circuit, there is NMOS pipe (MD1, MD2), described NMOS pipe (MD1, MD2) source electrode is all connected direct current biasing (VAA) with grid, the drain electrode of described NMOS pipe (MD1) connects the source electrode of the first metal-oxide-semiconductor (2) and the second metal-oxide-semiconductor (3), the first metal-oxide-semiconductor (2) is connected respectively input signal (CK1P with the grid of the second metal-oxide-semiconductor (3), CK2P), the drain electrode of described NMOS pipe (MD2) connects the source electrode of the 3rd metal-oxide-semiconductor (4) and the 4th metal-oxide-semiconductor (5), the 3rd metal-oxide-semiconductor (4) is connected respectively input signal (CK2N with the grid of the 4th metal-oxide-semiconductor (5), CK1N), the drain electrode of described the first metal-oxide-semiconductor (2) and the 4th metal-oxide-semiconductor (5) is connected control word (IW1), the drain electrode of the second metal-oxide-semiconductor (3) and the 3rd metal-oxide-semiconductor (4) is connected control word (IW2), it is characterized in that: described NMOS pipe (MD1, MD2) between grid and direct current biasing (VAA), be respectively provided with a resistance (1).