CN103490727A - Multiphase generating circuit - Google Patents

Multiphase generating circuit Download PDF

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Publication number
CN103490727A
CN103490727A CN201310381485.9A CN201310381485A CN103490727A CN 103490727 A CN103490727 A CN 103490727A CN 201310381485 A CN201310381485 A CN 201310381485A CN 103490727 A CN103490727 A CN 103490727A
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CN
China
Prior art keywords
module
output
leggy
clock source
multiphase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310381485.9A
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Chinese (zh)
Inventor
刘雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SUZHOU SUERDA INFORMATION TECHNOLOGY Co Ltd
Original Assignee
SUZHOU SUERDA INFORMATION TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SUZHOU SUERDA INFORMATION TECHNOLOGY Co Ltd filed Critical SUZHOU SUERDA INFORMATION TECHNOLOGY Co Ltd
Priority to CN201310381485.9A priority Critical patent/CN103490727A/en
Publication of CN103490727A publication Critical patent/CN103490727A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a multiphase generating circuit which is provided with a clock source module. The output end of the clock source module is connected with a multistage multiphase resistance capacitance filter, a difference value conversion array module and a square wave conversion module in sequence. The output end of the square wave conversion module is connected with an orthogonal compensation module in parallel, and the orthogonal compensation module is connected with the difference value conversion array module. The multistage multiphase resistance capacitance filter at least comprises two stages. The clock source module is a differential output oscillator. The multiphase generating circuit has the advantages that an oscillator of the multiphase generating circuit is stable in output frequency, low in phase noise, simple in technological requirement and small in consumption.

Description

A kind of leggy produces circuit
Technical field
The present invention relates to a kind of circuit, relate in particular to a kind of leggy and produce circuit.
Background technology
Oscillator refers to a kind of circuit, the signal of exportable one or more relative fixed frequencies (square wave or sine wave), the output individual signals is Single-end output, exporting two signals that differ 180 degree phase places is difference output, and the stability of output frequency is general with weighing as parameters such as phase noise or clock jitters.
What leggy generation circuit referred to is also a kind of circuit, according to the differential signal of input, produces the circuit of a plurality of out of phase signals.As produce 0 degree, and 90 degree, the signal of 180 degree and four phase places of 270 degree, or the signal of more eight phase places etc.; The signal of a plurality of phase places is widely used in radio-frequency front-end, the fields such as high speed serialization digital communication.
Existing leggy generation circuit generally depends on oscillator itself and produces a plurality of phase places, as utilizes annular voltage controlled oscillator etc.; But frequency stability or the phase noise of output of oscillator that can produce leggy is poor.The another one method is to allow oscillator operate in twice or higher frequency, and the output process is except two or follow leggy except producing after fourth class divider; Its major defect is, needs oscillator and divider to operate in twice, four times or higher frequency, to technique require highly, power consumption is large.
Summary of the invention
Technical problem to be solved by this invention is to provide the leggy that a kind of output frequency is stable and phase noise is little to produce circuit.
In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions: a kind of leggy produces circuit, there is the clock source module, the output of described clock source module is connected with multistage leggy resistor & capacitor filter, difference conversion array module and square wave modular converter in turn, be parallel with the quadrature compensation module on the output of described square wave modular converter, this quadrature compensation module is connected with difference conversion array module.
Preferably, described leggy resistor & capacitor filter has two-stage at least.
Preferably, described clock source module is difference output oscillator.
Compared with prior art, usefulness of the present invention is: it is stable that this leggy produces its oscillator output frequency of circuit, and phase noise is little, and technological requirement is simple, and power consumption is little.
the accompanying drawing explanation:
Below in conjunction with accompanying drawing, the present invention is further described.
Fig. 1 is that a kind of leggy of the present invention produces the circuit structure block diagram.
In figure: 1, clock source module; 2, leggy resistor & capacitor filter; 3, difference conversion array module; 4, square wave modular converter; 5, quadrature compensation module.
embodiment:
Below in conjunction with the drawings and the specific embodiments, describe the present invention:
Shown in Fig. 1, a kind of leggy produces circuit, there is clock source module 1, the output of described clock source module 1 is connected with two-stage or more leggy resistor & capacitor filter 2, difference conversion array module 3 and square wave modular converter 4 in turn, be parallel with quadrature compensation module 5 on the output of described square wave modular converter 4, this quadrature compensation module 5 is connected with difference conversion array module 3.
Clock source module 1 is the oscillator of certain difference output, output is through two-stage or more leggy resistor & capacitor filter 2, produce the signal of four more coarse phase places, after difference conversion array module 3 is carried out the quadrature phase compensation, be converted to square wave output by square wave modular converter 4, four signals of output are fed back to quadrature compensation module 5 and carry out computing, calculate the error amount of each phase place and desired phase, this error amount is fed back in difference conversion array module 3, and the phase place of output is proofreaied and correct.
It is stable that this leggy produces its oscillator output frequency of circuit, and phase noise is little, and technological requirement is simple, and power consumption is little.
It is emphasized that: above is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, any simple modification, equivalent variations and modification that every foundation technical spirit of the present invention is done above embodiment, all still belong in the scope of technical solution of the present invention.

Claims (3)

1. a leggy produces circuit, it is characterized in that: there is clock source module (1), the output of described clock source module (1) is connected with multistage leggy resistor & capacitor filter (2), difference conversion array module (3) and square wave modular converter (4) in turn, be parallel with quadrature compensation module (5) on the output of described square wave modular converter (4), this quadrature compensation module (5) is connected with difference conversion array module (3).
2. leggy according to claim 1 produces circuit, and it is characterized in that: described leggy resistor & capacitor filter (2) has two-stage at least.
3. leggy according to claim 1 produces circuit, it is characterized in that: described clock source module (1) is difference output oscillator.
CN201310381485.9A 2013-08-29 2013-08-29 Multiphase generating circuit Pending CN103490727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310381485.9A CN103490727A (en) 2013-08-29 2013-08-29 Multiphase generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310381485.9A CN103490727A (en) 2013-08-29 2013-08-29 Multiphase generating circuit

Publications (1)

Publication Number Publication Date
CN103490727A true CN103490727A (en) 2014-01-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310381485.9A Pending CN103490727A (en) 2013-08-29 2013-08-29 Multiphase generating circuit

Country Status (1)

Country Link
CN (1) CN103490727A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217276A (en) * 2007-01-03 2008-07-09 三星电子株式会社 Method and apparatus for generating multi-phase signals
CN102047340A (en) * 2008-05-28 2011-05-04 美光科技公司 Apparatus and method for multi-phase clock generation
CN102684684A (en) * 2012-04-27 2012-09-19 清华大学 Orthogonal clock generating circuit for multichannel forward clock high-speed serial interface
CN102946248A (en) * 2011-08-15 2013-02-27 南亚科技股份有限公司 Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method
CN103036559A (en) * 2011-09-28 2013-04-10 晨星软件研发(深圳)有限公司 Phase locked loop and alignment method of relevant phase positions
CN203504499U (en) * 2013-08-29 2014-03-26 苏州苏尔达信息科技有限公司 Multiphase generation circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217276A (en) * 2007-01-03 2008-07-09 三星电子株式会社 Method and apparatus for generating multi-phase signals
CN102047340A (en) * 2008-05-28 2011-05-04 美光科技公司 Apparatus and method for multi-phase clock generation
CN102946248A (en) * 2011-08-15 2013-02-27 南亚科技股份有限公司 Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method
CN103036559A (en) * 2011-09-28 2013-04-10 晨星软件研发(深圳)有限公司 Phase locked loop and alignment method of relevant phase positions
CN102684684A (en) * 2012-04-27 2012-09-19 清华大学 Orthogonal clock generating circuit for multichannel forward clock high-speed serial interface
CN203504499U (en) * 2013-08-29 2014-03-26 苏州苏尔达信息科技有限公司 Multiphase generation circuit

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Application publication date: 20140101