CN203086441U - Rapid clock generation circuit - Google Patents

Rapid clock generation circuit Download PDF

Info

Publication number
CN203086441U
CN203086441U CN 201320029892 CN201320029892U CN203086441U CN 203086441 U CN203086441 U CN 203086441U CN 201320029892 CN201320029892 CN 201320029892 CN 201320029892 U CN201320029892 U CN 201320029892U CN 203086441 U CN203086441 U CN 203086441U
Authority
CN
China
Prior art keywords
controlled oscillator
voltage controlled
phase comparator
analog
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201320029892
Other languages
Chinese (zh)
Inventor
吴朝荣
周慰君
陈中
吴泽源
陈焕洵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Liliput Optoelectronics Technology Co Ltd
Original Assignee
Fujian Liliput Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Liliput Optoelectronics Technology Co Ltd filed Critical Fujian Liliput Optoelectronics Technology Co Ltd
Priority to CN 201320029892 priority Critical patent/CN203086441U/en
Application granted granted Critical
Publication of CN203086441U publication Critical patent/CN203086441U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The utility model discloses a rapid clock generation circuit which comprises a quartz crystal capable of generating 10MHz low-frequency signals, a processor and an analogy phase-locked loop wherein the analogy phase-locked loop comprises a phase comparator, a charge pump, a loop filter and a voltage controlled oscillator, which are sequentially connected. The circuit further comprises a digital-analog conversion chip for providing tuning voltage to the voltage controlled oscillator. The output terminal of the quartz crystal is connected with the first input terminal of the phase comparator, and the feedback terminal of the voltage controlled oscillator is connected with the second input terminal of the phase comparator. A prescaler is arranged on the connection line between the voltage controlled oscillator and the phase comparator, and the output terminal of the processor is connected with the input terminal of the digital-analog conversion chip. The output terminal of the digital-analog conversion chip is connected with the input terminal of the voltage controlled oscillator, and the voltage controlled oscillator, the charge pump, the phase comparator, the loop filter and a pre distributor form a negative feedback system. The rapid clock generation circuit is capable of providing 4GHz clock signals, and is dynamically adjustable and highly stable.

Description

A kind of high-frequency clock produces circuit
Technical field
The utility model relates to a kind of high-frequency clock and produces circuit.
Background technology
Development along with instrument and meter industry, sample rate such as oscilloscope, signal generator requires up to several GHz and dynamically can be provided with, but this just require to need in the system one can produce up to several GHz and frequency dynamic programming, clock circuit that stability is high give the ADC(modulus conversion chip) or the DAC(analog-digital chip) make sampling clock, the conventional quartz crystal is subjected to the influence of its structural manufacturing process, can only produce the signal of fixed frequency, and frequency often is lower than 200M, can't satisfy the requirement of system.
Summary of the invention
The purpose of this utility model is to provide a kind of and provides up to 4 GHz and dynamic adjustable and the high high-frequency clock generation circuit of stability.
For achieving the above object, the utility model adopts following design, it comprises the quartz crystal that produces the 10Mhz low frequency signal, processor, analog phase-locked look, described analog phase-locked look comprises the phase comparator that connects in turn, charge pump, loop filter, voltage controlled oscillator, described circuit also is included as the analog-digital chip that voltage controlled oscillator provides tuning voltage, the output of described quartz crystal connects the first input end of phase comparator, the feedback end of described voltage controlled oscillator connects second input of phase comparator, also be provided with pre-divider on the connection line of described voltage controlled oscillator and phase comparator, the output of described processor connects the input of analog-digital chip, the output of described analog-digital chip connects the input of voltage controlled oscillator, described voltage controlled oscillator, charge pump, phase comparator, loop filter and presort orchestration and constitute degeneration factor.
Described processor is connected by the spi bus mode with analog-digital chip.
The utility model adopts above design, the reference clock source of stable low drift is provided by quartz crystal, phase comparator comparison reference clock and voltage controlled oscillator are through the phase place of signal behind the frequency division, phase difference is converted to voltage signal to charge to charge pump, export bigger voltage and provide purer differential mode voltage for voltage controlled oscillator through loop filter, and with the voltage of analog-digital chip output mutually adduction provide tuning voltage for voltage controlled oscillator, the signal of voltage controlled oscillator output is a high-speed clock signal, and the frequency division value that changes analog-digital chip or pre-divider in the processor just can realize exporting the high-speed clock signal of different frequency.
Description of drawings
Below in conjunction with the drawings and specific embodiments the utility model is described in further detail:
Fig. 1 is the utility model execution mode schematic diagram.
Embodiment
As shown in Figure 1, the utility model comprises the quartz crystal 1 that produces the 10Mhz low frequency signal, processor 2, analog phase-locked look 3, described analog phase-locked look comprises the phase comparator 31 that connects in turn, charge pump 32, loop filter 33, voltage controlled oscillator 34, described circuit also is included as the analog-digital chip 4 that voltage controlled oscillator 34 provides tuning voltage, the output of described quartz crystal 1 connects the first input end of phase comparator 31, the feedback end of described voltage controlled oscillator 34 connects second input of phase comparator 31, also be provided with pre-divider 35 on the connection line of described voltage controlled oscillator 34 and phase comparator 31, the output of described processor 2 connects the input of analog-digital chip 4, the output of described analog-digital chip 4 connects the input of voltage controlled oscillator 34, described voltage controlled oscillator 34, phase comparator 31, loop filter 33, charge pump 32 and pre-divider 35 constitute degeneration factor.
Described processor 2 and analog-digital chip 4 are connected by spi bus.
Operation principle of the present utility model is: the reference clock source that stable low drift is provided by quartz crystal 1, phase comparator 31 comparison reference clocks and voltage controlled oscillator 34 are through the phase place of signal behind the frequency divisions, phase difference is converted to voltage signal gives charge pump 32 chargings, export bigger voltage and provide purer differential mode voltage for voltage controlled oscillator 34 through loop filter 33, and with the voltage of analog-digital chip 4 output mutually adduction provide tuning voltage for voltage controlled oscillator 34, the signal of voltage controlled oscillator 34 outputs is a high-speed clock signal, the frequency division value that changes analog-digital chip 4 or pre-divider 35 in the processor 2 just can realize exporting different frequency, even reaches the high-speed clock signal of 4Ghz.

Claims (2)

1. a high-frequency clock produces circuit, it is characterized in that: it comprises the quartz crystal that produces the 10Mhz low frequency signal, processor, analog phase-locked look, described analog phase-locked look comprises the phase comparator that connects in turn, charge pump, loop filter, voltage controlled oscillator, described circuit also is included as the analog-digital chip that voltage controlled oscillator provides tuning voltage, the output of described quartz crystal connects the first input end of phase comparator, the feedback end of described voltage controlled oscillator connects second input of phase comparator, also be provided with pre-divider on the connection line of described voltage controlled oscillator and phase comparator, the output of described processor connects the input of analog-digital chip, the output of described analog-digital chip connects the input of voltage controlled oscillator, described voltage controlled oscillator, charge pump, phase comparator, loop filter and presort orchestration and constitute degeneration factor.
2. high-frequency clock according to claim 1 produces circuit, and it is characterized in that: described processor is connected by spi bus with analog-digital chip.
CN 201320029892 2013-01-21 2013-01-21 Rapid clock generation circuit Expired - Fee Related CN203086441U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201320029892 CN203086441U (en) 2013-01-21 2013-01-21 Rapid clock generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201320029892 CN203086441U (en) 2013-01-21 2013-01-21 Rapid clock generation circuit

Publications (1)

Publication Number Publication Date
CN203086441U true CN203086441U (en) 2013-07-24

Family

ID=48832243

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201320029892 Expired - Fee Related CN203086441U (en) 2013-01-21 2013-01-21 Rapid clock generation circuit

Country Status (1)

Country Link
CN (1) CN203086441U (en)

Similar Documents

Publication Publication Date Title
CN103731136B (en) Sequential equivalent sampling circuit and method based on delay signals
CN102723931B (en) The pulse wave generation method that a kind of wide dynamic high precision edge time is adjustable
CN102331979A (en) Dynamic clock frequency calibration method applied to universal serial bus (USB) equipment
CN101714875B (en) Phase-locked loop circuit
CN102045062A (en) Digital phase-locked loop based on Cordic algorithm
CN106656122B (en) Device and method for adjusting the duty ratio in clock signal
CN203324462U (en) System for performing test and calibration on magnetic sensors
CN103713159A (en) Feedback method of closed-loop micromechanics accelerometer
CN203086441U (en) Rapid clock generation circuit
CN102208911B (en) Window clock generation and dynamic configuration method based on phase-locked loop in FPGA (Field Programmable Gate Array) sheet
CN103647553B (en) Direct current frequency modulation reference source circuit of broadband ultra low phase noise
CN108199699A (en) A kind of stable duty ratio and low-jitter clock circuit
CN202957806U (en) FPGA-based DDS signal generator
CN102055438B (en) High-speed square wave generating device and method
CN104090160A (en) High-precision frequency measuring device
CN103576118A (en) System for detecting and calibrating magnetic sensor
CN203482173U (en) Signal generator with multipath signal superposition function
CN105116802A (en) An apparatus and method for generating deterministic clock jittering
CN205070990U (en) A crystal oscillator frequency dividing circuit that is used for radio general measuring instrument radio frequency local oscillator circuit
CN107395166B (en) Clock duty ratio stabilizing circuit based on delay phase locking
CN202231700U (en) Servo circuit for rubidium atomic frequency standard as well as rubidium atomic frequency standard
Nan et al. Design of PLL behavioral model based on the Verilog-A
CN204480671U (en) A kind of antimierophonic delay counter
CN104954024B (en) Sigma-delta ADC control signal synchronous method based on FPGA
CN105306068A (en) Parallel-serial conversion circuit based on clock phase modulation

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
EXPY Termination of patent right or utility model
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130724

Termination date: 20160121