CN103489782B - The manufacture method of trench power semiconductor structure - Google Patents
The manufacture method of trench power semiconductor structure Download PDFInfo
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- CN103489782B CN103489782B CN201210195911.5A CN201210195911A CN103489782B CN 103489782 B CN103489782 B CN 103489782B CN 201210195911 A CN201210195911 A CN 201210195911A CN 103489782 B CN103489782 B CN 103489782B
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 50
- 238000002955 isolation Methods 0.000 claims description 10
- 239000004575 stone Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229960001866 silicon dioxide Drugs 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
The invention provides a kind of manufacture method of trench power semiconductor structure, comprise the following steps: first to provide a base material and form a dielectric pattern layer on base material, to define an active region and a termination environment, the part base material of above-mentioned active region and the base material of termination environment are covered by dielectric pattern layer; Then,, selectively to build brilliant mode, grow up one first epitaxial layer on the base material not covered by dielectric pattern layer; Subsequently, remove the dielectric pattern layer on active region, to form a gate trench on base material; Form a gate dielectric in gate trench with the first epitaxial layer on and form a grid structure in gate trench; Finally, utilizing the dielectric pattern layer on termination environment is shielding, forms this tagma in the first epitaxial layer or on it, and forms the upper part in Yu Zhe tagma, one source pole district. The present invention reduces the technique of one light shield, and then reduces the great number cost of making light shield, and can avoid in light shield alignment procedures the foozle causing.
Description
Technical field
The present invention relates to a kind of manufacture method of power semiconductor structure, and be particularly related to a kind of ditchThe manufacture method of slot type power semiconductor structure.
Background technology
Along with energy-conservation demand is surging gradually, need higher energy conversion efficiency. These increasinglyStrict design specification requirement is a severe challenge for power supply changeover device designer. ForIn response to this demand, power component institute's role in efficient converter is healed and is become important. Wherein,Power MOSFET transistor (PowerMOSFET) be widely used at present variousOne of semiconductor element of power supply changeover device.
In traditional plane formula metal-oxide half field effect transistor, current trend is along being parallel to base materialThe trend on surface, and ditch type metal-oxide half field effect transistor element is that grid is arranged to grooveIn, and change the channel position of metal-oxide half field effect transistor element, make metal-oxide half field effect transistorThe current trend of element is perpendicular to base material. Whereby, can dwindle the size of element, raising elementActively degree, and be conducive to reduce cost of manufacture. Traditional ditch type metal-oxide half field effect transistor elementMaking, at least need to use six road light shield operations (micro-shadow operation), wherein, source area with thisThe making in tagma, just need to use twice optical cover process. At the initial stage of element exploitation, light shieldMake is a huge expense, adds the system at ditch type metal-oxide half field effect transistor elementWhile work, the consuming time and foozle of light shield operation, often causes the increase of cost of manufacture.
More and more focus at present the semi-conductor market of price competitiveness, therefore, find a letterSingle preparation method, improves the complexity of manufacturing process, and the competitive advantage that promotes price can not be fallen againEffect of low element is important problem of the art.
Summary of the invention
In view of this, the manufacture method of a kind of trench power semiconductor structure provided by the invention,By means of first form dielectric pattern layer on active region and termination environment, then, utilize selective of heap of stone brilliantMode, first epitaxial layer of growing up on the base material not covered by dielectric layer, then removes active regionOn dielectric pattern layer, and only leave dielectric layer pattern layer on termination environment for shielding, carry out bodyThe manufacture of district and source area, so, can reduce the technique of one light shield, and then reduces and make lightThe great number cost of cover, and can avoid in light shield alignment procedures the foozle causing.
The embodiment of the present invention provides a kind of manufacture method of trench power semiconductor structure, comprisesThe following step: first, provide a base material; Then, form a dielectric pattern layer on base material, withDefine an active region and a termination environment, wherein, the part base material of active region and the base material of termination environmentCovered by dielectric pattern layer; Next, selectively to build brilliant mode, one first crystalline substance of heap of stone of growing upLayer is on the base material not covered by dielectric pattern layer; Subsequently, remove the dielectric pattern on active regionLayer, to form a gate trench on base material; Then, form a gate dielectric in gate trenchIn with the first epitaxial layer on and form a grid structure in gate trench; Finally, utilize terminalDielectric pattern floor in district is shielding, forms this tagma in the first epitaxial layer or the first epitaxial layerUpper, and the upper part in formation Yu Zhe tagma, one source pole district.
In one of them embodiment of the present invention, the manufacture method of above-mentioned power semiconductor structure alsoBe included in and form before the step of this gate dielectric in this gate trench, first etching grid trench bottomThe step of portion.
In one of them embodiment of the present invention, in the manufacture method of above-mentioned power semiconductor structure,After the step of etching grid channel bottom, and forming the step of gate dielectric in gate trenchBefore rapid, also comprise: form sacrificial oxide layer step on this base material in gate trench.
In one of them embodiment of the present invention, in the manufacture method of above-mentioned power semiconductor structure,This tagma is formed in the first epitaxial layer in the mode of implanted ions.
In one of them embodiment of the present invention, in the manufacture method of above-mentioned power semiconductor structure,This tagma is formed on the first epitaxial layer to build brilliant mode.
In one of them embodiment of the present invention, in the manufacture method of above-mentioned power semiconductor structure,Source area is formed at the upper part in this tagma in the mode of implanted ions.
In one of them embodiment of the present invention, in the manufacture method of above-mentioned power semiconductor structure,The thickness of the first epitaxial layer is greater than the thickness of gate dielectric.
In one of them embodiment of the present invention, in the manufacture method of above-mentioned power semiconductor structure,The formation step of this tagma and source area is to complete after the formation step of gate dielectric.
In one of them embodiment of the present invention, in the manufacture method of above-mentioned power semiconductor structure,Dielectric pattern layer comprises a bottom dielectric structure, an isolation structures and a masking structure.
In one of them embodiment of the present invention, in the manufacture method of above-mentioned power semiconductor structure,The thickness of the first epitaxial layer is greater than the thickness of bottom dielectric structure.
Make groove power semiconductor according to manufacturing method thereof of the present invention, from base material to protective layerManufacture process, only need five road light shields to complete, so can also reduce being made into of entiretyOriginally, further promote the competitive advantage of price.
In order further to understand feature of the present invention and technology contents, refer to following relevantDetailed description of the present invention and accompanying drawing, but these explanations are graphicly only used for illustrating this with appendedBright, and unrestricted the present invention.
Brief description of the drawings
Figure 1A to Fig. 1 G is the manufacture of the trench power semiconductor structure of the embodiment of the present invention oneMethod;
Fig. 2 A to Fig. 2 E is the manufacture of the trench power semiconductor structure of the embodiment of the present invention twoMethod;
Fig. 3 A to Fig. 3 C is the manufacture of the trench power semiconductor structure of the embodiment of the present invention threeMethod;
Fig. 4 A is the manufacture method of the trench power semiconductor structure of the embodiment of the present invention four;
Fig. 4 B is the manufacture method of the trench power semiconductor structure of the embodiment of the present invention five.
[main element description of reference numerals]
Substrate 100
Base material 101
Active region 102
Termination environment 103
Epitaxial layer 110
Dielectric layer 120
Dielectric pattern layer 120 '
The first epitaxial layer 130,230,431,432
Gate trench 140,240,340
Gate dielectric 150,250,350
Grid structure 160,260,360
This tagma 170,270,370,471,472
Source area 180,280,380,481,482
Bottom dielectric layer 220
Isolation layer 221
Shielding layer 222
Bottom dielectric structure 220 '
Isolation structures 221 '
Masking structure 222 '
Detailed description of the invention
Embodiment mono-
Please refer to Figure 1A to Fig. 1 G, Figure 1A to Fig. 1 G is the plough groove type of the embodiment of the present invention oneThe manufacture method of power semiconductor structure. As shown in Figure 1A, first provide a base material 101, thisBase material 101 comprises a substrate 100 and an epitaxial layer 110. Then, form a dielectric layer 120 inOn base material 101, dielectric layer 120 is formed on base material 110 with depositional mode, but the present invention not withThis is limited, and the mode that can also be oxidized is grown up on base material. Next, carry out micro image etching procedureOperation to be to make a dielectric pattern layer 120 ' on base material 101, and defines an active region 102On base material 101, as shown in Figure 1B, be positioned at the crystalline substance of heap of stone of active region 102 with a termination environment 103Layer 110, only has part to be covered by dielectric pattern layer 120 ', is positioned at the crystalline substance of heap of stone of termination environment 103Layer 110, is all covered by dielectric pattern layer 120 '.
In this embodiment, epitaxial layer 110 is formed at substrate 100 by building crystal to grow modeTop. Substrate 100 can be silicon substrate (siliconsubstrate), and the kind of substrate is mixed with itThe conductivity type of foreign material there is no certain restriction. Epitaxial layer 110 can also be omitted, and base material is basePlate, and subsequent manufacturing processes is directly formed on substrate.
Next, as shown in Figure 1 C, selectively to build brilliant mode, one first epitaxial layer of growing up130 on base material 101, and the first epitaxial layer 130 is only grown up in active region 102 not by dielectricOn the epitaxial layer 110 that patterned layer 120 ' covers. In the present embodiment, the first epitaxial layer 130Identical with the conductivity type of base material 101. The thickness of the first epitaxial layer 130 is lower than dielectric pattern layer 120 'Thickness, in addition, the thickness of the first epitaxial layer 130 also can equal the thick of dielectric pattern layer 120 'Degree (not shown).
Then,, as shown in Fig. 1 D, carry out micro image etching procedure by the dielectric figure on active region 102Case layer 120 ' removes, to form a gate trench 140 on base material 101. For follow-up growthIn the operation of gate dielectric, make the even thickness of gate dielectric, next, as Fig. 1 E instituteShow, carry out the operation of etched trench bottom, with by gate trench 140 bottom corners, then shapesBecome sacrificial oxide layer (not shown) to repair epitaxial layer surface, then sacrificial oxide layer is removed. ?In the present embodiment, the step shown in Fig. 1 E can also be omitted, and directly carries out subsequent handling.
Subsequently, as shown in Fig. 1 F, form a gate dielectric 150 on the first epitaxial layer 130In gate trench 140. Above-mentioned gate dielectric 150 can, by the mode of thermal oxide, form oxygenSiClx on the first epitaxial layer 130 not covered by dielectric pattern layer 120 ' with gate trench 140Inner surface. In addition, gate dielectric 150 also can be by the mode of chemical vapour deposition (CVD),Be formed on the first epitaxial layer 130, in gate trench 140 with dielectric pattern layer 120 ' on. ?In practical operation, gate dielectric 150 can be by silica (silicondioxide) or high dielectricThe material of value forms.
Finally, as shown in Figure 1 G, first deposit compound crystal silicon on base material 101, then impose etch-backMode form a grid structure 160 in gate trench 140. Then, utilize on this termination environmentDielectric pattern layer 120 ' be shielding with grid structure 160, form this tagma 170 in firstIn epitaxial layer 130. Subsequently, form the upper part in 180Yu Zhe tagma, one source pole district 170. This realityExecute in example, the generation type of this tagma 170 and source area 180, is the mode shape with implanted ionsBe formed in the first epitaxial layer 130.
Embodiment bis-
In addition, can, according to the structural change of above-mentioned dielectric pattern layer 120 ', form bottom dielectricStructure is in the below of gate trench, further to obtain lower gate-to-drain electric capacity (Cgd).Embodiment please refer to Fig. 2 A to Fig. 2 E, and Fig. 2 A to Fig. 2 E is the ditch of the embodiment of the present invention twoThe manufacture method of slot type power semiconductor structure.
As shown in Figure 2 A, first, form epitaxial layer 110 on substrate 100, then, formDielectric layer on base material 100, dielectric layer comprise a bottom dielectric layer 220, an isolation layer 221 withOne shielding layer 222. Above-mentioned isolation layer 221 can be selected silicon nitride (SiN) material, but the present inventionNot as limit, as long as material selection and bottom dielectric layer 220 and the shielding layer of isolation layer 221222 is different, and bottom dielectric layer 220 can select oxide material with shielding layer 222, butThe present invention, not as limit, needs only bottom dielectric layer 220 and has high dielectric radio, and shielding layer 222Material and isolation layer 221 materials are different.
Next, as shown in Figure 2 B, carry out lithography operation to make dielectric pattern layer in of heap of stoneOn crystal layer 110, above-mentioned dielectric pattern layer comprises a bottom dielectric structure 220 ', an isolated knotStructure 221 ' and a masking structure 222 '. Subsequently, as shown in Figure 2 C, selectively to build brilliant sideFormula, grows up one first epitaxial layer 230 on the epitaxial layer 110 not covered by dielectric pattern layer.
Then, as shown in Figure 2 D, carry out, after micro-shadow operation, utilizing the method for selective etch,First the masking structure in active region 102 222 ' is removed, subsequently, recycle another and selectively loseThe method of carving, removes isolation structures 221 ', only retains bottom dielectric structure 220 ' Yu LeijingOn layer 110, to form a gate trench 240 in bottom dielectric structure 220 '.
Finally, as shown in Figure 2 E, form a gate dielectric 250 on the first epitaxial layer 230In gate trench 240. Next, form a grid structure 260 in gate trench 240.Then, utilizing dielectric pattern layer and grid structure 260 on this termination environment 103 is shielding, formsOne this tagma 270 is in the first epitaxial layer 230, and the degree of depth in this tagma 270 must be less than gridThe degree of depth of groove 240. Subsequently, form the upper part in 280Yu Zhe tagma, one source pole district 270. ThisIn embodiment, be positioned at the dielectric pattern layer of termination environment 103, comprise bottom dielectric structure 220 ',Isolation structures 221 ' and masking structure 222 '.
Embodiment tri-
Then, please refer to Fig. 3 A to Fig. 3 C, is the groove-type power half of the embodiment of the present invention threeThe manufacture method of conductor structure. Be different from above-described embodiment one, form the step in source area and this tagmaSuddenly, be after gate dielectric forms, the present embodiment is to form it completing in gate dielectricBefore. As shown in Figure 3A, immediately Fig. 1 C of embodiment mono-, after the first epitaxial layer 130 completes,Utilizing active region 102 and the dielectric pattern layer 120 ' in termination environment 103 is shielding, and with ionThe mode of implanting, forms this tagma 370 in the first epitaxial layer 130, subsequently, forms a sourceThe upper part in 380Yu Zhe tagma, polar region 370.
Next, as shown in Figure 3 B, remove dielectric pattern layer 120 ', and form a gate trench340 in epitaxial layer 110 tops, subsequently, impose the method for gate trench 340 bottom corners.Finally, as shown in Figure 3 C, form a gate dielectric 350 on the first epitaxial layer 130 with gridIn utmost point groove 340. Then, form a grid structure 360 in gate trench 340.
Embodiment tetra-
Fig. 4 A is the manufacture method of the trench power semiconductor structure of the embodiment of the present invention four. NoBe same as described embodiment mono-, this tagma 170 is to form in the mode of implanted ions with source area 180,This tagma 471 of the present embodiment is to build brilliant mode to form with source area 481.
As shown in Figure 4 A, be next to Figure 1B of embodiment mono-, after dielectric pattern layer 120 ' completes,Taking dielectric pattern layer 120 ' as shielding, and with selective building crystal to grow technology, first form and base materialOn the epitaxial layer 110 of one first epitaxial layer 431 of 101 same conductivity in active region. Connect downCome, with selective building crystal to grow technology, form this tagma 471 on the first epitaxial layer 431,The conductivity type in this tagma 471 is different from the first epitaxial layer 431.
Finally, form the upper part in 481Yu Zhe tagma, one source pole district 471. Above-mentioned source area 481Generation type, can be formed in this tagma 471 by the mode of implanted ions, can also with choosingThe mode of selecting property building crystal to grow, is formed on this tagma 471. Above-mentioned the first epitaxial layer 431 thickDegree must be greater than in subsequent step, the thickness of the gate dielectric of formation.
Embodiment five
Fig. 4 B is the manufacture method of the trench power semiconductor structure of the embodiment of the present invention five. NoBe same as described embodiment bis-, this tagma 270 is to form in the mode of implanted ions with source area 280,This tagma 472 of the present embodiment is to build brilliant mode to form with source area 482.
As shown in Figure 4 B, immediately Fig. 2 B of embodiment mono-, after dielectric pattern layer completes, to be situated betweenElectrical pattern layer is shielding, and with selective building crystal to grow technology, first forms lead identical with base material 101On the epitaxial layer 110 of one first epitaxial layer 432 of electricity type in active region. It should be noted thatThe thickness of the first epitaxial layer 432 must be greater than bottom dielectric structure 220 '.
Next,, with selective building crystal to grow technology, form this tagma 472 of heap of stone brilliant in firstOn layer 432, the conductivity type in this tagma 472 is different from the first epitaxial layer 432. Finally, form oneSource area 482 is in the upper part in this tagma 472.
The above, the embodiment of the present invention provides the manufacture method of a trench power semiconductor structure,Can utilize the dielectric pattern layer on active region and termination environment, and the selective brilliant method of heap of stone of collocation, becomeLong the first epitaxial layer, on the base material not covered by dielectric layer, so, carries out this tagma and source areaManufacture, can reduce the operation of one light shield, and then simplify the manufacture of groove power semiconductorMethod.
The foregoing is only embodiments of the invention, it is not in order to limit to protection model of the present inventionEnclose.
Claims (10)
1. a manufacture method for trench power semiconductor structure, is characterized in that, comprising:
One base material is provided;
Form a dielectric pattern layer on base material, to define an active region and a termination environment, itsIn the part base material of this active region and the base material of this termination environment covered by this dielectric pattern layer;
In selective brilliant mode of heap of stone, one first epitaxial layer of growing up is not in by this dielectric pattern layer instituteOn this base material covering;
Remove this dielectric pattern layer on this active region, to form at least one gate trench in this baseOn material;
Form a gate dielectric in this gate trench with this first epitaxial layer on;
Form a grid structure in this gate trench;
Utilizing this dielectric pattern layer on this termination environment is shielding, form this tagma in this firstIn epitaxial layer; And
Form the upper part in Yu Gaizhe tagma, one source pole district.
2. the manufacture method of trench power semiconductor structure as claimed in claim 1, itsBe characterised in that, before the step at this gate dielectric of formation in this gate trench, also comprise:The step of this gate trench bottom of etching.
3. the manufacture method of trench power semiconductor structure as claimed in claim 2, itsBe characterised in that, after the step of the bottom of this gate trench of etching, and forming this gate dielectricBefore the step of layer in this gate trench, also comprise: form a sacrificial oxide layer in this grid ditchStep in groove and on this base material.
4. the manufacture method of trench power semiconductor structure as claimed in claim 1, itsBe characterised in that, this this tagma is formed in this first epitaxial layer in the mode of implanted ions.
5. the manufacture method of trench power semiconductor structure as claimed in claim 4, itsBe characterised in that, this source area is formed at the upper part in this this tagma in the mode of implanted ions.
6. the manufacture method of trench power semiconductor structure as claimed in claim 1, itsBe characterised in that, the thickness of this first epitaxial layer is greater than the thickness of this gate dielectric.
7. the manufacture method of trench power semiconductor structure as claimed in claim 1, itsBe characterised in that the formation step of this this tagma and this source area is to complete in this gate dielectricAfter the formation step of layer.
8. the manufacture method of trench power semiconductor structure as claimed in claim 1, itsBe characterised in that, this dielectric pattern layer comprises that a bottom dielectric structure, an isolation structures and coverStructure.
9. the manufacture method of trench power semiconductor structure as claimed in claim 8, itsBe characterised in that, the thickness of this first epitaxial layer is greater than the thickness of this bottom dielectric structure.
10. a manufacture method for trench power semiconductor structure, is characterized in that, comprising:
One base material is provided;
Form a dielectric pattern layer on base material, to define an active region and a termination environment, itsIn the part base material of this active region and the base material of this termination environment covered by this dielectric pattern layer;
In selective brilliant mode of heap of stone, one first epitaxial layer of growing up is not in by this dielectric pattern layer instituteOn this base material covering;
Utilize this dielectric pattern layer for shielding, form this tagma on this first epitaxial layer; WithAnd
Form the upper part in Yu Gaizhe tagma, one source pole district.
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| CN105428396B (en) * | 2015-11-16 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | The terminal structure and its manufacturing method of power device |
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|---|---|---|---|---|
| CN1426598A (en) * | 2000-03-31 | 2003-06-25 | 通用半导体公司 | Method for making trench gate DMOS transistor |
| CN101728266A (en) * | 2008-10-15 | 2010-06-09 | 尼克森微电子股份有限公司 | Manufacturing method of ditch-type power semiconductor |
| CN101807546A (en) * | 2009-02-13 | 2010-08-18 | 尼克森微电子股份有限公司 | Trench type metal-oxide semiconductor device and manufacture method thereof |
| CN102222617A (en) * | 2010-04-14 | 2011-10-19 | 科轩微电子股份有限公司 | Manufacturing method of high density structure of trench power semiconductor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7217976B2 (en) * | 2004-02-09 | 2007-05-15 | International Rectifier Corporation | Low temperature process and structures for polycide power MOSFET with ultra-shallow source |
| JP5096739B2 (en) * | 2006-12-28 | 2012-12-12 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1426598A (en) * | 2000-03-31 | 2003-06-25 | 通用半导体公司 | Method for making trench gate DMOS transistor |
| CN101728266A (en) * | 2008-10-15 | 2010-06-09 | 尼克森微电子股份有限公司 | Manufacturing method of ditch-type power semiconductor |
| CN101807546A (en) * | 2009-02-13 | 2010-08-18 | 尼克森微电子股份有限公司 | Trench type metal-oxide semiconductor device and manufacture method thereof |
| CN102222617A (en) * | 2010-04-14 | 2011-10-19 | 科轩微电子股份有限公司 | Manufacturing method of high density structure of trench power semiconductor |
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