CN103474432B - A kind of array base palte and preparation method thereof and display unit - Google Patents
A kind of array base palte and preparation method thereof and display unit Download PDFInfo
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- CN103474432B CN103474432B CN201310383020.7A CN201310383020A CN103474432B CN 103474432 B CN103474432 B CN 103474432B CN 201310383020 A CN201310383020 A CN 201310383020A CN 103474432 B CN103474432 B CN 103474432B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 239000011159 matrix material Substances 0.000 claims abstract description 168
- 230000004888 barrier function Effects 0.000 claims abstract description 85
- 239000010409 thin film Substances 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000010408 film Substances 0.000 claims abstract description 30
- 238000009413 insulation Methods 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 57
- 239000000463 material Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 26
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- 238000002161 passivation Methods 0.000 claims description 19
- 150000002739 metals Chemical class 0.000 claims description 10
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- 239000011651 chromium Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 229910003437 indium oxide Inorganic materials 0.000 description 5
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
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- 239000000203 mixture Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- -1 Cu and alloy thereof Chemical class 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a kind of array base palte and preparation method thereof and display unit, in order to reduce the voltage differences of common electrode layer between different pixels unit, increase the aperture opening ratio of pixel simultaneously.Array base palte comprises: underlay substrate, the grid line of arranged crosswise, data wire and the pixel cell arranged in matrix that marked off by described grid line and data wire on described underlay substrate, thin-film transistor, pixel electrode and common electrode layer is provided with in described pixel cell, described thin-film transistor comprises grid, the first insulating barrier, source electrode, drain electrode and active layer, described array base palte also comprises: the black matrix with electric conductivity being arranged on the non-display area of pixel cell, and described black matrix is electrically connected with described common electrode layer; And, for the second insulating barrier by described black matrix and common electrode layer and described film crystal pipe insulation, the overlay area of described second insulating barrier and the covering area overlapping of described black matrix and described common electrode layer.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of array base palte and preparation method thereof and display unit.
Background technology
Thin Film Transistor-LCD (ThinFilmTransistorLiquidCrystalDisplay, TFT-LCD) there is the features such as volume is little, low in energy consumption, radiationless, obtain in recent years and develop by leaps and bounds, in current flat panel display market, occupy leading position.TFT-LCD is widely used on various big-and-middle undersized product, almost cover the primary electron product of current information-intensive society, as LCD TV, high definition digital television, computer, mobile phone, car-mounted display, Projection Display, video camera, digital camera, electronic watch, calculator, electronic instrument and meter, public display and illusory display etc.
TFT-LCD is made up of display panels, drive circuit and backlight module, and display panels is the pith of TFT-LCD.Display panels is by injecting liquid crystal between array base palte and color membrane substrates, and surrounding sealed plastic box seals, on array base palte and color membrane substrates, then stick that the process such as the orthogonal polarizer in polarization direction formed respectively.Wherein said array base palte is formed with the thin-film transistor of matrix arrangement, pixel electrode and peripheral circuit.Color membrane substrates (ColorFilter, CF) is formed pixel by red (R), green (G), blue (B) three primary colors resin, and is formed with transparent public electrode.
In order to block the light of transmission region, the liquid crystal panel of prior art is all provided with black matrix on color membrane substrates.In the design, the width of black matrix be light leak region width with to box trueness error sum, but due to comparatively large to box trueness error, cause the width d1 of the black matrix be arranged on color membrane substrates general larger, aperture opening ratio is low and the defect such as display brightness is low to cause TFT-LCD to exist.
Simultaneously, in order to reduce the voltage differences of public electrode between pixel, for multi-dimensional electric field type TFT-LCD, design is had to be illustrated in fig. 1 shown below at present, Fig. 1 is for reducing the sectional structure chart of the display floater of common electrode layer resistance in prior art, the common electrode layer 20 of electrically conducting transparent is directly placed in grid 10 with on the metal level 11 of layer, metal level 11 material therefor like this owing to arranging with layer with grid 10 is generally chromium (Cr), tungsten (W), titanium (Ti), (Ta), (Mo), (Al), (Cu) metal and the alloy thereof such as, common electrode layer 20 is generally tin indium oxide, indium zinc oxide, aluminum zinc oxide etc., the former resistivity is much less than the resistivity of the latter, thus the all-in resistance after both parallel connections is more much smaller than the resistance of common electrode layer, effectively can reduce the resistance value of common electrode layer, thus the voltage differences of public electrode between minimizing pixel.But owing to being non-transparent metals with described grid 10 with the metal level 11 of layer, therefore very large loss can be caused to the aperture opening ratio of pixel.
See Fig. 1 and Fig. 2, wherein Fig. 2 planar structure schematic diagram that is the display floater shown in Fig. 1.Composition graphs 1 and Fig. 2, can find out that described display floater comprises: tft array substrate, color membrane substrates, and the liquid crystal layer (not shown) be arranged between described array base palte and described color membrane substrates, wherein said array base palte comprises: grid 10, to arrange with layer with described grid 10 and with the metal level 11 of material and grid line 12, the common electrode layer 20 of electrically conducting transparent, and described common electrode layer 20 covers described metal level 11; First insulating barrier 30, active layer 40, data line layer 50(specifically comprises: data wire 501, source electrode 502 and drain electrode 503), and pixel electrode layer 60; Wherein, described grid 10, first insulating barrier 30, active layer 40, data line layer 50 constitutes a thin-film transistor, and grid line 12 is for providing start signal to thin-film transistor, and data wire 501 is for providing data-signal to pixel electrode 60; Wherein pixel electrode 60 is also a transparency conducting layer, arranges with layer with data line layer 50, and is electrically connected with described drain electrode 503.On the liquid crystal be applied between array base palte and color membrane substrates to make the electric field energy between common electrode layer 20 and pixel electrode 60, pixel electrode 60 is generally designed to plane hollow structure, as shown in Figure 3.First can be formed after data line layer 50 through patterning processes in technique in addition and form pixel electrode layer 60 again, also first can be formed after pixel electrode layer 60 through patterning processes and form data line layer 50 again, patterning processes mentioned here mainly comprises film forming, the processes such as exposure and etching.
Described array base palte also comprises the protective layer 70 be arranged on above described thin-film transistor and pixel electrode 60, and described protective layer 70 is not corroded for the protection of thin-film transistor.Described display floater also comprises the black matrix 80 be arranged on described color membrane substrates 200, and described black matrix 80 is for blocking light leak region.The region that dotted line AA ' and dotted line BB ' define is that TFT regions (or is called the non-display area of pixel cell, referred to as non-display area), dotted line BB ' and dotted line CC ' institute delimited area are the viewing area (referred to as viewing area) of pixel cell.
In prior art, to arrange with layer due to described metal level 11 and grid 10 and adopt identical making material, material therefor is generally Cr, W, Ti, Ta, Mo, Al, the metals such as Cu and alloy thereof, the resistance of common electrode layer 20 can be reduced to a certain extent after making metal level 11 in parallel with common electrode layer 20, but the restriction of the width d1 due to the black matrix 80 on color membrane substrates, and in order to prevent metal level 11 and grid 10 to be short-circuited, interval between described metal level 11 and grid 10 is about 5 microns (um), so the width d2 of described metal level 11 is very limited, thus not clearly to reducing the resistance effect of common electrode layer 20, but, the mode reducing the resistance of common electrode layer 20 by increasing d2 length then can cause d2 to enter into BB '-CC ' inside, pixel aperture ratio is caused to reduce.
Summary of the invention
Embodiments provide a kind of array base palte and preparation method thereof and display floater, in order to reduce the voltage differences of common electrode layer between different pixels unit, increase the aperture opening ratio of pixel simultaneously.
The array base palte that the embodiment of the present invention provides comprises: underlay substrate, the grid line of arranged crosswise, data wire and the pixel cell arranged in matrix that marked off by described grid line and data wire on described underlay substrate, thin-film transistor, pixel electrode and common electrode layer is provided with in described pixel cell, described thin-film transistor comprises grid, the first insulating barrier, active layer, source electrode and drain electrode, and described array base palte also comprises:
Be arranged on the black matrix with electric conductivity of the non-display area of pixel cell, described black matrix is electrically connected with described common electrode layer; And,
For the second insulating barrier by described black matrix and common electrode layer and described film crystal pipe insulation, the overlay area of described second insulating barrier and the covering area overlapping of described black matrix and described common electrode layer.
In described array base palte, be provided with the black matrix of conduction, described black matrix and common electrode layer electrical connection, the resistance of black matrix of electrical connections and the resistor coupled in parallel of common electrode layer, the all-in resistance after parallel connection is made to be less than the resistance of described common electrode layer, effectively reduce the resistance value of common electrode layer, thus reduce the voltage differences of common electrode layer between different pixels unit; Simultaneously, because described black arranged in matrix is on array base palte, do not need to consider box trueness error, and, the second insulation is provided with layer by layer, for insulating, described grid and described black matrix and public electrode so do not need to arrange larger spacing distance between public electrode and grid in this array base palte, the width of the black matrix therefore in described array base palte diminishes compared with the width of matrix black in prior art, is conducive to the aperture opening ratio improving pixel cell.
Preferably, described black arranged in matrix is between thin-film transistor and underlay substrate, and described second insulating barrier is arranged between thin-film transistor and black matrix, effectively can stop that the illumination of backlight is mapped to active layer, is conducive to the dark current reduced in thin-film transistor.In addition, described black matrix can also be arranged on the top of thin-film transistor, and described second insulating barrier is arranged between described black matrix and described thin-film transistor.
Preferably, the material of described black matrix is non-transparent metals material; The black matrix that described non-transparent metals material makes can have conducting function and shade function simultaneously, and the resistance of metal material is much smaller than the resistance of the transparent conductive material for making common electrode layer, after the two parallel connection, make the parallel resistance after parallel connection much smaller than the resistance of described common electrode layer, the voltage differences caused by the resistance value of common electrode layer can be effectively reduced.
Preferably, described black matrix is positioned at the top of described common electrode layer, or described black matrix is positioned at the below of described common electrode layer, makes described black matrix and the electrical connection of described common electrode layer.
Preferably, described black matrix and the overlay area of the electrical connections of described common electrode layer and the overlay area of described grid not overlapping, form coupling capacitance for preventing between described common electrode layer and grid, in order to avoid impact the performance of thin-film transistor.
Preferably, described array base palte also comprises passivation layer, and described passivation layer is arranged on the top of described thin-film transistor place layer, covers the upper area of described thin-film transistor and pixel electrode, and described passivation layer is not corroded mainly for the protection of thin-film transistor.
Preferably, described second insulating barrier is formed with described grid, described first insulating barrier, described active layer, described source electrode and drain electrode and described pixel electrode successively;
Or, described second insulating barrier is formed successively described source electrode and drain electrode and described pixel electrode, described in have edge layer, described first insulating barrier, described grid;
In described array base palte, source electrode, drain electrode and pixel electrode are set with layer, described drain electrode and pixel electrode are directly electrically connected, be conducive to reducing manufacture craft.
Embodiments provide a kind of display unit, described display unit comprises above-mentioned array base palte.
The embodiment of the present invention provides a kind of preparation method of array base palte, and described preparation method comprises:
Underlay substrate is formed the figure of the black matrix comprising common electrode layer and have electric conductivity, and described black matrix is electrically connected with described common electrode layer, and described black arranged in matrix is at the non-display area of pixel cell;
Underlay substrate forms the second insulating barrier, the overlay area of described second insulating barrier and the covering area overlapping of described black matrix and described common electrode layer, for by described black matrix and common electrode layer and described film crystal pipe insulation;
Underlay substrate is formed the figure comprising thin-film transistor and pixel electrode.
In the array base palte utilizing described method to prepare, comprise the black matrix with electric conductivity be arranged on above underlay substrate, described black matrix is electrically connected with described common electrode layer, the resistance of black matrix of electrical connections and the resistor coupled in parallel of common electrode layer, the all-in resistance after parallel connection is made to be less than the resistance of described common electrode layer, effectively reduce the resistance value of common electrode layer, thus reduce the voltage differences of common electrode layer between different pixels unit; Simultaneously, because described black arranged in matrix is on array base palte, do not need to consider box trueness error, and, the second insulating barrier is provided with, for insulating, described grid and described black matrix and public electrode so do not need to arrange larger spacing distance between public electrode and grid in this array base palte, therefore the width of described black matrix diminishes compared with the width of matrix black in prior art, is conducive to the aperture opening ratio improving pixel cell.
Preferably, described black arranged in matrix is between thin-film transistor and underlay substrate, and described second insulating barrier is arranged between thin-film transistor and black matrix, and described formation on underlay substrate comprises the figure of black matrix and common electrode layer, specifically comprises:
Described underlay substrate is formed the figure comprising black matrix; The figure comprising common electrode layer is formed above the described figure comprising black matrix;
Or, described underlay substrate is formed the figure comprising common electrode layer; The figure comprising black matrix is formed above the described figure comprising common electrode layer;
Wherein, the non-display area of described black each pixel cell of Matrix cover.
Comprise in the process of the figure of black matrix and common electrode layer in formation, both can first form black matrix, and also first can form common electrode layer, as long as ensure that black matrix and common electrode layer are electrically connected; Wherein, the non-display area of described black each pixel cell of Matrix cover, for prevent light in non-display area through, be conducive to reducing the dark current in thin-film transistor.
Preferably, underlay substrate is formed the figure comprising thin-film transistor and pixel electrode, specifically comprises:
The top of described second insulating barrier forms the figure comprising grid and grid line;
The first insulating barrier is formed above the described figure comprising grid and grid line;
The figure including active layer is formed above described first insulating barrier;
The figure comprising source electrode, drain electrode and pixel electrode is formed above the described figure including active layer.
Or, above described second insulating barrier, form the figure comprising thin-film transistor and pixel electrode, specifically comprise:
The top of described second insulating barrier forms the figure comprising source electrode, drain electrode and pixel electrode;
The figure including active layer is formed above the described figure comprising source electrode, drain electrode and pixel electrode;
The first insulating barrier is formed above the described figure including active layer;
The figure comprising grid and grid line is formed above described first insulating barrier.
In the process forming described thin-film transistor and pixel electrode, form the figure comprising source electrode, drain electrode and pixel electrode with layer, described drain electrode and pixel electrode are directly electrically connected, are conducive to reducing manufacture craft.
Preferably, described method also comprises: above the described figure comprising thin-film transistor and pixel electrode, form passivation layer, described passivation layer covers the upper area of described thin-film transistor and pixel electrode, is corroded for preventing thin-film transistor.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of a kind of display floater of the prior art;
The planar structure schematic diagram that Fig. 2 is display floater shown in Fig. 1;
Fig. 3 is the plane structure chart of pixel electrode;
The cross-sectional view of a kind of array base palte that Fig. 4 provides for the embodiment of the present invention one;
The planar structure schematic diagram that Fig. 5 is the array base palte shown in Fig. 4;
The cross-sectional view of a kind of array base palte that Fig. 6 provides for the embodiment of the present invention two;
The cross-sectional view of a kind of array base palte that Fig. 7 provides for the embodiment of the present invention three;
The cross-sectional view of a kind of array base palte that Fig. 8 provides for the embodiment of the present invention four;
Fig. 9 has been the cross-sectional view of the array base palte that black matrix and common electrode layer make;
Figure 10 has been the cross-sectional view of the array base palte that the second insulating barrier makes;
Figure 11 has been the cross-sectional view of the array base palte that thin-film transistor makes;
Figure 12 has been the cross-sectional view of the array base palte that pixel electrode makes;
Figure 13, in the process preparing the array base palte that embodiment two provides, completes the cross-sectional view of the array base palte after black matrix and common electrode layer making.
Embodiment
Embodiments provide a kind of array base palte and preparation method thereof and display floater, in order to reduce the voltage differences of common electrode layer between different pixels unit, increase the aperture opening ratio of pixel simultaneously.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention one provides a kind of array base palte, see Fig. 4 and Fig. 5, and the wherein cross-sectional view of array base palte that provides for the embodiment of the present invention one of Fig. 4, the planar structure schematic diagram that Fig. 5 is array base palte shown in Fig. 4.Composition graphs 4 and Fig. 5, can find out that described array base palte comprises: underlay substrate 1001, black matrix 80, common electrode layer 20, second insulating barrier 90, grid 10, grid line 12, first insulating barrier 30, active layer 40, data line layer 50(specifically comprise: data wire 501, source electrode 502, drain electrode 503) and pixel electrode 60;
Concrete, described black matrix 80 is positioned at the top of described underlay substrate 1001, the material of described black matrix is non-transparent metals material, the black matrix that described employing non-transparent metals material makes can have conducting function and shade function simultaneously, and the resistance of metal material is much smaller than the resistance for utilizing other nontransparent electric conducting material.
The width of described black matrix 80 is d3, and it covers the non-display area of each pixel cell, for prevent light in non-display area through; Because described black matrix 80 is arranged on array base palte, therefore when designing black matrix 80, not needing to consider box trueness error, being conducive to the size reducing black matrix, improving the aperture opening ratio of pixel;
In addition, described black matrix 80 can also cover the channel region of active layer 40, and the light being irradiated to active layer 40 is all covered, and then reduces the leakage current of active layer.
Described common electrode layer 20 is positioned at the top of described black matrix 80 place layer, and is electrically connected with described black matrix 80, and the material of described common electrode layer 20 is generally the transparent oxides such as tin indium oxide, indium zinc oxide or aluminum zinc oxide.
Described black matrix 80 is d4 with the width of the electrical connections of described common electrode layer 20, the overlay area of described electrical connections is not overlapping with the overlay area of described grid 10, coupling capacitance is formed between described common electrode layer 20 and grid 10, in order to avoid affect the performance of thin-film transistor for preventing.The overlay area of indication refers to dependency structure (electrical connections of such as described black matrix and described common electrode layer or the grid) view field on underlay substrate herein.
At the electrical connections of described black matrix 80 with described common electrode layer 20, the resistance of the black matrix of electrical connections and the resistor coupled in parallel of described common electrode layer 20, because the resistance value of described electrical connections is much smaller than the resistance of described common electrode layer 20, therefore, the resistance of the all-in resistance after parallel connection much smaller than the resistance of described common electrode layer 20, and then makes the voltage differences caused by the resistance of common electrode layer 20 reduce.
Described second insulating barrier 90, be arranged on described common electrode layer 20 place layer and described grid 10 and grid line 12 institute between layers, the overlay area of described second insulating barrier and the covering area overlapping of described black matrix and described common electrode layer, namely described second insulating barrier covers the upper area of described black matrix 80 and described common electrode layer 20, for being insulated with described black matrix 80 and described common electrode layer 20 by the grid 10 of described thin-film transistor.Therefore, in this array base palte, do not need to consider the spacing distance between common electrode layer 20 and grid line 10.Be conducive to the size reducing black matrix further, improve the aperture opening ratio of pixel.
Described grid 10 is arranged with layer with grid line 12, all between described first insulating barrier 30 and the second insulating barrier 90, and described grid 10 adopts identical making material with described grid line 12, making material used is generally the non-transparent metals such as Cr, W, Ti, Ta, Mo, Al, Cu and alloy thereof.
Described first insulating barrier 30 is positioned at described grid 10 and the top of grid line 12, covers the upper area of described grid 10 and grid line 12; In the present embodiment, the making material of described first insulating barrier 30 is photoresist, and its thickness is about 20000 Ethylmercurichlorendimides, and meanwhile, described first insulating barrier 30 can also with other insulating layer material, and thickness should be determined according to actual needs.
Described active layer 40 is positioned at the top of described first insulating barrier 30;
Described data wire 501, source electrode 502 and drain electrode 503 are arranged with layer, are positioned at the top of described active layer 40 place layer, and adopt identical material to make;
Described data wire 501 is electrically connected with described source electrode 502, and arranged in a crossed manner with grid line 12;
Described source electrode 502 is positioned at the relative both sides above described active layer 40 with drain electrode 503.
Described pixel electrode 60 and described data wire 501, source electrode 502, draining 503 is arranged with layer, and described pixel electrode 60 is electrically connected with described drain electrode 503, described pixel electrode generally adopts the transparent oxide material such as tin indium oxide, indium zinc oxide or aluminum zinc oxide to make, and described pixel electrode is slit-shaped.
Described array base palte also comprises the passivation layer 70 be positioned at above described data wire 501, source electrode 502 and drain electrode 503, and described passivation layer 70 is not corroded for the protection of thin-film transistor; Described passivation layer 70 adopts the transparent insulation material such as silicon nitride or silica to be formed.
In order to better explain the impact of present design on the aperture opening ratio of thin-film transistor pixel and grid line and data wire, to be now described for the pixel cell in the display floater shown in Fig. 2 and the pixel cell in the array base palte shown in Fig. 5:
Fig. 2 is the pixel cell structure schematic diagram in the display floater designed in prior art, and material and the thickness data of concrete each layer film refer to table 1;
The material of each layer film and thickness data in table 1 prior art
Pixel cell planar structure schematic diagram in the array base palte that Fig. 5 provides for the embodiment of the present invention one, material and the thickness data of concrete each layer film refer to table 2;
The material of each layer film and thickness data in the array base palte that table 2 embodiment of the present invention one provides
Further, Fig. 2 and Fig. 5 is the dot structure figure that resolution is 480 × 272 5.2 inches, and pixel cell size is 80 × 240um, and grid line 12 live width is 6um, and data wire 501 live width is 4um.
As calculated, the grid line resistance of each pixel cell and the resistance of data wire 501 of above-mentioned two kinds of designs can not change, in structure pixel cell as shown in Figure 2, and grid line electric capacity C
gate=5.91 × 10
-14f, data line capacitance C
data=9.56 × 10
-14f, supposes that its picture scanning frequency is 60Hz, and when pixel charge rate is 99.99%, then in described pixel cell, the width of thin-film transistor and length need to be designed to 16um and 5um respectively;
Suppose that the Anawgy accuracy of array base palte and color membrane substrates is 7.5um, then in structure pixel cell as described in Figure 5, grid line electric capacity C
gate=3.72 × 10
-13f, data line capacitance C
data=2.19 × 10
-13f, is 60Hz in picture scanning frequency, and when pixel charge rate is 99.99%, the width of the thin-film transistor in this pixel cell and length need to be designed to 17um and 5um respectively.
In sum, due to the introducing of black matrix in the pixel cell described in Fig. 5, the grid line electric capacity of each pixel cell can be caused by original 5.91 × 10
-14f increases to 3.72 × 10
-13f, the data line capacitance of each pixel cell is by original 9.56 × 10
-14f increases to 2.19 × 10
-13f, and the increase of electric capacity can cause the delay of grid line and data wire to increase, and then cause the charging interval of each pixel cell to reduce, need to increase charging current for this reason, therefore, in the array base palte that embodiment one provides, need the width of thin-film transistor, length to need to be designed to 17um, 5um respectively and be used for increasing charging current, to ensure the normal display of pixel cell.Although the introducing of described black matrix can increase the electric capacity of grid line and data wire, and then cause the width of thin-film transistor to increase (aperture opening ratio can be caused to reduce), but because black matrix in parallel with common electrode layer in this pixel cell and grid line layer are that non-same layer designs, do not need to arrange larger interval between black matrix and grid line layer, and do not need to consider box trueness error, therefore the aperture opening ratio of pixel cell increases as a complete unit, and the aperture opening ratio of whole pixel increases to 75.5% by original 72%.
The embodiment of the present invention two additionally provides a kind of array base palte, its cross-section structure as shown in Figure 6, as can be seen from Figure 6, the structure of the array base palte shown in this array base palte with Fig. 4 is substantially identical, both difference parts are: in the array base palte shown in Fig. 4, and black matrix 80 is between underlay substrate 1001 and described common electrode layer 20; And in the array base palte shown in Fig. 6, black matrix 80 is between the second insulating barrier 90 and described common electrode layer 20.
The embodiment of the present invention three additionally provides a kind of array base palte, its cross-section structure as shown in Figure 7, as can be seen from 7, the structure of the array base palte shown in this array base palte with Fig. 4 is substantially identical, both difference parts are: the array base palte shown in Fig. 4 is the array base palte of bottom grating structure, and the array base palte shown in Fig. 7 is the array base palte of top gate structure, concrete, in array base palte shown in Fig. 7, described data wire 501, the top being positioned at described second insulating barrier 90 of source electrode 502 and drain electrode 503, data wire 501 is comprised described in described active layer 40 is positioned at, the top of the figure of source electrode 502 and drain electrode 503, described first insulating barrier 30 is positioned at the top of described active layer 40, described grid 10 and grid line 12 are positioned at the top of described first insulating barrier 30.Further, because described pixel electrode 60 and described data wire 501, source electrode 502 and draining 503 is arranged with layer, therefore in the array base palte shown in Fig. 7, described pixel electrode 60 to be arranged between described first insulating barrier 30 and the second insulating barrier 90.
The embodiment of the present invention four additionally provides a kind of array base palte, its cross-section structure as shown in Figure 8, as can be seen from Figure 8, described array base palte is substantially identical with the structure of the array base palte shown in Fig. 7, both differences are: in the array base palte shown in Fig. 7, and black matrix 80 is between underlay substrate 1001 and described common electrode layer 20; And in the array base palte shown in Fig. 8, black matrix 80 is between the second insulating barrier 90 and described common electrode layer 20.
In the array base palte that above-described embodiment one, embodiment two, embodiment three and embodiment four provide, include the black matrix with conductivity be arranged on above underlay substrate, described black matrix and common electrode layer electrical connection, the resistance of black matrix of electrical connections and the resistor coupled in parallel of common electrode layer, the all-in resistance of the electrical connections after parallel connection is made to be less than the resistance of the common electrode layer of this electrical connections, effectively reduce the resistance value of common electrode layer, thus reduce the voltage differences of common electrode layer between different pixels unit; Meanwhile, because described black arranged in matrix is on array base palte, does not need to consider box trueness error, be conducive to the width dimensions reducing black matrix, improve the aperture opening ratio of pixel; Simultaneously, the second insulation is also provided with layer by layer in this array base palte, for described grid and described black matrix and public electrode are insulated, so do not need to arrange larger spacing distance for preventing grid and common electrode layer short circuit between common electrode layer and grid, be conducive to the size reducing black matrix further, improve the aperture opening ratio of pixel.
Be pointed out that, described black matrix can also be arranged on the top of thin-film transistor, concrete, described second insulating barrier is arranged on the top of film crystal, described black arranged in matrix is above the second insulating barrier, described common electrode layer is arranged on the top/below of described black matrix and is electrically connected with black matrix, described passivation layer is arranged on the top of described common electrode layer and black matrix, described pixel electrode is arranged on the top of described passivation layer, wherein, described pixel electrode is slit-shaped, and described public electrode is tabular or slit-shaped;
Or, described second insulating barrier is arranged on the top of thin-film transistor, described pixel electrode is arranged on the below of the second insulating barrier, described common electrode layer is arranged on the top of thin-film transistor, described black arranged in matrix is above the second insulating barrier, above or below common electrode layer, and be electrically connected with described common electrode layer, described passivation layer is arranged on the top of described black matrix and common electrode layer; Wherein, described public electrode is slit-shaped, and described pixel electrode is tabular or slit-shaped.
The preparation method of a kind of array base palte that the embodiment of the present invention five provides, described method comprises:
Underlay substrate is formed the figure of the black matrix comprising common electrode layer and have electric conductivity, and described black matrix is electrically connected with described common electrode layer, and described black arranged in matrix is at the non-display area of pixel cell;
Underlay substrate forms the second insulating barrier, the overlay area of described second insulating barrier and the covering area overlapping of described black matrix and described common electrode layer, for by described black matrix and common electrode layer and film crystal pipe insulation;
Underlay substrate is formed the figure comprising thin-film transistor and pixel electrode.
In the array base palte utilizing described method to prepare, comprise the black matrix with electric conductivity be arranged on above underlay substrate, described black matrix is electrically connected with described common electrode layer, the resistance of black matrix of electrical connections and the resistor coupled in parallel of common electrode layer, the all-in resistance after parallel connection is made to be less than the resistance of described common electrode layer, effectively reduce the resistance value of common electrode layer, thus reduce the voltage differences of common electrode layer between different pixels unit; Simultaneously, because described black arranged in matrix is on array base palte, do not need to consider box trueness error, and, the second insulation is provided with layer by layer, for insulating, described grid and described black matrix and public electrode so do not need to arrange larger spacing distance between public electrode and grid in this array base palte, therefore the width of described black matrix diminishes compared with the width of matrix black in prior art, is conducive to the aperture opening ratio improving pixel cell.
Below for the array base palte that the embodiment of the present invention one provides, introduce in actual preparation technology in detail, the preparation method of described array base palte, the method specifically comprises:
The first step, see Fig. 9, underlay substrate 1001 forms the figure comprising black matrix 80 and common electrode layer 20; Concrete, this step comprises:
Underlay substrate 1001 deposits the nontransparent metallic film of one deck, and then by patterning processes process, form the figure comprising black matrix 80, described black matrix 80 covers the non-display area of each pixel cell; Wherein, in the present embodiment, described patterning processes comprises: first, and underlay substrate 1001 is formed the nontransparent metallic film of (as sputtering or coating etc.) one deck for the formation of black matrix; Then, metallic film applies one deck photoresist; Then, with the mask plate being provided with the figure comprising black matrix, photoresist is exposed; The figure comprising black matrix 80 is formed finally by after development, etching.In the preparation method of the present embodiment array base palte, the preparation technology relating to the rete formed by patterning processes is identical therewith, is after this no longer described in detail.
Above the described figure comprising black matrix 80, use magnetron sputtering method deposition indium oxide layer tin transparent conductive film, and by patterning processes, form the figure comprising common electrode layer 20; Described common electrode layer 20 is electrically connected with described black matrix, the width of its electrical connections is d4, owing to not needing to consider the interval between common electrode layer and grid, therefore the width d4 of this electrical connections is greater than the width d2 of the electrical connections of metal level and public electrode wire in prior art.
Second step, see Figure 10, at the described disposed thereon silicon nitride (SiN comprising the figure of black matrix 80 and common electrode layer 20
x) or silica (SiO
x) layer, form the second insulating barrier 90, described second gate insulating barrier 90 for covering the upper area of described black matrix 80 and common electrode layer 20, for by described black matrix 80 and common electrode layer 20 and film crystal pipe insulation.
3rd step, see Figure 11, above described second insulating barrier 90, form the figure comprising thin-film transistor, this step specifically comprises:
One, the disposed thereon of described second insulating barrier 90 deposits layer of metal film, then by patterning processes process, formation comprises grid 10 and grid line 12(is shown in Fig. 5) figure, the described material for the formation of metallic film is non-transparent metals and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu;
Two, at the described disposed thereon silicon nitride (SiN comprising the figure of grid 10 and grid line 12
x) or silica (SiO
x) layer, form the first insulating barrier 30, described first grid insulating barrier 30 for covering the upper area of described grid line and grid, for grid line and grid and other layer are insulated;
Three, at the disposed thereon amorphous silicon semiconductor material of described first insulating barrier 30, then formed the figure including active layer 40 by patterning processes;
Four, above the described figure including active layer 40, form source and drain metallic film, then by patterning processes, form the figure comprising data wire 501, source electrode 502 and drain electrode 503.
4th step, see Figure 12, above described first insulating barrier 30, use magnetron sputtering method to deposit indium oxide layer tin transparent conductive film, and pass through patterning processes, form the figure comprising pixel electrode 60, described pixel electrode 60 and described data wire 501, source electrode 502, draining 503 is arranged with layer, and described pixel electrode 60 is electrically connected with described drain electrode 503.
5th step, see Fig. 4, at described the disposed thereon silicon nitride or the silicon oxide layer that comprise the figure of pixel electrode, forms passivation layer 70, is not corroded for the protection of thin-film transistor.
Through above-mentioned steps, namely form the embodiment of the present invention one provides, structure array base palte as shown in Figure 4.
It is noted that prepare in the process of array base palte above-mentioned, after can first forming thin-film transistor, form pixel electrode again, after also can first forming pixel electrode, form thin-film transistor again.
For the array base palte that the embodiment of the present invention two provides, its preparation method is similar with the method for the array base palte that the preparation embodiment of the present invention one provides, difference is, see Figure 13, in the process making the array base palte that the embodiment of the present invention two provides, described formation on underlay substrate comprises the figure of black matrix and common electrode layer, specifically comprises:
1), underlay substrate 1001 uses magnetron sputtering method deposit indium oxide layer tin transparent conductive film, and by patterning processes, form the figure comprising common electrode layer 20;
2), at the described nontransparent metallic film of disposed thereon one deck comprising the figure of common electrode layer 20, then by patterning processes process, form the figure comprising black matrix 80, described black matrix 80 covers the non-display area of each pixel cell;
Wherein, described common electrode layer 20 is electrically connected with described black matrix, the width of its electrical connections is d4, owing to not needing to consider the interval between common electrode layer and grid, therefore the width d4 of this electrical connections is greater than the width d2 of the electrical connections of metal level and public electrode wire in prior art; .
For the array base palte that the embodiment of the present invention three provides, its preparation method is similar with the method for the array base palte that the preparation embodiment of the present invention one provides, difference is, see Fig. 7, in the process making the array base palte that the embodiment of the present invention three provides, described formation comprises the figure of thin-film transistor and pixel electrode, specifically comprises:
A), the top of described second insulating barrier 90 forms source and drain metallic film, then by patterning processes, forms the figure comprising data wire 501, source electrode 502 and drain electrode 503;
B), above described second insulating barrier 90, use magnetron sputtering method to deposit indium oxide layer tin transparent conductive film, and pass through patterning processes, form the figure comprising pixel electrode 60, described pixel electrode 60 and described data wire 501, source electrode 502, draining 503 is arranged with layer, and described pixel electrode 60 is electrically connected with described drain electrode 503;
C), at the described disposed thereon semi-conducting material of figure comprising data wire 501, source electrode 502 and drain electrode 503, the figure including active layer 40 is then formed by patterning processes;
D), at described the disposed thereon silicon nitride or the silicon oxide layer that include the figure of active layer 40, form the first insulating barrier 30, described first grid insulating barrier 30 for covering the upper area of described active layer 40, for described active layer 40 and other layer are insulated;
E), at the disposed thereon layer of metal film of described first insulating barrier 30, then by patterning processes process, formed and comprise grid 10 and grid line 12(is shown in Fig. 4) figure, the described material for the formation of metallic film is non-transparent metals and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu.
For the array base palte that the embodiment of the present invention four provides, its preparation method is similar with the method for the array base palte that the preparation embodiment of the present invention three provides, difference is, see Fig. 8, in the process preparing the array base palte that the embodiment of the present invention four provides, described formation on underlay substrate comprises the figure of black matrix and common electrode layer, specifically comprises:
1), underlay substrate 1001 uses magnetron sputtering method deposit indium oxide layer tin transparent conductive film, and by patterning processes, form the figure comprising common electrode layer 20;
2), at the described nontransparent metallic film of disposed thereon one deck comprising the figure of common electrode layer 20, then by patterning processes process, form the figure comprising black matrix 80, described black matrix 80 covers the non-display area of each pixel cell;
Wherein, described common electrode layer 20 is electrically connected with described black matrix, the width of its electrical connections is d4, owing to not needing to consider the interval between common electrode layer and grid, therefore the width d4 of this electrical connections is greater than the width d2 of the electrical connections of metal level and public electrode wire in prior art.
It is noted that in the present invention, described patterning processes, can only include photoetching process, or, comprise photoetching process and etch step, other techniques for the formation of predetermined pattern such as printing, ink-jet can also be comprised simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. that comprise the technical processs such as film forming, exposure, development form the technique of figure.Can according to the structure choice formed in the present invention corresponding patterning processes.
In addition, be all arranged on the array base palte above thin-film transistor for black matrix, common electrode layer and the second insulating barrier, its manufacture method comprises:
Underlay substrate is formed the figure comprising thin-film transistor, the second insulating barrier and the figure comprising common electrode layer and black matrix is formed successively above the described figure comprising thin-film transistor, passivation layer is formed above the described figure comprising common electrode layer and black matrix, the figure comprising pixel electrode is formed above described passivation layer, wherein, pixel electrode is slit-shaped, and described common electrode layer is tabular or slit-shaped;
Or, underlay substrate is formed the figure comprising thin-film transistor, the figure and the second insulating barrier that comprise pixel electrode is formed successively above the described figure comprising thin-film transistor, the figure comprising common electrode layer and black matrix is formed above described second insulating barrier, passivation layer is formed, wherein, wherein above the described figure comprising common electrode layer and black matrix, pixel electrode is slit-shaped or tabular, and described common electrode layer is slit-shaped.
To sum up, in the array base palte that the embodiment of the present invention provides, comprise the black matrix with conductivity be arranged on above underlay substrate, described black matrix and common electrode layer electrical connection, the resistance of black matrix of electrical connections and the resistor coupled in parallel of common electrode layer, make the all-in resistance of the electrical connections after parallel connection be less than the resistance of the common electrode layer of this electrical connections, effectively reduce the resistance value of common electrode layer, thus reduce the voltage differences of common electrode layer between different pixels unit; Meanwhile, because described black arranged in matrix is on array base palte, does not need to consider box trueness error, be conducive to the width dimensions reducing black matrix, improve the aperture opening ratio of pixel; Simultaneously, the second insulation is also provided with layer by layer in this array base palte, for described grid and described black matrix and public electrode are insulated, so do not need to arrange larger spacing distance for preventing grid and common electrode layer short circuit between common electrode layer and grid, be conducive to the size reducing black matrix further, improve the aperture opening ratio of pixel.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (13)
1. an array base palte, described array base palte comprises underlay substrate, the grid line of arranged crosswise, data wire and the pixel cell arranged in matrix that marked off by described grid line and data wire on described underlay substrate, thin-film transistor, pixel electrode and tabular common electrode layer is provided with in described pixel cell, described thin-film transistor comprises grid, the first insulating barrier, active layer, source electrode and drain electrode, it is characterized in that, described array base palte also comprises:
Be arranged on the black matrix with electric conductivity of the non-display area of pixel cell, described black matrix is electrically connected with described common electrode layer, the resistance of black matrix of electrical connections and the resistor coupled in parallel of common electrode layer; And,
For the second insulating barrier by described black matrix and common electrode layer and described film crystal pipe insulation, the overlay area of described second insulating barrier and the covering area overlapping of described black matrix and described common electrode layer;
Wherein, described black arranged in matrix is between described thin-film transistor and described underlay substrate, and described second insulating barrier is arranged between described thin-film transistor and described black matrix.
2. array base palte as claimed in claim 1, it is characterized in that, the material of described black matrix is non-transparent metals material.
3. array base palte as claimed in claim 1, it is characterized in that, described black matrix is positioned at the top of described common electrode layer, or described black matrix is positioned at the below of described common electrode layer.
4. array base palte as claimed in claim 1, is characterized in that, described black matrix and the overlay area of the electrical connections of described common electrode layer and the overlay area of described grid not overlapping.
5. array base palte as claimed in claim 1, it is characterized in that, described array base palte also comprises passivation layer, and described passivation layer is arranged on the top of described thin-film transistor place layer, covers the upper area of described thin-film transistor and pixel electrode.
6. array base palte as claimed in claim 5, is characterized in that, described second insulating barrier is formed described grid, described first insulating barrier, described active layer, described source electrode and drain electrode and described pixel electrode successively.
7. array base palte as claimed in claim 5, is characterized in that, described second insulating barrier is formed described source electrode and drain electrode and described pixel electrode, described active layer, described first insulating barrier, described grid successively.
8. a display unit, is characterized in that, described display unit comprises the arbitrary described array base palte of claim 1 ~ 7.
9. a preparation method for array base palte, is characterized in that, described preparation method comprises:
Underlay substrate is formed the figure of the black matrix comprising tabular common electrode layer and have electric conductivity, described black matrix is electrically connected with described common electrode layer, the resistance of black matrix of electrical connections and the resistor coupled in parallel of common electrode layer, described black arranged in matrix is at the non-display area of pixel cell;
Underlay substrate is formed the second insulating barrier;
Underlay substrate is formed the figure comprising thin-film transistor and pixel electrode;
Wherein, the overlay area of described second insulating barrier and the covering area overlapping of described black matrix and described common electrode layer, for by described black matrix and common electrode layer and described film crystal pipe insulation; Described black arranged in matrix is between described thin-film transistor and described underlay substrate, and described second insulating barrier is arranged between described thin-film transistor and described black matrix.
10. preparation method as claimed in claim 9, is characterized in that, describedly on underlay substrate, forms the figure comprising black matrix and common electrode layer, specifically comprises:
Described underlay substrate is formed the figure comprising black matrix; The figure comprising common electrode layer is formed above the described figure comprising black matrix;
Or, described underlay substrate is formed the figure comprising common electrode layer; The figure comprising black matrix is formed above the described figure comprising common electrode layer;
Wherein, the non-display area of described black each pixel cell of Matrix cover.
11. preparation methods as claimed in claim 10, is characterized in that, underlay substrate is formed the figure comprising thin-film transistor and pixel electrode, specifically comprises:
The top of described second insulating barrier forms the figure comprising grid and grid line;
The first insulating barrier is formed above the described figure comprising grid and grid line;
The figure including active layer is formed above described first insulating barrier;
The figure comprising source electrode, drain electrode and pixel electrode is formed above the described figure including active layer.
12. preparation methods as claimed in claim 10, is characterized in that, underlay substrate is formed the figure comprising thin-film transistor and pixel electrode, specifically comprises:
The top of described second insulating barrier forms the figure comprising source electrode, drain electrode and pixel electrode;
The figure including active layer is formed above the described figure comprising source electrode, drain electrode and pixel electrode;
The first insulating barrier is formed above the described figure including active layer;
The figure comprising grid and grid line is formed above described first insulating barrier.
13. preparation methods as claimed in claim 10, it is characterized in that, described method also comprises:
Above the described figure comprising thin-film transistor and pixel electrode, form passivation layer, described passivation layer covers the upper area of described thin-film transistor and pixel electrode.
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| PCT/CN2013/088834 WO2015027609A1 (en) | 2013-08-28 | 2013-12-09 | Array substrate and manufacturing method therefor, and display device |
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| CN110061013B (en) * | 2019-04-23 | 2021-06-01 | 武汉华星光电技术有限公司 | Array substrate and preparation method thereof |
| EP4002004B1 (en) * | 2019-07-16 | 2024-02-21 | BOE Technology Group Co., Ltd. | Array substrate, display panel, display device and method for manufacturing array substrate |
| CN111539340B (en) * | 2020-04-26 | 2022-08-05 | 厦门天马微电子有限公司 | Display panel, display device and driving method |
| CN111522181B (en) * | 2020-04-27 | 2023-05-05 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and preparation method of display panel |
| CN112379552A (en) * | 2020-12-03 | 2021-02-19 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
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Also Published As
| Publication number | Publication date |
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| CN103474432A (en) | 2013-12-25 |
| WO2015027609A1 (en) | 2015-03-05 |
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