CN111522181B - Array substrate, display panel and preparation method of display panel - Google Patents
Array substrate, display panel and preparation method of display panel Download PDFInfo
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- CN111522181B CN111522181B CN202010344750.6A CN202010344750A CN111522181B CN 111522181 B CN111522181 B CN 111522181B CN 202010344750 A CN202010344750 A CN 202010344750A CN 111522181 B CN111522181 B CN 111522181B
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- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 33
- 230000005540 biological transmission Effects 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000002834 transmittance Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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Abstract
The application discloses an array substrate, a display panel and a preparation method thereof, wherein the array substrate comprises a transparent substrate and a pixel structure arranged on the transparent substrate; the pixel structure includes: scan lines and data lines crossing each other; a pixel region defined by the scan line and the data line crossing each other; a thin film transistor region formed at an intersection of the scan line and the data line; in the pixel region, a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode are sequentially laminated on one side of the transparent substrate; a light transmission part is arranged below the active layer and corresponds to the active layer, and the light transmission part is used for transmitting light to irradiate the active layer. Compared with the pixel structure in which the active layer is completely shielded in the prior art, the pixel structure improves the pixel aperture ratio by 3 to 8 percent, and meanwhile, the problem of capacitance structure change caused by pixel structure change is avoided.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a display panel and a preparation method of the array substrate and the display panel.
Background
The viewing angle and transmittance are key parameters of a liquid crystal display panel (Liquid Crystal Display, LCD) panel. For a vertically aligned (Vertical Alignment, VA) display mode LCD panel, increasing the number of pixel domains (domains) from 4 to 8 can significantly increase the viewing angle. However, at the same time, the voltage difference between two sides of the liquid crystal of the Sub-Pixel in the 8-domain Pixel is smaller, so that the area occupied ratio of the Sub-Pixel is large, and the transmittance of the Sub-Pixel (Sub Pixel) in the Sub-region is obviously lower than that of the Sub-Pixel (Main Pixel) in the Main region. In addition, the driving circuit of the pixel is changed from one TFT (thin film transistor) to three TFTs from 4-domain pixel to 8-domain pixel, so that the occupied area is larger, the light transmission area of the pixel is reduced, and the transmittance of the pixel is further reduced. Thus, increasing the pixel transmittance has been the direction of the development of LCD panels.
The active layer in the pixel region of the 8-domain 3T (8-domain 3 transistor) pixel structure prepared in the prior art generally uses an a-Si material, which is converted from a semiconductor to a conductor under the irradiation of a backlight source, so that the capacitance between the pixel electrode and the share electrode (common electrode) is changed, on one hand, the capacitance structure of the pixel deviates from a design value, and on the other hand, under the irradiation of a scanning backlight source, the capacitance is switched between two states, thereby causing the brightness variation of the pixel and causing abnormality. The metal layer is generally provided to completely shield the active layer from backlight, but this widens the opaque region of the pixel region and further reduces the pixel aperture ratio.
Disclosure of Invention
In order to solve the problems in the prior art, the application aims to provide an array substrate capable of improving the pixel transmittance, a display panel and a preparation method thereof.
The application provides an array substrate, which comprises a transparent substrate and a pixel structure arranged on the transparent substrate; the pixel structure includes:
scan lines and data lines crossing each other;
a pixel region defined by the scan line and the data line crossing each other;
a thin film transistor region formed at an intersection of the scan line and the data line;
in the pixel region, a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode are sequentially laminated on one side of the transparent substrate;
a light transmission part is arranged below the active layer and corresponds to the active layer, and the light transmission part is used for transmitting light to irradiate the active layer.
In some embodiments, the first metal layer includes a common electrode, and a through hole is formed in the first metal layer in the light-transmitting portion, where the through hole corresponds to an orthographic projection of the active layer on the first metal layer.
In some embodiments, the light transmitting portion extends from one end to the other end of the pixel region.
In some embodiments, the width of the light-transmitting portion is greater than or equal to the width of the active layer.
In some embodiments, the width of the pixel electrode is less than or equal to the width of the active layer.
In some embodiments, the active layer has light stability.
In some embodiments, the active layer has a forbidden bandwidth greater than 3eV.
In some embodiments, the thin film transistor region is provided with a main region thin film transistor, a sub region thin film transistor, and a sharing thin film transistor, the second metal layer includes a source or a drain of the sharing thin film transistor, and the light transmitting part is provided corresponding to the source and/or the drain.
The application also provides a display panel comprising the array substrate as described in any one of the above.
The application also provides a preparation method of the array substrate, which comprises the following steps:
providing a transparent substrate; forming scanning lines and data lines on the transparent substrate, wherein the scanning lines and the data lines cross each other to define a pixel region;
sequentially stacking a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode on the transparent substrate, and forming a thin film transistor region at the intersection of the scanning line and the data line;
and forming a light transmission part below the active layer and corresponding to the active layer, wherein the light transmission part is used for transmitting light to irradiate the active layer.
Compared with the pixel structure in which the active layer is completely shielded in the prior art, the pixel structure improves the pixel aperture ratio by 3 to 8 percent, and meanwhile, the problem of capacitance structure change caused by pixel structure change is avoided.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a plan view showing an array substrate of the present application.
Fig. 2 is a schematic cross-sectional view illustrating the array substrate of fig. 1 along A-A'.
Fig. 3 is a schematic structural diagram of a display panel of the present application.
Fig. 4 is a schematic flow chart showing a preparation method of the array substrate of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
Specifically, please refer to fig. 1, which is a schematic top view of an array substrate provided in the present application. The embodiment of the application provides an array substrate, which comprises a transparent substrate 10 and a pixel structure arranged on the transparent substrate 10; the pixel structure includes: a scanning line 21 and a data line 22 crossing each other; a pixel region 23 defined by the scan line 21 and the data line 22 crossing each other; a thin film transistor region 24 formed at the intersection of the scan line 21 and the data line 22; the thin film transistor region 24 includes a main region thin film transistor, a sub region thin film transistor, and a shared thin film transistor 241. An opaque region 230 is disposed in the pixel region 23, and the opaque region 230 extends from one end of the pixel region 23 to the other end.
Fig. 2 is a schematic cross-sectional view illustrating the pixel region of fig. 1 at the opaque region A-A', and referring to fig. 1 and 2, one side of the transparent substrate 10 is sequentially laminated with a first metal layer, a first insulating layer 231, an active layer 232, a second metal layer 233, a second insulating layer 234, and a pixel electrode 235; the first metal layer includes a common electrode and a gate electrode of the thin film transistor region 24, the first insulating layer 231 is a gate insulating layer for insulating and separating the active layer 232 from the first metal layer, the second metal layer 233 includes a source/drain electrode of the thin film transistor region 24, a common electrode (share electrode) sharing the source or drain electrode of the thin film transistor 241, and the second insulating layer 234 covers the active layer 232 and planarizes the pixel region 23. A light-transmitting portion 236 is disposed below the active layer 232 and corresponding to the active layer 232, and the light-transmitting portion 236 is used for transmitting light to the active layer 232.
A through hole is formed in the first metal layer in the light-transmitting portion 236, and the through hole corresponds to the orthographic projection of the active layer 232 on the first metal layer.
The light transmitting portion 236 extends from one end to the other end of the pixel region 23.
The width of the light transmitting portion 236 is greater than or equal to the width of the active layer 232.
The width of the pixel electrode 235 is less than or equal to the width of the active layer 232.
In the prior art, the first metal layer generally includes a light shielding portion disposed below the active layer 232 and corresponding to the active layer 232, in order to completely shield the active layer 232, the width of the light shielding portion is greater than the width of the active layer 232, the width of the opaque region 230 is defined by the width of the light shielding portion, the light shielding portion of the first metal layer is removed to form a light transmitting portion, then the width of the opaque region 230 is defined by the width d1 of the pixel electrode 235, the width of the opaque region 230 is reduced, and the aperture ratio is increased.
To ensure that the capacitance between the pixel electrode 235 and the common electrode (share electrode) does not change, the active layer has light stability. The light stability refers to the property that the physical properties of the active layer 232 are not changed under the irradiation of light, and the active layer is insensitive to the irradiation of light. In some embodiments, the active layer 232 uses a semiconductor material having a forbidden band width greater than 3eV, which does not change from semiconductor to conductor under irradiation of light. In some embodiments, the material of the active layer 232 may be oxide semiconductor InGaZnO, silicon-based nanomaterial, zinc oxide, or the like.
The present application also provides a display panel 200, referring to fig. 3, which is a schematic structural diagram of the display panel 200. The display panel 200 includes an array substrate 100 and a color filter substrate disposed opposite to each other; electrodes are oppositely arranged on the array substrate 200 and the color filter substrate respectively, an alignment film is oppositely attached to the electrodes, and liquid crystal molecules are filled between the array substrate 200 and the color filter substrate.
Another exemplary embodiment of the present application provides a method for preparing the array substrate, referring to fig. 4, which is a schematic flow chart of steps of the method for preparing the array substrate, including the following steps: providing a transparent substrate 10, depositing a first metal layer on the transparent substrate 10, performing photoetching to form a common electrode, and forming the grids of the main area thin film transistor, the secondary area thin film transistor and the shared thin film transistor 241 and the scanning line 21; a through hole is further formed in the first metal layer, and the through hole corresponds to orthographic projection of the active layer 232 on the first metal layer. Depositing a first insulating layer 231 on the first metal layer after the pattern, wherein the first insulating layer 231 covers the through hole, and the first insulating layer 231 is used for forming a gate insulating layer; forming an active layer 232 on the gate insulating layer at a position corresponding to the position of the through hole; depositing a second metal layer 233 on the active layer, and photoetching the second metal layer 233 by a 4Mask process halotone technology to form a common electrode (share electrode) for sharing the source electrode or the drain electrode of the thin film transistor 241, the source electrode and the drain electrode and the data line 22; depositing a second insulating layer 234 on the active layer 232 and covering the second metal layer 233 on the active layer, wherein the second insulating layer 234 is used for covering the active layer 232 and flattening the pixel region 23; a pixel electrode 235 is deposited on the second insulating layer 234, and in some embodiments, the material of the pixel electrode 235 is indium tin oxide.
Through the above steps, a thin film transistor region 24 is formed at the intersection of the scan line 21 and the data line 22, and a main region thin film transistor, a sub region thin film transistor, and a shared thin film transistor 241 are formed in the thin film transistor region 24.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The foregoing has described in detail an electronic device provided by embodiments of the present application, and specific examples have been applied herein to illustrate the principles and embodiments of the present application, where the foregoing examples are only for aiding in understanding of the technical solutions and core ideas of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. An array substrate is characterized by comprising a transparent substrate and a pixel structure arranged on the transparent substrate; the pixel structure includes:
scan lines and data lines crossing each other;
a pixel region defined by the scan line and the data line crossing each other;
a thin film transistor region formed at an intersection of the scan line and the data line;
in the pixel region, a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode are sequentially laminated on one side of the transparent substrate;
a through hole is formed in the first metal layer, the through hole corresponds to orthographic projection of the active layer on the first metal layer, so that a light transmission part is formed below the active layer and corresponds to the active layer, and the light transmission part is used for transmitting light to irradiate the active layer; an opaque region is arranged in the pixel region, the opaque region extends from one end of the pixel region to the other end, and at least part of the active layer and the light transmitting part is positioned in the opaque region.
2. The array substrate of claim 1, wherein the first metal layer comprises a common electrode.
3. The array substrate of claim 1, wherein the light-transmitting portion extends from one end of the pixel region to the other end.
4. The array substrate according to claim 1, wherein a width of the light transmitting portion is greater than or equal to a width of the active layer.
5. The array substrate of claim 1, wherein a width of the pixel electrode is less than or equal to a width of the active layer.
6. The array substrate of claim 1, wherein the active layer has light stability.
7. The array substrate of claim 6, wherein a forbidden bandwidth of the active layer is greater than 3eV.
8. The array substrate according to claim 1, wherein the thin film transistor region is provided with a main region thin film transistor, a sub region thin film transistor, and a shared thin film transistor, the second metal layer includes a source or a drain of the shared thin film transistor, and the light transmitting portion is provided corresponding to the source and/or the drain.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. The preparation method of the array substrate is characterized by comprising the following steps of:
providing a transparent substrate; forming scanning lines and data lines on the transparent substrate, wherein the scanning lines and the data lines cross each other to define a pixel region;
sequentially stacking a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer and a pixel electrode on the transparent substrate, and forming a thin film transistor region at the intersection of the scanning line and the data line; an opaque region is arranged in the pixel region, the opaque region extends from one end of the pixel region to the other end, and at least part of the active layer and the light transmitting part is positioned in the opaque region;
and the through hole corresponds to orthographic projection of the active layer on the first metal layer, so that a light transmission part is formed below the active layer and corresponds to the active layer, and the light transmission part is used for transmitting light to irradiate the active layer.
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| CN103474432A (en) * | 2013-08-28 | 2013-12-25 | 合肥京东方光电科技有限公司 | Array substrate and preparation method and display device of array substrate |
| WO2016078170A1 (en) * | 2014-11-20 | 2016-05-26 | 深圳市华星光电技术有限公司 | Thin-film transistor array substrate, manufacturing method, and display device |
| CN107479287A (en) * | 2017-09-04 | 2017-12-15 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof |
| CN110837195A (en) * | 2019-10-22 | 2020-02-25 | 深圳市华星光电技术有限公司 | Eight-domain pixel structure |
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| JP3096372B2 (en) * | 1993-03-18 | 2000-10-10 | シャープ株式会社 | Two-terminal display device |
| CN101325201B (en) * | 2007-06-13 | 2011-04-13 | 北京京东方光电科技有限公司 | Array substrate structure of transparent film transistor and manufacturing method thereof |
| JP5567770B2 (en) * | 2007-09-21 | 2014-08-06 | 株式会社ジャパンディスプレイ | Display device and manufacturing method of display device |
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