CN105974691B - A kind of array substrate of FFS mode and preparation method thereof - Google Patents
A kind of array substrate of FFS mode and preparation method thereof Download PDFInfo
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- CN105974691B CN105974691B CN201610589138.9A CN201610589138A CN105974691B CN 105974691 B CN105974691 B CN 105974691B CN 201610589138 A CN201610589138 A CN 201610589138A CN 105974691 B CN105974691 B CN 105974691B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
Abstract
The invention discloses array substrates of a kind of FFS mode and preparation method thereof.Array substrate definition has pixel display area；The production method includes that the data-signal input side in the pixel display area periphery of the array substrate forms data side metal layer, and scanning signal input side forms scan-side metal layer；Common electrode layer is formed in the array substrate；The data side metal layer and the scan-side metal layer are electrically connected with the common electrode layer respectively in the pixel display area periphery.The invention also discloses a kind of array substrates.The present invention provides common voltage by the data side metal layer and scan-side metal layer of pixel display area periphery for the common electrode layer of array substrate, it does not need to make public electrode wire in pixel display area, it can be while providing common voltage for common electrode layer, the aperture opening ratio for not influencing liquid crystal display panel, mentions high display quality.
Description
Technical field
The present invention relates to technical field of liquid crystal display, in particular to the array substrate and its preparation of a kind of FFS mode
Method.
Background technique
Fringe field switching (Fringe Field Switching, abbreviation FFS) is a kind of fringing field liquid crystal display mode, is
A kind of currently used wide viewing angle LCD technology, FFS liquid crystal display panel is with the response time is fast, light transmission rate is high, wide
The advantages that visual angle.FFS mode is to form fringe field by public electrode and pixel electrode in the pixel display area of array substrate
The control to liquid crystal is realized to achieve the purpose that picture is shown, public electrode is the common electrode layer of an entirety, pixel electricity
The current potential of pole is by data line come independent control, and the current potential of public electrode is then by external circuit independent control.In the prior art, lead to
It crosses the formation public electrode wire in pixel display area to be electrically connected with public electrode, is by the public electrode wire in pixel display area
Public electrode provides common voltage, because public electrode wire is arranged in pixel display area, to occupy array substrate pixel
The area in the effective light transmission region of viewing area, becomes smaller so as to cause the aperture opening ratio of array substrate, influences the aobvious of liquid crystal display panel
Show quality.
Summary of the invention
In view of this, the present invention provides a kind of array substrate and preparation method thereof of FFS mode, array substrate of the invention
The aperture opening ratio of liquid crystal display panel can not be influenced, high display quality is mentioned while providing common voltage for common electrode layer.
In order to solve the above technical problems, a technical solution proposed by the present invention is: providing a kind of array base of FFS mode
The preparation method of plate, the array substrate definition have pixel display area；
The preparation method includes:
Data-signal input side in the pixel display area periphery of the array substrate forms data side metal layer, scanning letter
Number input side forms scan-side metal layer；
Common electrode layer is formed in the array substrate；
The pixel display area periphery by the data side metal layer and the scan-side metal layer respectively with the public affairs
Common electrode layer electrical connection；
Wherein, there is several or described data side in the position that the data side metal layer is electrically connected with the common electrode layer
Adjacent boundary is continuously contacted with to realize and be electrically connected between metal layer and the common electrode layer；The scan-side metal layer and institute
There is side adjacent between several or described scan-side metal layer and the common electrode layer in the position for stating common electrode layer electrical connection
Boundary is continuously contacted with to realize electrical connection.
Wherein, at least partly described data side metal layer and at least partly described scan-side metal layer and the pixel are shown
The metal layer same layer of data line in area is formed；
The common electrode layer covers the pixel display area, and at least partly covers institute in the pixel display area periphery
State data side metal layer and even-line interlace side metal layer.
Wherein, the data-signal input side of the pixel display area periphery in the array substrate forms data side metal
Layer, scanning signal input side form scan-side metal layer specifically:
The first metal layer is formed in the pixel display area periphery of the array substrate, it is aobvious to the pixel by one of light shield
Show that the first metal layer of area periphery scanning signal input side performs etching；
The first separation layer is formed in the array substrate, the data by one of light shield in the pixel display area periphery
Through-hole is formed on first separation layer of signal input side；
Second metal layer is formed on the separation layer, the data-signal input side in the pixel display area periphery, institute
It states second metal layer to be electrically connected by the through-hole on first separation layer with the first metal layer, forms data-signal input
The data side metal layer of side forms scanning signal in the second metal layer of the scanning signal input side of the pixel display area periphery
The scan-side metal layer of input side；
Wherein, the first metal layer is the metal layer being formed simultaneously with scan line in pixel display area, second gold medal
Belonging to layer is the metal layer being formed simultaneously with data line in pixel display area.
Wherein, the data-signal input side of the pixel display area periphery in the array substrate forms data side metal
Layer, scanning signal input side form scan-side metal layer specifically:
The first metal layer is formed in the pixel display area periphery of the array substrate, by light shield to the pixel display area
The first metal layer of peripheral data signal input side performs etching；
The first separation layer is formed in the array substrate, the scanning signal by light shield in the pixel display area periphery
Through-hole is formed on first separation layer of input side；
Second metal layer is formed on the separation layer, the scanning signal input side in the pixel display area periphery, institute
It states second metal layer to be electrically connected by the through-hole on first separation layer with the first metal layer, forms scanning signal input
The scan-side metal layer of side forms data-signal in the first metal layer of the data-signal input side of the pixel display area periphery
The data side metal layer of input side；
Wherein, the first metal layer is the metal layer being formed simultaneously with scan line in pixel display area, second gold medal
Belonging to layer is the metal layer being formed simultaneously with data line in pixel display area.
Wherein, described to distinguish the data side metal layer and the scan-side metal layer in the pixel display area periphery
It is electrically connected with the common electrode layer specifically:
The second separation layer is formed in the second metal layer, is formed flatness layer on second separation layer, is passed through one
Road light shield forms through-hole on the flat laye；
Common electrode layer is formed on the flat laye, and through-hole is formed in the common electrode layer by one of light shield,
The position consistency of through-hole on the position of through-hole in the common electrode layer and the flatness layer；
Third separation layer is formed in the common electrode layer, by one of light shield simultaneously in the third separation layer and institute
It states and forms through-hole on the second separation layer, the position of through-hole and the common electrical on the third separation layer and second separation layer
The position consistency of through-hole on the layer of pole, while passing through the light shield with along with and forming another through-hole on the third separation layer；
Form pixel electrode layer on the third separation layer, the pixel electrode layer by another through-hole with it is described
Common electrode layer electrical connection, wherein the pixel electrode layer is in the pixel display area periphery, in the pixel display area
Pixel electrode is formed simultaneously.
Another embodiment of the present invention provides a kind of array substrate of FFS mode, the array substrate definition has pixel to show
Area, and at least common electrode layer is provided on the pixel display area；
The data-signal input side of the pixel display area periphery of the array substrate is equipped with data side metal layer, scanning signal
Input side is equipped with scan-side metal layer, the data side metal layer and the scan-side metal layer electricity public electrode described in succession
Layer, provides common voltage for the common electrode layer；
Wherein, there is several or described data side in the position that the data side metal layer is electrically connected with the common electrode layer
Adjacent boundary is continuously contacted with to realize and be electrically connected between metal layer and the common electrode layer；The scan-side metal layer and institute
There is side adjacent between several or described scan-side metal layer and the common electrode layer in the position for stating common electrode layer electrical connection
Boundary is continuously contacted with to realize electrical connection.
Wherein, the data side metal layer and the scan-side metal layer are respectively connected with pcb board, the pcb board with it is public
Voltage source connection.
Wherein, the data side metal layer includes the first metal layer being arranged from bottom to up and second metal layer, described to sweep
It retouches side metal and the second metal layer same layer is arranged；Or
The scan-side metal layer includes the first metal layer being arranged from bottom to up and second metal layer, the data side gold
Belong to layer and the second metal layer same layer is arranged；
Wherein, the first metal layer is the metal layer being formed simultaneously with scan line in pixel display area, second gold medal
Belonging to layer is the metal layer being formed simultaneously with data line in pixel display area.
Wherein, the data side metal layer and the scan-side metal layer are respectively connected with pcb board specifically:
In the data side metal layer, only the first metal layer connects the pcb board；Or
In the scan-side metal layer, only the first metal layer is connected with pcb board.
Wherein, the data side metal layer and the scan-side metal layer electricity common electrode layer described in succession specifically:
In the data side metal layer or the scan-side metal layer, the first metal layer and the second metal layer it
Between be equipped with the first separation layer, the second metal layer is electrically connected by the through-hole on first separation layer with the first metal layer
It connects；
The second separation layer, flatness layer, common electrode layer, third isolation are successively arranged in the second metal layer from bottom to up
Layer and pixel electrode layer, the second metal layer pass through on second separation layer, the flatness layer and the third separation layer
Through-hole be electrically connected with the pixel electrode layer, the pixel electrode layer and the common electrode layer pass through the third separation layer
On another through-hole electrical connection, realize that the second metal layer is electrically connected with the common electrode layer；
The pixel electrode layer is in pixel display area periphery, with the shape simultaneously of the pixel electrode in the pixel display area
At.
The utility model has the advantages that being different from the prior art, the present invention passes through the number in the pixel display area of array substrate periphery
It is believed that number input side forms data side metal layer, scanning signal input side forms scan-side metal layer；In the array substrate
Form common electrode layer；The pixel display area periphery by the data side metal layer and the scan-side metal layer respectively with
The common electrode layer electrical connection.The present invention is battle array using the data side metal layer and scan-side metal layer of pixel display area periphery
The common electrode layer of column substrate provides common voltage, does not need to make public electrode wire in pixel display area, can be public
While common electrode layer provides common voltage, the aperture opening ratio of liquid crystal display panel is not influenced, mentions high display quality.
Detailed description of the invention
Fig. 1 is the flow diagram of one embodiment of preparation method of array substrate of the present invention；
Fig. 2 is the floor map for the array substrate being prepared according to Fig. 1；
Fig. 3 is an idiographic flow schematic diagram of step S1 in Fig. 1；
Fig. 4 a- Fig. 4 b is the data side metal layer being prepared according to Fig. 3 and the structural schematic diagram of scan-side metal layer；
Fig. 5 is another idiographic flow schematic diagram of step S1 in Fig. 1；
Fig. 6 a- Fig. 6 b is the scan-side metal layer being prepared according to Fig. 5 and the structural schematic diagram of data side metal layer；
Fig. 7 is the idiographic flow schematic diagram of step S3 in Fig. 1；
Fig. 8 a- Fig. 8 d is the data side metal layer being prepared according to Fig. 7 and scan-side metal layer and common electrode layer electricity
The structural schematic diagram of connection；
Fig. 9 a- Fig. 9 d is the floor map of Fig. 8 a- Fig. 8 d.
Specific embodiment
To make those skilled in the art more fully understand technical solution of the present invention, with reference to the accompanying drawing and it is embodied
Example is described in further detail a kind of array substrate of FFS mode provided by the present invention and preparation method thereof.In the accompanying drawings,
In order to understand device, the thickness of layer and region is exaggerated, identical label is used to indicate identical in the whole instruction and attached drawing
Element.
The array substrate definition of the FFS mode of the embodiment of the present invention has pixel display area, and the pixel display area refers to array
Substrate is equipped with pixel electrode, the region shown for liquid crystal display panel.
Fig. 1 is the flow diagram of one embodiment of preparation method of array substrate of the present invention, the preparation side of the array substrate
Method specifically comprises the following steps:
S1, the data-signal input side in the pixel display area periphery of the array substrate form data side metal layer, sweep
It retouches signal input side and forms scan-side metal layer.
Data line is in longitudinal arrangement in array substrate, and data-signal, in longitudinal transmission, will be counted according to the arrangement of data line
It is believed that number along the pixel display area of data line longitudinal direction input array substrate direction definition be data-signal input side；In array base
The data-signal input side of the pixel display area periphery of plate forms one layer of metal layer, which is defined as data side metal layer.
Scan line line is in laterally arrangement in array substrate, and scanning signal is in lateral transport according to the arrangement of scan line, by scanning signal
Direction definition along the pixel display area of scan line transverse direction input array substrate is scanning signal input side；In the picture of array substrate
The scanning signal input side of plain non-display area forms one layer of metal layer, which is defined as data side metal layer.
In at least partly described data side metal layer and at least partly described scan-side metal layer and the pixel display area
The metal layer same layer of data line formed；One layer, which is formed, by sputtering, deposition or coating in array substrate is used to prepare scanning
The metal layer of line and/or data line, then by the methods of coating, exposure, development, wet etching, dry etching and removing in pixel display area
Scan line and data line are formed, while forming the metal layer for surrounding the pixel display area in pixel display area periphery.
S2, common electrode layer is formed in the array substrate.
Common electrode layer in liquid crystal display panel based on FFS mode is arranged in array substrate, in array substrate,
The common electrode layer at least covers the pixel display area of array substrate, and optionally, the region of common electrode layer covering is slightly larger than picture
Plain viewing area.
S3, the pixel display area periphery by the data side metal layer and the scan-side metal layer respectively with it is described
Common electrode layer electrical connection.
Pixel display area periphery by data side metal layer and scan-side metal layer respectively with the public electrode of array substrate
Layer electrical connection, data side metal layer and scan-side metal layer are connect with public voltage source respectively, then data metal layer and scanning gold
Common voltage can be provided for the common electrode layer of array substrate by belonging to layer, to utilize the data metal layer of pixel display area periphery
Common voltage is provided for common electrode layer with scanning metal layer, is not required to make public electrode wire in pixel display area, Neng Gouwei
Common electrode layer does not influence the purpose of the aperture opening ratio of liquid crystal display panel while providing common voltage.
Wherein, data side metal layer and scan-side metal layer can connect the pcb board of array substrate peripheral setting, optional
, the pcb board connection of the data-signal input side periphery of data side metal layer and array substrate, between pcb board and array substrate
It is connected by flip chip (Chip On Film, COF), pcb board is connect with public voltage source again, and pcb board is arranged in array base
The data-signal input side of plate periphery, pcb board are conducted public voltage signal to array substrate by COF；Wherein, data side
The public voltage signal of metal layer is imported by the pcb board of the data-signal input side periphery of array substrate, scan-side metal layer
Public voltage signal is equally imported by the pcb board of the data-signal input side periphery of array substrate.
Wherein it is possible to only provide common electrical by data metal layer or scanning metal layer for the common electrode layer of array substrate
Pressure can also provide common voltage simultaneously by data metal layer and scanning metal layer for the common electrode layer of array substrate.
In pixel display area periphery, data side metal layer and scan-side metal layer respectively with the common electrical of array substrate
Pole layer electrical connection, so that data side metal layer and scan-side metal layer are electrically connected with common electrode layer respectively.Wherein, data side gold
Belonging to the position that layer is electrically connected with common electrode layer has boundary adjacent between several or data side metal layer and common electrode layer to connect
Continued access touching is to realize electrical connection；There is several or scan-side metal layer in the position that scan-side metal layer is electrically connected with common electrode layer
Adjacent boundary is continuously contacted with to realize and be electrically connected between common electrode layer.
The plane for the array substrate that one embodiment of preparation method of array substrate of the present invention according to figure 1 obtains is illustrated
Figure is represented according to embodiments of the present invention in order to clearer as shown in Fig. 2, the structure due to array substrate is stacked
Array substrate one embodiment of preparation method obtain array substrate common voltage transmission path, only marked phase in Fig. 2
The hierarchical structure of pass.
Referring to Fig. 2, the shadow region at center is pixel display area 1, and common electrode layer is equipped at least on pixel display area 1
2.The data-signal input side of the corresponding array substrate of two sides up and down of pixel display area periphery, the left and right two of pixel display area periphery
The scanning signal input side of side corresponding array substrate；The data-signal input side of pixel display area periphery is equipped with data side metal layer
3, the scanning signal input side of pixel display area periphery is equipped with scan-side metal layer 4.Data-signal in Fig. 2 in array substrate is defeated
Enter side equipped with pcb board 5, data side metal layer 3 is connect by feeding point 6 with the pcb board 5 of data-signal input side, wherein scanning
Side metal layer periphery is equipped with COF, and COF also is provided between data side metal layer 3 and pcb board, and pcb board passes through COF for common voltage
Signal imports in array substrate.The region of common electrode layer covering in Fig. 2 is slightly larger than pixel display area 1, unfilled region
For the overlapping region with data side metal layer and scan-side metal layer respectively of common electrode layer 2, in the overlapping region, data side gold
Belong to layer and scan-side metal layer is electrically connected with common electrode layer 2 respectively, the position that data side metal layer is electrically connected with common electrode layer
Setting 7 has several, and the position 8 that scan-side metal layer is electrically connected with common electrode layer also has several.In addition, data side metal layer and public affairs
Common electrode layer can also be continuously contacted with by adjacent boundary to realize electrical connection, and scan-side metal layer and common electrode layer may be used also
Electrical connection is realized to continuously contact with by adjacent boundary.Data side metal layer and scan-side metal layer respectively with public electrode
It is electrically connected at layer electrical connection.
The array substrate that the preparation method of array substrate obtains through the invention utilizes the data side of pixel display area periphery
Metal layer and scan-side metal layer provide common voltage for the common electrode layer of array substrate, establish in pixel display area periphery public
The conducting path of common voltage is not required to make public electrode wire in pixel display area, so that being reached for common electrode layer provides public affairs
The purpose of the aperture opening ratio of liquid crystal display panel is not influenced while common voltage.
Optionally, as shown in figure 3, step S1 specifically comprises the following steps:
S101, the first metal layer is formed in the pixel display area periphery of the array substrate, by one of light shield to described
The first metal layer of pixel display area periphery scanning signal input side performs etching.
One layer of metal layer for being used to prepare scan line is formed by sputtering, deposition or coating in array substrate, by the gold
Belong to layer and is defined as the first metal layer.Pass through the processes such as coating, exposure, development, wet etching, dry etching and removing on the first metal layer,
Scan line is formed in pixel display area, while the first metal layer of pixel display area periphery scanning signal input side being etched,
Peripheral data signal input side in pixel display area remains with the first metal layer at this time.
S102, the first separation layer is formed in the array substrate, by one of light shield in the pixel display area periphery
Data-signal input side the first separation layer on form through-hole.
The first separation layer is formed in array substrate, in pixel display area periphery scanning signal input side, due to the first gold medal
Belong to layer to be etched, the first separation layer is deposited on substrate；In pixel display area peripheral data signal input side, the first separation layer
Covering is on the first metal layer.By one of light shield the pixel display area periphery data-signal input side first isolation
Through-hole is formed on layer.The first separation layer of scanning signal input side can also be etched away in this step.
S103, second metal layer is formed on first separation layer.
On the first separation layer formed second metal layer be together with the metal layer formed data line in pixel display area,
Second metal layer is same metal layer with the metal layer for being used to form data line.By techniques such as sputtering, deposition or coatings by
Two metal layers are formed on the first separation layer, the data-signal input side in the pixel display area periphery, and second metal layer is logical
The through-hole crossed on the first separation layer is electrically connected with the first metal layer, forms the data side metal layer of data-signal input side.Institute
State the scanning signal input side of pixel display area periphery second metal layer formed scan-side metal layer, i.e., scan-side metal layer with
The setting of second metal layer same layer.As shown in figures 4 a and 4b, Fig. 4 a is the structural schematic diagram of data side metal layer 3, data side gold
Belonging to layer 3 includes the first metal layer 301, the first separation layer 303 and the second metal layer 302 set gradually from bottom to up, the first gold medal
Belong to layer 301 to be electrically connected by the through-hole 3031 on the first separation layer 303 with second metal layer 302；Fig. 4 b is scan-side metal layer 4
Structural schematic diagram, scan-side metal layer 4 and second metal layer 302 are same layer, and scan-side metal layer 4 and second metal layer
302 same layers are arranged, and are the first separation layer 303 below scan-side metal layer 4, the first separation layer 303 can also be in step herein
It is etched in S102.By 301 connecting PCB board of the first metal layer in data side metal layer 3, scan-side metal layer periphery is equipped with
COF, also is provided with COF between data side metal layer 3 and pcb board, public voltage signal is imported array substrate by COF by pcb board
On.
Data side metal layer and scan-side metal layer can also be made by following step, optionally, as shown in figure 5, step
Rapid S1 specifically comprises the following steps:
S104, the first metal layer is formed in the pixel display area periphery of the array substrate, by one of light shield to described
The first metal layer of pixel display area peripheral data signal input side performs etching.
One layer of metal layer for being used to prepare scan line is formed in array substrate, which is defined as the first metal
Layer.It performs etching on the first metal layer, forms scan line in pixel display area, while pixel display area peripheral data being believed
The first metal layer etching of number input side, pixel display area periphery scanning signal input side remains with the first metal layer at this time.
S105, the first separation layer is formed in the array substrate, pass through light shield sweeping in the pixel display area periphery
It retouches and forms through-hole on the first separation layer of signal input side.
The first separation layer is formed in array substrate, in pixel display area peripheral data signal input side, due to the first gold medal
Belong to layer to be etched, the first separation layer is deposited on substrate；In pixel display area periphery scanning signal input side, the first separation layer
Covering is on the first metal layer.By one of light shield the pixel display area periphery scanning signal input side first isolation
Through-hole is formed on layer.
S106, second metal layer is formed on first separation layer.
On the first separation layer formed second metal layer be together with the metal layer formed data line in pixel display area,
Second metal layer is same metal layer with the metal layer for being used to form data line.
Second metal layer is formed on the first separation layer, the scanning signal input side in the pixel display area periphery,
Second metal layer is electrically connected by the through-hole on the first separation layer with the first metal layer, and the scan-side of scanning signal input side is formed
Metal layer.Data side metal layer is formed in the second metal layer of the data-signal input side of the pixel display area periphery, that is, is counted
It is arranged according to side metal layer and second metal layer same layer.As shown in figures 6 a and 6b, Fig. 6 a is the structural representation of scan-side metal layer 4
Figure, scan-side metal layer 4 include the first metal layer 401, the first separation layer 403 and the second metal layer set gradually from bottom to up
402, the first metal layer 401 is electrically connected by the through-hole on the first separation layer 403 with second metal layer 402；Fig. 6 b is data side
The structural schematic diagram of metal layer 3, data side metal layer 3 are second metal layer 402, data side metal layer 3 and second metal layer
The setting of 402 same layers；It is the first separation layer 403 below data side metal layer 3, the first separation layer 403 can also be in step herein
It is etched in S105.By 401 connecting PCB board of the first metal layer in scan-side metal layer 4, data side metal layer 3 (is equal to the
Two metal layers 402) connecting PCB board.
Based on the preparation method of above-mentioned data side metal layer and scan-side metal layer, as shown in fig. 7, step S3 is specifically wrapped
Include following steps:
S301, the second separation layer is formed in the second metal layer, form flatness layer on second separation layer, lead to
It crosses one of light shield and forms through-hole on the flat laye.
The second separation layer is formed in second metal layer, forms flatness layer on the second separation layer, flatness layer is carved
The second separation layer is not influenced when erosion, at this point, there is no through-hole on the second separation layer.
S302, common electrode layer is formed on the flat laye, formed in the common electrode layer by one of light shield
Through-hole.
Common electrode layer is deposited on flatness layer, is formed in common electrode layer on one and flatness layer by one of light shield
The corresponding through-hole of through-hole, the position consistency of the through-hole on the position and flatness layer of the through-hole in common electrode layer.Optionally,
The aperture of through-hole in common electrode layer is greater than the aperture of the through-hole on flatness layer.
S303, third separation layer is formed in the common electrode layer, be isolated simultaneously in the third by one of light shield
Layer and second separation layer on form through-hole, on the third separation layer and second separation layer position of through-hole with it is described
The position consistency of through-hole in common electrode layer, while passing through the light shield with along with and forming another lead on the third separation layer
Hole.
It is formed simultaneously corresponding through-hole on third separation layer and the second separation layer by one of light shield, meanwhile, pass through
Light shield forms another through-hole on third separation layer with along with.
S304, pixel electrode layer is formed on the third separation layer.
Pixel electrode layer, can be with the shape simultaneously of the pixel electrode in the pixel display area in pixel display area periphery
At.Pixel electrode layer is electrically connected by another through-hole on third separation layer with common electrode layer.
Pixel electrode layer is set in the electrical communication path of common electrode layer and data side metal layer and scan-side metal layer, it is public
Position that position that common electrode layer is electrically connected with pixel electrode layer, common electrode layer are electrically connected with data side metal layer and public
The position that electrode layer is electrically connected with scan-side metal layer has multiple, and the position of multiple electrical connection is aobvious in the pixel of array substrate
Show that area periphery is distributed, enables to the common voltage more stable homogeneous in common electrode layer.
S3 through the above steps, then obtained in array substrate data side metal layer and scan-side metal layer respectively with public affairs
The structure of common electrode layer electrical connection.Referring to Fig. 8 a, data side metal layer be the first metal layer 301 set gradually from bottom to up,
First separation layer 303 and second metal layer 302, the first metal layer 301 pass through the through-hole 3031 and second on the first separation layer 303
Metal layer 302 is electrically connected, and is successively arranged the second separation layer 9, flatness layer 10, common electrode layer 11, third in second metal layer 302
Separation layer 12 and pixel electrode layer 13, wherein through-hole of the pixel electrode layer 13 on pixel display area periphery, the second separation layer 9
With one of through-hole 1201 on third separation layer 12 be by with along with light shield formed, second metal layer 302 passes through the
One of through-hole on through-hole 1001 and third separation layer 12 on the through-hole 901 and flatness layer 100 of two separation layers 303
1201 are electrically connected with pixel electrode layer 13, and pixel electrode layer 13 passes through another through-hole 1202 and common electrical on third separation layer 12
Pole layer 11 is electrically connected.Fig. 9 a is the floor map that data side metal layer shown in Fig. 8 a is electrically connected with common electrode layer, data
Signal input is longitudinal input, and dash area is the common electrode layer 11 in array substrate, 301 connecting PCB board of the first metal layer,
Pcb board connects public voltage source, and public voltage source exports constant public voltage signal, and public voltage signal passes through the first metal
Layer 301, is transferred to second metal layer 302 by the through-hole 3031 on the first separation layer, is passing through the through-hole on the second separation layer 9
901, the through-hole 1201 on the through-hole 1001 and third separation layer 12 on flatness layer 10 imports pixel electrode layer 13, then passes through third
Another through-hole 1202 of separation layer 12 imports common electrode layer 11.Referring to Fig. 8 b, scan-side metal layer 4 is second metal layer
302, the structure on scan-side metal layer 4 is identical as the structure on data side metal layer in Fig. 8 a.Fig. 9 b is to sweep shown in Fig. 8 b
The floor map that side metal layer 4 is electrically connected with common electrode layer 11 is retouched, scanning signal input is for laterally input, dash area
Common electrode layer 11, scan-side metal layer periphery are equipped with COF, COF, pcb board also are provided between data side metal layer 3 and pcb board
Public voltage signal is imported on data side metal layer 3 and scan-side metal layer 4 by COF, public voltage signal is scanned
Side metal layer 4 (second metal layer 302), then pass through the through-hole 901 on the second separation layer 9,1001 and of through-hole on flatness layer 10
Through-hole 1201 on third separation layer 12 imports pixel electrode layer 13, then is imported by another through-hole 1202 of third separation layer 12
Common electrode layer.Referring to Fig. 8 c, scan-side metal layer 4 is the first metal layer 401 set gradually from bottom to up, the first separation layer
403 and second metal layer 402, the hierarchical structure on scan-side metal layer 4 is identical as Fig. 8 a, and details are not described herein again.Fig. 9 c is figure
The floor map that scan-side metal layer 4 shown in 8c is connect with common electrode layer electricity 11, scanning signal input are laterally input,
The transmission mode of public voltage signal is illustrated with the plane that data side metal layer 3 is electrically connected with common electrode layer 11 shown in Fig. 9 a
The mode of the common voltage transmission of figure is identical, and details are not described herein again.Referring to Fig. 8 d, data side metal layer 3 is second metal layer
402, the hierarchical structure on data side metal layer 3 is identical as Fig. 8 b, and details are not described herein again.Fig. 9 d is the gold of data side shown in Fig. 8 d
Belong to the floor map that layer 3 is electrically connected with common electrode layer 11, data-signal input is longitudinal input, the biography of public voltage signal
Defeated mode is transmitted with the common voltage for the floor map that data side metal layer 4 is electrically connected with common electrode layer 11 shown in Fig. 9 b
Mode it is identical, details are not described herein again.
Fig. 9 a, Fig. 9 b, in Fig. 9 c and Fig. 9 d, due to logical on the through-hole 901 and third separation layer 12 on the second separation layer 9
Hole 1201 is formed by same light shield, so the through-hole 1201 on the through-hole 901 and third separation layer 12 on the second separation layer 9
It is overlapped, therefore the through-hole 1201 located on third separation layer 12 is only marked in Fig. 9 a, Fig. 9 b, Fig. 9 c and Fig. 9 d.
The preparation method of array substrate of the present invention passes through the data-signal in the pixel display area of array substrate periphery
Input side forms data side metal layer, and scanning signal input side forms scan-side metal layer；It is formed in the array substrate public
Common electrode layer；The pixel display area periphery by the data side metal layer and the scan-side metal layer respectively with the public affairs
Common electrode layer electrical connection.The data side metal layer and scan-side metal layer that the present invention passes through pixel display area periphery are array substrate
Common electrode layer common voltage is provided, do not need to make public electrode wire in pixel display area, can be for public electrode
While layer provides common voltage, the aperture opening ratio of liquid crystal display panel is not influenced, mentions high display quality.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills
Art field similarly includes in scope of patent protection of the invention.
Claims (10)
1. a kind of production method of the array substrate of FFS mode, which is characterized in that the array substrate definition has pixel to show
Area；
The production method includes:
Data-signal input side in the pixel display area periphery of the array substrate forms data side metal layer, and scanning signal is defeated
Enter side and forms scan-side metal layer；
Common electrode layer is formed in the array substrate；
The pixel display area periphery by the data side metal layer and the scan-side metal layer respectively with the common electrical
Pole layer electrical connection；
Wherein, there is several or described data side metal in the position that the data side metal layer is electrically connected with the common electrode layer
The layer boundary adjacent between the common electrode layer is continuously contacted with to realize and be electrically connected；The scan-side metal layer and the public affairs
The position of common electrode layer electrical connection has boundary adjacent between several or described scan-side metal layer and the common electrode layer to connect
Continued access touching is to realize electrical connection.
2. manufacturing method according to claim 1, which is characterized in that at least partly described data side metal layer and at least portion
The metal layer same layer of the scan-side metal layer and the data line in the pixel display area is divided to be formed；
The common electrode layer covers the pixel display area, and at least partly covers the number in the pixel display area periphery
According to side metal layer and the scan-side metal layer.
3. manufacturing method according to claim 1, which is characterized in that described outside the pixel display area of the array substrate
The data-signal input side enclosed forms data side metal layer, and scanning signal input side forms scan-side metal layer specifically:
The first metal layer is formed in the pixel display area periphery of the array substrate, by one of light shield to the pixel display area
The first metal layer of peripheral scanning signal input side performs etching；
The first separation layer is formed in the array substrate, the data-signal by one of light shield in the pixel display area periphery
Through-hole is formed on first separation layer of input side；
Second metal layer is formed on the separation layer；Data-signal input side in the pixel display area periphery, described
Two metal layers are electrically connected by the through-hole on first separation layer with the first metal layer, and data-signal input side is formed
Data side metal layer forms scanning signal input in the second metal layer of the scanning signal input side of the pixel display area periphery
The scan-side metal layer of side；Wherein, the first metal layer is the metal layer being formed simultaneously with scan line in pixel display area, institute
Stating second metal layer is the metal layer being formed simultaneously with data line in pixel display area.
4. manufacturing method according to claim 1, which is characterized in that described outside the pixel display area of the array substrate
The data-signal input side enclosed forms data side metal layer, and scanning signal input side forms scan-side metal layer specifically:
The first metal layer is formed in the pixel display area periphery of the array substrate, by light shield to the pixel display area periphery
The first metal layer of data-signal input side performs etching；
The first separation layer is formed in the array substrate, the scanning signal by light shield in the pixel display area periphery inputs
Through-hole is formed on first separation layer of side；
Second metal layer is formed on the separation layer, the scanning signal input side in the pixel display area periphery, described
Two metal layers are electrically connected by the through-hole on first separation layer with the first metal layer, and scanning signal input side is formed
Scan-side metal layer forms data-signal input in the second metal layer of the data-signal input side of the pixel display area periphery
The data side metal layer of side；
Wherein, the first metal layer is the metal layer being formed simultaneously with scan line in pixel display area, the second metal layer
It is the metal layer being formed simultaneously with data line in pixel display area.
5. production method according to claim 3 or 4, which is characterized in that it is described in the pixel display area periphery by institute
It states data side metal layer and the scan-side metal layer is electrically connected with the common electrode layer respectively specifically:
The second separation layer is formed in the second metal layer, is formed flatness layer on second separation layer, is passed through one of light
Cover forms through-hole on the flat laye；
Common electrode layer is formed on the flat laye, and through-hole is formed in the common electrode layer by one of light shield, it is described
The position consistency of through-hole on the position of through-hole in common electrode layer and the flatness layer；
Third separation layer is formed in the common electrode layer, by one light shield simultaneously in the third separation layer and described the
Through-hole is formed on two separation layers, the position of through-hole and the common electrode layer on the third separation layer and second separation layer
On through-hole position consistency, while by with along with light shield form another through-hole on the third separation layer；
Form pixel electrode layer on the third separation layer, the pixel electrode layer by another through-hole with it is described public
Electrode layer electrical connection, wherein the pixel electrode layer is in the pixel display area periphery, with the pixel in the pixel display area
Electrode is formed simultaneously.
6. a kind of array substrate of FFS mode, which is characterized in that the array substrate definition has pixel display area, and at least exists
Common electrode layer is provided on the pixel display area；
The data-signal input side of the pixel display area periphery of the array substrate is equipped with data side metal layer, scanning signal input
Side is equipped with scan-side metal layer, the data side metal layer and the scan-side metal layer electricity common electrode layer described in succession,
Common voltage is provided for the common electrode layer；
Wherein, there is several or described data side metal in the position that the data side metal layer is electrically connected with the common electrode layer
The layer boundary adjacent between the common electrode layer is continuously contacted with to realize and be electrically connected；The scan-side metal layer and the public affairs
The position of common electrode layer electrical connection has boundary adjacent between several or described scan-side metal layer and the common electrode layer to connect
Continued access touching is to realize electrical connection.
7. array substrate according to claim 6, which is characterized in that the data side metal layer and the scan-side metal
Layer is respectively connected with pcb board, and the pcb board is connect with public voltage source.
8. array substrate according to claim 7, which is characterized in that the data side metal layer includes being arranged from bottom to up
The first metal layer and second metal layer, the scan-side metal and the second metal layer same layer be arranged；Or
The scan-side metal layer includes the first metal layer being arranged from bottom to up and second metal layer, the data side metal layer
It is arranged with the second metal layer same layer；
Wherein, the first metal layer is the metal layer being formed simultaneously with scan line in pixel display area, the second metal layer
It is the metal layer being formed simultaneously with data line in pixel display area.
9. array substrate according to claim 8, which is characterized in that the data side metal layer and the scan-side metal
Layer is respectively connected with pcb board specifically:
In the data side metal layer, only the first metal layer connects the pcb board；Or
In the scan-side metal layer, only the first metal layer is connected with pcb board.
10. array substrate according to claim 8, which is characterized in that the data side metal layer and scan-side gold
Belong to the layer electricity common electrode layer described in succession specifically:
In the data side metal layer or the scan-side metal layer, set between the first metal layer and the second metal layer
There is the first separation layer, the second metal layer is electrically connected by the through-hole on first separation layer with the first metal layer；
Be successively arranged from bottom to up in the second metal layer the second separation layer, flatness layer, common electrode layer, third separation layer and
Pixel electrode layer, the second metal layer pass through logical on second separation layer, the flatness layer and the third separation layer
Hole is electrically connected with the pixel electrode layer, and the pixel electrode layer and the common electrode layer pass through on the third separation layer
Another through-hole electrical connection, realizes that the second metal layer is electrically connected with the common electrode layer；
The pixel electrode layer is formed simultaneously in the pixel display area periphery with the pixel electrode in the pixel display area.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020015002A (en) * | 2000-07-11 | 2002-02-27 | 가네꼬 히사시 | Liquid crystal display unit having pixel electrode encircled with partition wall and process for fabrication thereof |
| CN102116981A (en) * | 2009-12-30 | 2011-07-06 | 乐金显示有限公司 | Thin film transistor array substrate and method for fabricating the same |
| CN102466936A (en) * | 2010-11-04 | 2012-05-23 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display and manufacturing method of array substrate |
| CN103474432A (en) * | 2013-08-28 | 2013-12-25 | 合肥京东方光电科技有限公司 | Array substrate and preparation method and display device of array substrate |
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| KR102020353B1 (en) * | 2013-03-20 | 2019-11-05 | 삼성디스플레이 주식회사 | Display apparatus and method of manufacturing the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020015002A (en) * | 2000-07-11 | 2002-02-27 | 가네꼬 히사시 | Liquid crystal display unit having pixel electrode encircled with partition wall and process for fabrication thereof |
| CN102116981A (en) * | 2009-12-30 | 2011-07-06 | 乐金显示有限公司 | Thin film transistor array substrate and method for fabricating the same |
| CN102466936A (en) * | 2010-11-04 | 2012-05-23 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display and manufacturing method of array substrate |
| CN103474432A (en) * | 2013-08-28 | 2013-12-25 | 合肥京东方光电科技有限公司 | Array substrate and preparation method and display device of array substrate |
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