CN105974691A - FFS mode array substrate and preparing method thereof - Google Patents
FFS mode array substrate and preparing method thereof Download PDFInfo
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- CN105974691A CN105974691A CN201610589138.9A CN201610589138A CN105974691A CN 105974691 A CN105974691 A CN 105974691A CN 201610589138 A CN201610589138 A CN 201610589138A CN 105974691 A CN105974691 A CN 105974691A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an FFS mode array substrate and a preparing method thereof. A pixel display area is defined on the array substrate. The preparing method comprises the steps of forming a data side metal layer on the digital signal input side on the periphery of the pixel display area of the array substrate, and forming a scanning side metal layer on the scanning signal input side; forming a common electrode layer on the array substrate; connecting the data side metal layer and the scanning side metal layer with the common electrode layer electrically on the periphery of the pixel display area. The invention further discloses an array substrate. Common voltage is provided for the common electrode layer of the array substrate through the data side metal layer and the scanning side metal layer on the periphery of the pixel display area, manufacturing of a common electrode wire in the pixel display area is not needed, and the aperture ratio of a liquid crystal display panel can not be affected and display quality can be improved while common voltage is provided for the common electrode layer.
Description
Technical field
The present invention relates to technical field of liquid crystal display, in particular to the array of a kind of FFS mode
Substrate and preparation method thereof.
Background technology
Fringe field switching (Fringe Field Switching is called for short FFS) is a kind of fringing field liquid crystal
Display pattern, is the most conventional a kind of wide viewing angle lcd technology, FFS display panels
There is the advantages such as response time is fast, light transmission rate is high, wide viewing angle.FFS mode is at array base palte
Pixel display area form fringe field by public electrode and pixel electrode and realize liquid crystal
Controlling to reach the purpose that picture shows, public electrode is an overall common electrode layer, pixel
The current potential of electrode is independently controlled by data wire, and the current potential of public electrode is then independent by external circuit
Control.In prior art, by forming public electrode wire and public electrode electricity in pixel display area
Connect, provide common electric voltage by the public electrode wire in pixel display area for public electrode, because
Public electrode wire is arranged in pixel display area, thus occupies having of array base palte pixel display area
The area of effect transmission region, thus cause the aperture opening ratio of array base palte to diminish, affect LCD
The display quality of plate.
Summary of the invention
In view of this, the present invention provides array base palte of a kind of FFS mode and preparation method thereof, this
The array base palte of invention can not affect liquid crystal while providing common electric voltage for common electrode layer
The aperture opening ratio of display floater, improves display quality.
For solving above-mentioned technical problem, the technical scheme that the present invention proposes is: provide a kind of FFS
The preparation method of the array base palte of pattern, the definition of described array base palte has pixel display area；
Described preparation method includes:
The data signal input side peripheral in the pixel display area of described array base palte forms data side
Metal level, scanning signal input side forms scan-side metal level；
Described array base palte is formed common electrode layer；
Peripheral by described data side metal level and described scan-side metal level in described pixel display area
Electrically connect with described common electrode layer respectively；
Wherein, the position that described data side metal level electrically connects with described common electrode layer has some,
Or adjacent border contacts continuously with reality between described data side metal level and described common electrode layer
Now electrically connect；The position that described scan-side metal level electrically connects with described common electrode layer has some,
Or adjacent border contacts continuously with reality between described scan-side metal level and described common electrode layer
Now electrically connect.
Wherein, described data side metal level and described scan-side metal level and described pixel display area
Interior scan line and/or the metal level of data wire are together formed；
Described common electrode layer covers described pixel display area, and peripheral in described pixel display area
At least partly cover described data side metal level and even-line interlace side metal level.
Wherein, the described data signal input side peripheral in the pixel display area of described array base palte
Formed data side metal level, scanning signal input side formed scan-side metal level particularly as follows:
The first metal layer is formed, by one light in the periphery, pixel display area of described array base palte
Cover the first metal layer to periphery, described pixel display area scanning signal input side to perform etching；
Described array base palte is formed the first sealing coat, covers on described pixel by one light and show
Show and form through hole on the first sealing coat of the peripheral data signal input side in district；
Described sealing coat forms the second metal level, the data peripheral in described pixel display area
Signal input side, described second metal level is by the through hole on described first sealing coat and described the
One metal level electrical connection, forms the data side metal level of data signal input side, in described pixel
Second metal level of the scanning signal input side that viewing area is peripheral forms sweeping of scanning signal input side
Retouch side metal level；
Wherein, the metal level that described the first metal layer concurrently forms with pixel display area interscan line,
The metal level that described second metal level concurrently forms with data wire in pixel display area.
Wherein, the described data signal input side peripheral in the pixel display area of described array base palte
Formed data side metal level, scanning signal input side formed scan-side metal level particularly as follows:
The first metal layer is formed, by light shield pair in the periphery, pixel display area of described array base palte
The first metal layer of described pixel display area peripheral data signal input side performs etching；
Described array base palte is formed the first sealing coat, covers on described pixel display area by light
Through hole is formed on first sealing coat of peripheral data signal input side；
Described sealing coat forms the second metal level, the scanning peripheral in described pixel display area
Signal input side, described second metal level is by the through hole on described first sealing coat and described the
One metal level electrical connection, forms the scan-side metal level of scanning signal input side, in described pixel
Second metal level of the data signal input side that viewing area is peripheral forms the number of data signal input side
According to side metal level；
Wherein, the metal level that described the first metal layer concurrently forms with pixel display area interscan line,
The metal level that described second metal level concurrently forms with data wire in pixel display area.
Wherein, described peripheral by described data side metal level with described sweep in described pixel display area
Retouch side metal level electrically connect with described common electrode layer respectively particularly as follows:
Described second metal level forms the second sealing coat, described second sealing coat is formed flat
Smooth layer, covers on formation through hole on described flatness layer by one light；
Described flatness layer is formed common electrode layer, covers on described common electrode layer by one light
Upper formation through hole, the position of the through hole in described common electrode layer and the through hole on described flatness layer
Position consistency；
Described common electrode layer forms the 3rd sealing coat, by one light shield simultaneously described the
On three sealing coats and described second sealing coat formed through hole, described 3rd sealing coat and described second every
On absciss layer, the position of through hole and the position consistency of the through hole in described common electrode layer, pass through same simultaneously
Another through hole is formed together on described 3rd sealing coat；
On described 3rd sealing coat formed pixel electrode layer, described pixel electrode layer by described separately
One through hole electrically connects with described common electrode layer, and wherein, described pixel electrode layer shows in described pixel
Show that district is peripheral, concurrently form with the pixel electrode in described pixel display area.
Another embodiment of the present invention provides the array base palte of a kind of FFS mode, and described array base palte is fixed
Justice has pixel display area, and is at least provided with common electrode layer on described pixel display area；
The data signal input side of the periphery, pixel display area of described array base palte is provided with data side gold
Belonging to layer, scanning signal input side is provided with scan-side metal level, described data side metal level and described sweep
Retouch the side metal level the most described common electrode layer of all electricity, provide common electric voltage for described common electrode layer；
Wherein, the position that described data side metal level electrically connects with described common electrode layer has some,
Or adjacent border contacts continuously with reality between described data side metal level and described common electrode layer
Now electrically connect；The position that described scan-side metal level electrically connects with described common electrode layer has some,
Or adjacent border contacts continuously with reality between described scan-side metal level and described common electrode layer
Now electrically connect.
Wherein, described data side metal level and described scan-side metal level are respectively connected with pcb board,
Described pcb board is connected with public voltage source.
Wherein, described data side metal level includes the first metal layer and second arranged from bottom to up
Metal level, described scan-side metal is arranged with layer with described second metal level；Or
Described scan-side metal level includes the first metal layer and the second metal level arranged from bottom to up,
Described data side metal level is arranged with layer with described second metal level；
Wherein, described the first metal layer is the metal concurrently formed with pixel display area interscan line
Layer, described second metal level is the metal level concurrently formed with data wire in pixel display area.
Wherein, described data side metal level and described scan-side metal level are respectively connected with pcb board tool
Body is:
In described data side metal level, the most described the first metal layer connects described pcb board；Or
In described scan-side metal level, the most described the first metal layer connects pcb board.
Wherein, described data side metal level and described scan-side metal level all electricity are the most described public
Electrode layer particularly as follows:
In described data side metal level or described scan-side metal level, described the first metal layer and institute
State and between the second metal level, be provided with the first sealing coat, described second metal level by described first every
Through hole on absciss layer electrically connects with described the first metal layer；
The second sealing coat, flatness layer, public it is sequentially provided with from bottom to up on described second metal level
Electrode layer, the 3rd sealing coat and pixel electrode layer, described second metal level by described second every
Through hole on absciss layer, described flatness layer and described 3rd sealing coat is electrically connected with described pixel electrode layer
Connecing, described pixel electrode layer and described common electrode layer are by another on described 3rd sealing coat
Through hole electrically connects, it is achieved described second metal level electrically connects with described common electrode layer；
Described pixel electrode layer is peripheral, with the picture in described pixel display area in described pixel display area
Element electrode concurrently forms.
Beneficial effect: be different from prior art, the present invention is shown by the pixel at described array base palte
Showing the data signal input side formation data side metal level that district is peripheral, scanning signal input side is formed to be swept
Retouch side metal level；Described array base palte is formed common electrode layer；Outside described pixel display area
Enclose electric with described common electrode layer respectively to described data side metal level and described scan-side metal level
Connect.The present invention utilizes the data side metal level of periphery, pixel display area and scan-side metal level to be battle array
The common electrode layer of row substrate provides common electric voltage, it is not necessary to make common electrical in pixel display area
Polar curve, it is possible to while providing common electric voltage for common electrode layer, do not affect display panels
Aperture opening ratio, improve display quality.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of preparation method one embodiment of array base palte of the present invention；
Fig. 2 is the floor map of the array base palte prepared according to Fig. 1；
Fig. 3 is an idiographic flow schematic diagram of step S1 in Fig. 1；
Fig. 4 a-Fig. 4 b is the data side metal level and scan-side metal level prepared according to Fig. 3
Structural representation；
Fig. 5 is another idiographic flow schematic diagram of step S1 in Fig. 1；
Fig. 6 a-Fig. 6 b is the scan-side metal level and data side metal level prepared according to Fig. 5
Structural representation；
Fig. 7 is the idiographic flow schematic diagram of step S3 in Fig. 1；
Fig. 8 a-Fig. 8 d be the data side metal level prepared according to Fig. 7 and scan-side metal level with
The structural representation of common electrode layer electrical connection；
Fig. 9 a-Fig. 9 d is the floor map of Fig. 8 a-Fig. 8 d.
Specific embodiment
For making those skilled in the art be more fully understood that technical scheme, below in conjunction with attached
Figure and specific embodiment are to the array base palte of a kind of FFS mode provided by the present invention and preparation side thereof
Method is described in further detail.In the accompanying drawings, in order to understand device, exaggerate the thickness in layer and region
Degree, identical label is used for representing identical element in entire disclosure and accompanying drawing.
The array base palte definition of the FFS mode of the embodiment of the present invention has pixel display area, described pixel
Viewing area refers to that array base palte is provided with pixel electrode, the region shown for display panels.
Fig. 1 is the schematic flow sheet of preparation method one embodiment of array base palte of the present invention, this array
The preparation method of substrate specifically includes following steps:
S1, the data signal input side peripheral in the pixel display area of described array base palte form data
Side metal level, scanning signal input side forms scan-side metal level.
In array base palte, data wire is longitudinal arrangement, data signal according to the arrangement of data wire in vertical
To transmission, data signal is fixed along the direction of the pixel display area of data wire longitudinal direction input array substrate
Justice is data signal input side；The data signal input side peripheral in the pixel display area of array base palte
Forming layer of metal layer, this metal level is defined as data side metal level.Scan line in array base palte
Line is in laterally arrangement, and scanning signal is lateral transport according to the arrangement of scan line, will scanning signal edge
The direction of the pixel display area of scan line horizontal input array substrate is defined as scanning signal input side；
The scanning signal input side peripheral in the pixel display area of array base palte forms layer of metal layer, this gold
Belong to layer and be defined as data side metal level.
Data side metal level and data side metal level that pixel display area is peripheral are and pixel display area
The interior metal level for preparing scan line and/or data wire is formed together.
On array base palte by sputtering, deposit or coat formation one layer for prepare scan line and/
Or the metal level of data wire, then by be coated with, expose, develop, wet etching, dry etching and stripping etc. just
Method forms scan line and data wire in pixel display area, formed in periphery, pixel display area simultaneously around
The metal level of described pixel display area.
S2, on described array base palte formed common electrode layer.
Common electrode layer in display panels based on FFS mode is arranged on array base palte,
On array base palte, this common electrode layer at least covers the pixel display area of array base palte, optionally,
The region that common electrode layer covers is slightly larger than pixel display area.
S3, peripheral by described data side metal level and described scan-side metal in described pixel display area
Layer electrically connects with described common electrode layer respectively.
In pixel display area peripheral by data side metal level and scan-side metal level respectively with array base
Plate common electrode layer electrical connection, data side metal level and scan-side metal level respectively with common electric voltage
Source connects, then data metal layer and scanning metal level can provide for the common electrode layer of array base palte
Common electric voltage, thus the data metal layer utilizing pixel display area peripheral is public with scanning metal level
Electrode layer provides common electric voltage, is not required in pixel display area make public electrode wire, it is possible to for public affairs
Common electrode layer does not affect the purpose of the aperture opening ratio of display panels while providing common electric voltage.
Wherein, data side metal level and scan-side metal level can connect what array substrate peripheral was arranged
Pcb board, optionally, the data signal input side periphery of data side metal level and array base palte
Pcb board connects, by chip on film (Chip On Film, COF) between pcb board and array base palte
Connecting, pcb board is connected with public voltage source again, and pcb board is arranged on the data of array substrate peripheral
Signal input side, public voltage signal is conducted to array base palte by pcb board by COF；Its
In, the public voltage signal of data side metal level is by the data signal input side periphery of array base palte
Pcb board imports, and the public voltage signal of scan-side metal level is equally by the data signal of array base palte
The pcb board importing that input side is peripheral.
Wherein it is possible to only by data metal layer or scanning metal level be the public electrode of array base palte
Layer provide common electric voltage, it is also possible to by data metal layer and scanning metal level be array base palte simultaneously
Common electrode layer provide common electric voltage.
Peripheral in described pixel display area, data side metal level and scan-side metal level respectively with array
Substrate common electrode layer electrical connection so that data side metal level and scan-side metal level respectively with public affairs
Common electrode layer electrically connects.Wherein, if the position that data side metal level electrically connects with common electrode layer has
Do, or border adjacent between data side metal level and common electrode layer contacts to realize being electrically connected continuously
Connect；The position that scan-side metal level electrically connects with common electrode layer has some, or scan-side metal level
The border adjacent with between common electrode layer contacts to realize electrical connection continuously.
The array base that preparation method one embodiment according to the array base palte of the present invention shown in Fig. 1 obtains
The floor map of plate as in figure 2 it is shown, owing to the structure of array base palte is that stacking is arranged, in order to
Clearer preparation method one embodiment representing array base palte according to embodiments of the present invention obtains
To the transmission path of the common electric voltage of array base palte, Fig. 2 only marks relevant hierarchical structure.
With reference to Fig. 2, the shadow region at center is pixel display area 1, at least in pixel display area 1
It is provided with common electrode layer 2.The data of the correspondence array base palte of both sides up and down that pixel display area is peripheral
Signal input side, the scanning signal input of the left and right sides correspondence array base palte that pixel display area is peripheral
Side；The data signal input side of periphery, pixel display area is provided with data side metal level 3, and pixel shows
The scanning signal input side of periphery, district is provided with scan-side metal level 4.At the number of array base palte in Fig. 2
The number of it is believed that input side is provided with pcb board 5, and data side metal level 3 is by distributing point 6 and data signal
The pcb board 5 of input side connects, and wherein, scan-side metal level periphery is provided with COF, data side
Also being provided with COF between metal level 3 and pcb board, pcb board passes through COF by public voltage signal
Import on array base palte.The region that common electrode layer in Fig. 2 covers is slightly larger than pixel display area 1,
Unfilled region be common electrode layer 2 respectively with data side metal level and the weight of scan-side metal level
Folded region, in this overlapping region, data side metal level and scan-side metal level respectively with public electrode
Layer 2 electrical connection, the position 7 that data side metal level electrically connects with common electrode layer has some, scanning
The position 8 that side metal level electrically connects with common electrode layer also has some.Additionally, data side metal level
Can also contact continuously to realize electrical connection by adjacent border with common electrode layer, scan-side gold
Belong to layer to contact continuously to realize electrical connection by adjacent border with common electrode layer.Data
Side metal level and scan-side metal level electrically connect with the common electrode layer place of electrical connection respectively.
The array base palte obtained by the preparation method of array base palte of the present invention, utilizes pixel display area
The common electrode layer that peripheral data side metal level and scan-side metal level are array base palte provides public affairs
Common voltage, sets up the conducting path of common electric voltage in periphery, pixel display area, is not required to show in pixel
Making public electrode wire in district, thus not shadow while common electrode layer offer common electric voltage is provided
Ring the purpose of the aperture opening ratio of display panels.
Optionally, as it is shown on figure 3, step S1 specifically includes following steps:
S101, the periphery, pixel display area of described array base palte formed the first metal layer, by one
The first metal layer of periphery, described pixel display area scanning signal input side is performed etching by road light shield.
By sputtering on array base palte, deposit or coat formation one layer for preparing the gold of scan line
Belong to layer, this metal level is defined as the first metal layer.On the first metal layer by coating, exposure,
The operations such as development, wet etching, dry etching and stripping, form scan line in pixel display area, will simultaneously
The first metal layer etching of periphery, pixel display area scanning signal input side, now outside pixel display area
Enclose data signal input side and remain with the first metal layer.
S102, on described array base palte, form the first sealing coat, cover on described picture by one light
Through hole is formed on first sealing coat of the data signal input side that element viewing area is peripheral.
Array base palte is formed the first sealing coat, scans signal input side in periphery, pixel display area,
Owing to the first metal layer is etched, the first sealing coat is deposited on substrate；Outside pixel display area
Enclosing data signal input side, the first sealing coat covers on the first metal layer.Covered on by one light
Through hole is formed on first sealing coat of the data signal input side that described pixel display area is peripheral.At this
The first sealing coat scanning signal input side in step can also be etched away.
S103, on described first sealing coat, form the second metal level.
First sealing coat is formed the second metal level and forms data wire in pixel display area
Metal level together, the second metal level be same metal level for forming the metal level of data wire.
By sputtering, deposit or the second metal level is formed on the first sealing coat, in institute by the technique such as coating
Stating the data signal input side that pixel display area is peripheral, the second metal level is by the first sealing coat
Through hole electrically connects with the first metal layer, forms the data side metal level of data signal input side.Institute
The second metal level stating the peripheral scanning signal input side in pixel display area forms scan-side metal level,
I.e. scan-side metal level and the second metal level is arranged with layer.As shown in figures 4 a and 4b, Fig. 4 a
For the structural representation of data side metal level 3, data side metal level 3 includes setting the most successively
The first metal layer the 301, first sealing coat 303 put and the second metal level 302, the first metal layer
301 are electrically connected with the second metal level 302 by the through hole 3031 on the first sealing coat 303；Figure
4b is the structural representation of scan-side metal level 4, scan-side metal level 4 and the second metal level 302
For same layer, and scan-side metal level 4 and the second metal level 302 are arranged with layer, scan-side metal
Being the first sealing coat 303 below layer 4, the first sealing coat 303 can also be in step s 102 herein
It is etched.By the first metal layer 301 connecting PCB board in data side metal level 3, scan-side gold
Belong to layer periphery and be provided with COF, between data side metal level 3 and pcb board, also be provided with COF, PCB
Public voltage signal is imported on array base palte by plate by COF.
Data side metal level and scan-side metal level can also be made by following step, optionally,
As it is shown in figure 5, step S1 specifically includes following steps:
S104, the periphery, pixel display area of described array base palte formed the first metal layer, by one
The first metal layer of described pixel display area peripheral data signal input side is performed etching by road light shield.
Array base palte is formed one layer of metal level being used for preparing scan line, this metal level is defined
For the first metal layer.Perform etching on the first metal layer, in pixel display area, form scan line,
Being etched by the first metal layer of pixel display area peripheral data signal input side, now pixel shows simultaneously
Show that periphery, district scanning signal input side remains with the first metal layer.
S105, on described array base palte, form the first sealing coat, cover on described pixel by light and show
Show and form through hole on the first sealing coat scanning signal input side that district is peripheral.
Array base palte is formed the first sealing coat, at pixel display area peripheral data signal input side,
Owing to the first metal layer is etched, the first sealing coat is deposited on substrate；Outside pixel display area
Enclosing scanning signal input side, the first sealing coat covers on the first metal layer.Covered on by one light
Through hole is formed on first sealing coat of the scanning signal input side that described pixel display area is peripheral.
S106, on described first sealing coat, form the second metal level.
First sealing coat is formed the second metal level and forms data wire in pixel display area
Metal level together, the second metal level be same metal level for forming the metal level of data wire.
Second metal level is formed on the first sealing coat, the scanning peripheral in described pixel display area
Signal input side, the second metal level is electrically connected with the first metal layer by the through hole on the first sealing coat,
Form the scan-side metal level of scanning signal input side.The data letter peripheral in described pixel display area
Second metal level of number input side forms data side metal level, i.e. data side metal level and the second metal
Layer is arranged with layer.As shown in figures 6 a and 6b, Fig. 6 a is the structural representation of scan-side metal level 4
Figure, scan-side metal level 4 include the first metal layer 401, first that sets gradually from bottom to up every
Absciss layer 403 and the second metal level 402, the first metal layer 401 is by the first sealing coat 403
Through hole and the second metal level 402 electrically connect；Fig. 6 b is the structural representation of data side metal level 3,
Data side metal level 3 is the second metal level 402, data side metal level 3 and the second metal level 402
Arrange with layer；It is the first sealing coat 403, herein the first sealing coat 403 below data side metal level 3
Can also be etched in step S105.By the first metal layer 401 in scan-side metal level 4
Connecting PCB board, data side metal level 3 (being equal to the second metal level 402) connecting PCB board.
Based on above-mentioned data side metal level and the preparation method of scan-side metal level, as it is shown in fig. 7,
Step S3 specifically includes following steps:
S301, on described second metal level, form the second sealing coat, on described second sealing coat
Form flatness layer, cover on formation through hole on described flatness layer by one light.
Second metal level is formed the second sealing coat, the second sealing coat is formed flatness layer, right
Do not affect the second sealing coat when flatness layer performs etching, now, the second sealing coat does not has through hole.
S302, on described flatness layer formed common electrode layer, cover on described public by one light
Through hole is formed on electrode layer.
Flatness layer deposits common electrode layer, is covered on by one light and in common electrode layer, form one
The through hole that individual and on flatness layer through hole is corresponding, the position of the through hole in common electrode layer is with smooth
The position consistency of the through hole on layer.Optionally, the aperture of the through hole in common electrode layer is more than smooth
The aperture of the through hole on layer.
S303, in described common electrode layer, form the 3rd sealing coat, existed by one light shield simultaneously
Through hole, described 3rd sealing coat and described is formed on described 3rd sealing coat and described second sealing coat
The position consistency of the through hole in the position of through hole and described common electrode layer on second sealing coat, simultaneously
By with along with on described 3rd sealing coat, form another through hole.
Covered on by one light and on the 3rd sealing coat and the second sealing coat, concurrently form corresponding leading to
Hole, meanwhile, by with along with light shield on the 3rd sealing coat, form another through hole.
S304, on described 3rd sealing coat formed pixel electrode layer.
Pixel electrode layer is peripheral in described pixel display area, can be with the picture in described pixel display area
Element electrode concurrently forms.Pixel electrode layer is by another through hole on the 3rd sealing coat and public electrode
Layer electrical connection.
Common electrode layer and the electrical communication path of data side metal level and scan-side metal level are arranged
Pixel electrode layer, position, common electrode layer and the number that common electrode layer electrically connects with pixel electrode layer
The position electrically connected with scan-side metal level according to position and the common electrode layer of the electrical connection of side metal level
Putting all has multiple, and the position of the plurality of electrical connection all has in the periphery, pixel display area of array base palte point
Cloth, it is possible to make the more stable homogeneous of the common electric voltage in common electrode layer.
By above-mentioned step S3, then on array base palte, obtain data side metal level and scan-side gold
Belong to the structure that layer electrically connects respectively with common electrode layer.With reference to Fig. 8 a, data side metal level be under
Supreme the first metal layer the 301, first sealing coat 303 set gradually and the second metal level 302,
The first metal layer 301 is by the through hole 3031 on the first sealing coat 303 and the second metal level 302
Electrical connection, the second metal level 302 is sequentially provided with the second sealing coat 9, flatness layer 10, common electrical
Pole layer the 11, the 3rd sealing coat 12 and pixel electrode layer 13, wherein, pixel electrode layer 13 is at picture
Element viewing area is peripheral, the through hole on the second sealing coat 9 and one of them on the 3rd sealing coat 12
Through hole 1201 be by with along with light shield formed, the second metal level 302 is by the second sealing coat
Through hole 1001 on the through hole 901 of 303 and flatness layer 100, and on the 3rd sealing coat 12
One of them through hole 1201 electrically connects with pixel electrode layer 13, and pixel electrode layer 13 is by the 3rd
Another through hole 1202 on sealing coat 12 electrically connects with common electrode layer 11.Fig. 9 a is Fig. 8 a
The floor map that shown data side metal level electrically connects with common electrode layer, data signal inputs
For longitudinal input, dash area is the common electrode layer 11 on array base palte, the first metal layer 301
Connecting PCB board, pcb board connects public voltage source, the common electrical that public voltage source output is constant
Pressure signal, public voltage signal is through the first metal layer 301, by the through hole on the first sealing coat
3031 are transferred to the second metal level 302, by the through hole 901 on the second sealing coat 9, smooth
Through hole 1001 on layer 10 and the through hole 1201 on the 3rd sealing coat 12 import pixel electrode layer 13,
Common electrode layer 11 is imported again by another through hole 1202 of the 3rd sealing coat 12.With reference to Fig. 8 b,
Scan-side metal level 4 is the second metal level 302, the structure on scan-side metal level 4 and Fig. 8 a
Structure on middle data side metal level is identical.Fig. 9 b be scan-side metal level shown in Fig. 8 b 4 with
The floor map of common electrode layer 11 electrical connection, scanning signal input is laterally input, shade
Part is common electrode layer 11, and scan-side metal level periphery is provided with COF, data side metal level 3
And also being provided with COF between pcb board, public voltage signal is imported data by COF by pcb board
On side metal level 3 and scan-side metal level 4, public voltage signal is scanned through side metal level 4 (
Two metal levels 302), then by leading on the through hole 901 on the second sealing coat 9, flatness layer 10
Through hole 1201 on hole 1001 and the 3rd sealing coat 12 imports pixel electrode layer 13, then by the
Another through hole 1202 of three sealing coats 12 imports common electrode layer.With reference to Fig. 8 c, scan-side metal
Layer 4 is the first metal layer the 401, first sealing coat 403 and the second gold medal set gradually from bottom to up
Belonging to layer 402, the hierarchical structure on scan-side metal level 4 is identical with Fig. 8 a, and here is omitted.
Fig. 9 c is the plane signal that the scan-side metal level 4 shown in Fig. 8 c is connected with common electrode layer electricity 11
Figure, scans signal input for laterally shown in input, the transmission means of public voltage signal and Fig. 9 a
The common electric voltage transmission of the floor map that data side metal level 3 electrically connects with common electrode layer 11
Mode identical, here is omitted.With reference to Fig. 8 d, data side metal level 3 is the second metal
Layer 402, the hierarchical structure on data side metal level 3 is identical with Fig. 8 b, and here is omitted.Figure
9d is the floor map that the data side metal level 3 shown in Fig. 8 d electrically connects with common electrode layer 11,
Data signal input is longitudinally input, the transmission means of public voltage signal and the number shown in Fig. 9 b
The common electric voltage transmission of the floor map electrically connected with common electrode layer 11 according to side metal level 4
Mode is identical, and here is omitted.
In Fig. 9 a, Fig. 9 b, Fig. 9 c and Fig. 9 d, due to the through hole 901 on the second sealing coat 9
It is to be formed by same light shield with the through hole 1201 on the 3rd sealing coat 12, so the second sealing coat
Through hole 901 on 9 and the through hole 1201 on the 3rd sealing coat 12 are overlapped, therefore Fig. 9 a,
Fig. 9 b, Fig. 9 c and Fig. 9 d only mark the through hole 1201 located on the 3rd sealing coat 12.
The preparation method of array base palte of the present invention is by outside the pixel display area of described array base palte
The data signal input side enclosed forms data side metal level, and scanning signal input side forms scan-side gold
Belong to layer；Described array base palte is formed common electrode layer；Peripheral by institute in described pixel display area
State data side metal level and described scan-side metal level electrically connects with described common electrode layer respectively.This
Invent the data side metal level peripheral by pixel display area and scan-side metal level is array base palte
Common electrode layer provide common electric voltage, it is not necessary in pixel display area make public electrode wire,
The opening of display panels can not be affected while providing common electric voltage for common electrode layer
Rate, improves display quality.
The foregoing is only embodiments of the invention, not thereby limit the scope of the claims of the present invention,
Every equivalent structure utilizing description of the invention and accompanying drawing content to be made or equivalence flow process conversion, or
Directly or indirectly being used in other relevant technical fields, the patent being the most in like manner included in the present invention is protected
Protect scope.
Claims (10)
1. the manufacture method of the array base palte of a FFS mode, it is characterised in that described array base
Plate definition has pixel display area；
Described manufacture method includes:
The data signal input side peripheral in the pixel display area of described array base palte forms data side
Metal level, scanning signal input side forms scan-side metal level；
Described array base palte is formed common electrode layer；
Peripheral by described data side metal level and described scan-side metal level in described pixel display area
Electrically connect with described common electrode layer respectively；
Wherein, the position that described data side metal level electrically connects with described common electrode layer has some,
Or adjacent border contacts continuously with reality between described data side metal level and described common electrode layer
Now electrically connect；The position that described scan-side metal level electrically connects with described common electrode layer has some,
Or adjacent border contacts continuously with reality between described scan-side metal level and described common electrode layer
Now electrically connect.
Manufacture method the most according to claim 1, it is characterised in that described data side gold
Belong to layer and described scan-side metal level and the scan line in described pixel display area and/or data wire
Metal level is together formed；
Described common electrode layer covers described pixel display area, and peripheral in described pixel display area
At least partly cover described data side metal level and described scan-side metal level.
Manufacture method the most according to claim 1, it is characterised in that described in described battle array
The data signal input side formation data side metal level that the pixel display area of row substrate is peripheral, scanning
Signal input side formed scan-side metal level particularly as follows:
The first metal layer is formed, by one light in the periphery, pixel display area of described array base palte
Cover the first metal layer to periphery, described pixel display area scanning signal input side to perform etching；
Described array base palte is formed the first sealing coat, covers on described pixel by one light and show
Show and form through hole on the first sealing coat of the peripheral data signal input side in district；
Described sealing coat is formed the second metal level；The data peripheral in described pixel display area
Signal input side, described second metal level is by the through hole on described first sealing coat and described the
One metal level electrical connection, forms the data side metal level of data signal input side, in described pixel
Second metal level of the scanning signal input side that viewing area is peripheral forms sweeping of scanning signal input side
Retouch side metal level；
Wherein, the metal level that described the first metal layer concurrently forms with pixel display area interscan line,
The metal level that described second metal level concurrently forms with data wire in pixel display area.
Manufacture method the most according to claim 1, it is characterised in that described in described battle array
The data signal input side formation data side metal level that the pixel display area of row substrate is peripheral, scanning
Signal input side formed scan-side metal level particularly as follows:
The first metal layer is formed, by light shield pair in the periphery, pixel display area of described array base palte
The first metal layer of described pixel display area peripheral data signal input side performs etching；
Described array base palte is formed the first sealing coat, covers on described pixel display area by light
Through hole is formed on first sealing coat of peripheral data signal input side；
Described sealing coat forms the second metal level, the scanning peripheral in described pixel display area
Signal input side, described second metal level is by the through hole on described first sealing coat and described the
One metal level electrical connection, forms the scan-side metal level of scanning signal input side, in described pixel
Second metal level of the data signal input side that viewing area is peripheral forms the number of data signal input side
According to side metal level；
Wherein, the metal level that described the first metal layer concurrently forms with pixel display area interscan line,
The metal level that described second metal level concurrently forms with data wire in pixel display area.
5. according to the manufacture method described in claim 3 or 4, it is characterised in that described in institute
State pixel display area peripheral by described data side metal level and described scan-side metal level respectively with institute
State common electrode layer electrical connection particularly as follows:
Described second metal level forms the second sealing coat, described second sealing coat is formed flat
Smooth layer, covers on formation through hole on described flatness layer by one light；
Described flatness layer is formed common electrode layer, covers on described common electrode layer by one light
Upper formation through hole, the position of the through hole in described common electrode layer and the through hole on described flatness layer
Position consistency；
Described common electrode layer forms the 3rd sealing coat, by one light shield simultaneously described the
On three sealing coats and described second sealing coat formed through hole, described 3rd sealing coat and described second every
On absciss layer, the position of through hole and the position consistency of the through hole in described common electrode layer, pass through same simultaneously
Another through hole is formed together on described 3rd sealing coat；
On described 3rd sealing coat formed pixel electrode layer, described pixel electrode layer by described separately
One through hole electrically connects with described common electrode layer, and wherein, described pixel electrode layer shows in described pixel
Show that district is peripheral, concurrently form with the pixel electrode in described pixel display area.
6. the array base palte of a FFS mode, it is characterised in that the definition of described array base palte has picture
Element viewing area, and at least on described pixel display area, it is provided with common electrode layer；
The data signal input side of the periphery, pixel display area of described array base palte is provided with data side gold
Belonging to layer, scanning signal input side is provided with scan-side metal level, described data side metal level and described sweep
Retouch the side metal level the most described common electrode layer of all electricity, provide common electric voltage for described common electrode layer；
Wherein, the position that described data side metal level electrically connects with described common electrode layer has some,
Or adjacent border contacts continuously with reality between described data side metal level and described common electrode layer
Now electrically connect；The position that described scan-side metal level electrically connects with described common electrode layer has some,
Or adjacent border contacts continuously with reality between described scan-side metal level and described common electrode layer
Now electrically connect.
Array base palte the most according to claim 6, it is characterised in that described data side gold
Belong to layer and described scan-side metal level is respectively connected with pcb board, described pcb board and public voltage source
Connect.
Array base palte the most according to claim 7, it is characterised in that described data side gold
Belong to the first metal layer and the second metal level that layer includes arranging from bottom to up, described scan-side metal
Arrange with layer with described second metal level；Or
Described scan-side metal level includes the first metal layer and the second metal level arranged from bottom to up,
Described data side metal level is arranged with layer with described second metal level；
Wherein, described the first metal layer is the metal concurrently formed with pixel display area interscan line
Layer, described second metal level is the metal level concurrently formed with data wire in pixel display area.
Array base palte the most according to claim 8, it is characterised in that described data side gold
Belong to layer and described scan-side metal level be respectively connected with pcb board particularly as follows:
In described data side metal level, the most described the first metal layer connects described pcb board；Or
In described scan-side metal level, the most described the first metal layer connects pcb board.
Array base palte the most according to claim 8, it is characterised in that described data side
Metal level and the described scan-side metal level the most described common electrode layer of all electricity particularly as follows:
In described data side metal level or described scan-side metal level, described the first metal layer and institute
State and between the second metal level, be provided with the first sealing coat, described second metal level by described first every
Through hole on absciss layer electrically connects with described the first metal layer；
The second sealing coat, flatness layer, public it is sequentially provided with from bottom to up on described second metal level
Electrode layer, the 3rd sealing coat and pixel electrode layer, described second metal level by described second every
Through hole on absciss layer, described flatness layer and described 3rd sealing coat is electrically connected with described pixel electrode layer
Connecing, described pixel electrode layer and described common electrode layer are by another on described 3rd sealing coat
Through hole electrically connects, it is achieved described second metal level electrically connects with described common electrode layer；
Described pixel electrode layer is peripheral, with the picture in described pixel display area in described pixel display area
Element electrode concurrently forms.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020015002A (en) * | 2000-07-11 | 2002-02-27 | 가네꼬 히사시 | Liquid crystal display unit having pixel electrode encircled with partition wall and process for fabrication thereof |
| CN102116981A (en) * | 2009-12-30 | 2011-07-06 | 乐金显示有限公司 | Thin film transistor array substrate and method for fabricating the same |
| CN102466936A (en) * | 2010-11-04 | 2012-05-23 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display and manufacturing method of array substrate |
| CN103474432A (en) * | 2013-08-28 | 2013-12-25 | 合肥京东方光电科技有限公司 | Array substrate and preparation method and display device of array substrate |
| US20140284574A1 (en) * | 2013-03-20 | 2014-09-25 | Samsung Display Co., Ltd. | Display apparatus and method of manufacturing the same |
-
2016
- 2016-07-25 CN CN201610589138.9A patent/CN105974691B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020015002A (en) * | 2000-07-11 | 2002-02-27 | 가네꼬 히사시 | Liquid crystal display unit having pixel electrode encircled with partition wall and process for fabrication thereof |
| CN102116981A (en) * | 2009-12-30 | 2011-07-06 | 乐金显示有限公司 | Thin film transistor array substrate and method for fabricating the same |
| CN102466936A (en) * | 2010-11-04 | 2012-05-23 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display and manufacturing method of array substrate |
| US20140284574A1 (en) * | 2013-03-20 | 2014-09-25 | Samsung Display Co., Ltd. | Display apparatus and method of manufacturing the same |
| CN103474432A (en) * | 2013-08-28 | 2013-12-25 | 合肥京东方光电科技有限公司 | Array substrate and preparation method and display device of array substrate |
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