CN103474348A - Punch-through groove Schottky device structure and manufacturing method thereof - Google Patents
Punch-through groove Schottky device structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 94
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 91
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- 238000000034 method Methods 0.000 claims abstract description 42
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
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- 239000004020 conductor Substances 0.000 claims abstract description 11
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Abstract
The invention provides a punch-through groove Schottky device structure and a manufacturing method thereof. The punch-through groove Schottky device structure comprises an N-type heavily doped silicon chip, an N-type lightly doped silicon epitaxial layer bound to the surface of the N-type heavily doped silicon chip, at least two grooves which at least penetrate through the silicon epitaxial layer, silica layers formed on the surfaces of the grooves, conductive material layers filled in the grooves, a metal silicide layer formed on the surface of the silicon epitaxial layer, and a positive electrode layer formed on the surface of the metal silicide layer. The grooves of which the depths completely exceed the thickness of the silicon epitaxial layer are formed according to the advantage of the thickness of the silicon epitaxial layer. Under the condition that the thickness of a gate oxide layer is not increased, the reverse breakdown capacity is improved, the forward conductive voltage drop is not increased simultaneously, and the device performance is optimized. The punch-through groove Schottky device structure is compatible with a traditional complementary metal oxide semiconductor (CMOS) process and is suitable for industrial production.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of manufacture method of punch trench schottky device structure.
Background technology
Along with the development of semiconductor technology, power device, as a kind of new device, is widely used in the fields such as disk drive, automotive electronics.Power device needs to bear larger voltage, electric current and power termination.And the devices such as existing MOS transistor can't meet the demand, therefore, in order to meet the needs of application, various power devices become the focus of concern.
Schottky diode is noble metal (gold, silver, aluminium, platinum etc.) for anodal, take N type semiconductor as negative pole, utilizes the potential barrier formed on the two contact-making surface to have rectification characteristic and the metal-semiconductor device made.Because exist a large amount of electronics in N type semiconductor, the free electron of minute quantity is only arranged, so electronics just spreads in low silicon metal to concentration high N type semiconductor from concentration in the silicon metal.Obviously, in the silicon metal, there is no hole, just do not exist yet hole from metal the diffusion motion to N type semiconductor.Along with electronics constantly is diffused into noble metal from N type semiconductor, N type semiconductor surface electronic concentration reduces gradually, and surface electrical neutrality is destroyed, so just form potential barrier, its direction of an electric field is N type semiconductor → noble metal.But, under this electric field action, the electronics in noble metal also can produce the drift motion from noble metal → N type semiconductor, thereby weakened the electric field formed due to diffusion motion.Behind the space charge region of setting up one fixed width, the electron drift motion that electric field the causes electrons spread motions that cause different from concentration reach relative balance, have just formed Schottky barrier.Schottky diode is a kind of low-power consumption, ultra-speed semiconductor device.Outstanding feature is reverse recovery time extremely short (may diminish to several nanoseconds), and forward conduction voltage drop is low.It is multiplex makes high frequency, low pressure, large current commutates diode, fly-wheel diode, protection diode, also is used in the circuit such as microwave communication and makes rectifier diode, the small-signal detector diode is used.More common in communication power supply, frequency converter etc.
Power schottky device is a kind of semiconductor two terminal device for large current commutates, power schottky device commonly used is made by the schottky junction between metal silicide and low-doped N-type silicon at present, and metal silicide can be platinum silicon compound, titanium-silicon compound, nickel-silicon compound and chrome-silicon compound etc.In recent years, due to the development of trench technique, various slot type structures are used to the earth leakage protective ring of production unit Schottky junction structure, the groove type MOS structure of employing as usual etc.The area of conventional P N knot guard ring has been dwindled in the employing of groove type MOS structure, when the chip used area of device is identical, can reduce the forward conduction voltage drop of device.
The gash depth of MOS structure on epitaxial loayer commonly used is all the thickness that is less than epitaxial loayer, on identical epitaxial loayer, and in order to obtain higher reverse breakdown ability, can only be by increasing the thickness of gate oxide; But from technique, use thick oxide layer need to increase groove width, this has just reduced the effective area of device forward conduction, thereby can increase forward conduction voltage.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of punch trench schottky device structure and manufacture method thereof, for providing a kind of when improving Schottky reverse breakdown ability, do not increase punch trench schottky device structure and the manufacture method thereof of forward conduction voltage drop.
Reach for achieving the above object other relevant purposes, the invention provides a kind of manufacture method of punch trench schottky device structure, at least comprise the following steps:
1) provide a N-type heavily doped silicon chip, in described substrate surface, form the lightly doped silicon epitaxy layer of N-type;
2) form at least two grooves that at least run through described silicon epitaxy layer;
3) form silicon dioxide layer in the surface of described groove;
4) fill the full conductive layer bed of material in described groove;
5) form schottky metal layer in described silicon epitaxy layer surface, and make described schottky metal layer react the formation metal silicide layer with described silicon epitaxy layer by Technology for Heating Processing;
6) form the front electrode layer in described metal silicide layer surface.
As a kind of preferred version of the manufacture method of punch trench schottky device structure of the present invention, a kind of in the TiN/AlSiCu/Ti/TiN/Ti/Ni/Ag lamination, TiN/AlSi/Ti/TiN/Ti/Ni/Ag lamination and the TiN/Al/Ti/TiN/Ti/Ni/Ag lamination that stack gradually from bottom to top of described front electrode layer.
As a kind of preferred version of the manufacture method of punch trench schottky device structure of the present invention, the thickness of the lightly doped silicon epitaxy layer of described N-type is 2～20 μ m, and ion doping concentration is 10
14～10
17/ cm
3.
As a kind of preferred version of the manufacture method of punch trench schottky device structure of the present invention, the width of described groove is 0.18～0.8 μ m, and described groove runs through described silicon epitaxy layer and extends to described silicon chip certain depth.
As a kind of preferred version of the manufacture method of punch trench schottky device structure of the present invention, described conductive material layer is the heavily doped polysilicon layer of N-type, and the doping content of described polysilicon layer is 10
19～10
21/ cm
3.
As a kind of preferred version of the manufacture method of punch trench schottky device structure of the present invention, the material of described schottky metal layer is Pt, Ni, Ti, Cr, W, Mo or Co.
As a kind of preferred version of the manufacture method of punch trench schottky device structure of the present invention, further comprising the steps of:
7) adopt photoetching process to carry out etching to the front electrode layer, form the front electrode figure, and, at positive deposit protective layer medium, again adopt photoetching process to the etching of carrying out property of protective layer medium, form positive lead-in wire graph window;
8) attenuate is carried out in the back side of the heavily doped silicon chip of described N-type, then at the heavily doped substrate back of described N-type, form the Ti/Ni/Ag lamination, after the heating alloying, form backplate.
The present invention also provides a kind of punch trench schottky device structure, comprising:
The heavily doped silicon chip of N-type;
The lightly doped silicon epitaxy layer of N-type, be incorporated into described N-type heavy doping silicon chip surface;
At least two grooves, at least run through described silicon epitaxy layer;
Silicon dioxide layer, be formed at described flute surfaces;
Conductive material layer, be filled in described groove;
Metal silicide layer, be formed at described silicon epitaxy layer surface; And
The front electrode layer, be formed at described metal silicide layer surface.
As a kind of preferred version of punch trench schottky device structure of the present invention, a kind of in the TiN/AlSiCu/Ti/TiN/Ti/Ni/Ag lamination, TiN/AlSi/Ti/TiN/Ti/Ni/Ag lamination and the TiN/Al/Ti/TiN/Ti/Ni/Ag lamination that stack gradually from bottom to top of described front electrode layer.
As a kind of preferred version of punch trench schottky device structure of the present invention, the thickness of the lightly doped silicon epitaxy layer of described N-type is 2～20 μ m, and ion doping concentration is 10
14～10
17/ cm
3.
As a kind of preferred version of punch trench schottky device structure of the present invention, the width of described groove is 0.18～0.8 μ m, and described groove runs through described silicon epitaxy layer and extends to described silicon chip certain depth.
As a kind of preferred version of punch trench schottky device structure of the present invention, described conductive material layer is the heavily doped polysilicon layer of N-type, and the doping content of described polysilicon layer is 10
19～10
21/ cm
3.
As mentioned above, the invention provides a kind of punch trench schottky device structure and manufacture method thereof, comprising: the heavily doped silicon chip of N-type; The lightly doped silicon epitaxy layer of N-type, be incorporated into described N-type heavy doping silicon chip surface; At least two grooves, at least run through described silicon epitaxy layer; Silicon dioxide layer, be formed at described flute surfaces; Conductive material layer, be filled in described groove; Metal silicide layer, be formed at described silicon epitaxy layer surface; And the front electrode layer, be formed at described metal silicide layer surface.The present invention utilizes the advantage of silicon epitaxy layer thickness, produce the degree of depth and surpass the groove of described silicon epitaxy layer thickness fully, when not improving gate oxide thickness, improved the reverse breakdown ability, can not increase forward conduction voltage drop, be conducive to the optimization of device performance simultaneously.The present invention and traditional cmos process compatibility, be applicable to industrial production.
The accompanying drawing explanation
Fig. 1 is shown as the steps flow chart schematic diagram of the manufacture method of punch trench schottky device structure of the present invention.
Fig. 2～Fig. 3 is shown as the structural representation that the manufacture method step 1) of punch trench schottky device structure of the present invention presents.
Fig. 4 is shown as the manufacture method step 2 of punch trench schottky device structure of the present invention) structural representation that presents.
Fig. 5 is shown as the structural representation that the manufacture method step 3) of punch trench schottky device structure of the present invention presents.
Fig. 6～Fig. 7 is shown as the structural representation that the manufacture method step 4) of punch trench schottky device structure of the present invention presents.
Fig. 8～Fig. 9 is shown as the structural representation that the manufacture method step 5) of punch trench schottky device structure of the present invention presents.
Figure 10 is shown as the structural representation that the manufacture method step 6) of punch trench schottky device structure of the present invention presents.
The element numbers explanation
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to Fig. 1～Figure 10.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy in graphic and only show with assembly relevant in the present invention but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
As shown in Fig. 1～Figure 10, the present embodiment provides a kind of manufacture method of punch trench schottky device structure, at least comprises the following steps:
As shown in FIG. 1 to 3, at first carry out step 1) S11, provide a N-type heavily doped silicon chip 101, in described substrate surface, form the lightly doped silicon epitaxy layer 102 of N-type.
As example, the resistivity of the heavily doped silicon chip 101 of described N-type is no more than 0.01 ohmcm, and the thickness of the lightly doped silicon epitaxy layer 102 of described N-type is that between 2 μ m to 20 μ m, ion doping concentration is 10
14～10
17/ cm
3between, in the present embodiment, the resistivity of the heavily doped silicon chip 101 of described N-type is 0.005 ohmcm, and the thickness of the lightly doped silicon epitaxy layer 102 of described N-type is 20 μ m, and ion doping concentration is 10
15/ cm
3.
As shown in Fig. 1 and Fig. 4, then carry out step 2) S12, form at least two grooves 103 that at least run through described silicon epitaxy layer 102.
As example, adopt the described silicon epitaxy layer 102 of dry etch process etching and described silicon chip 101, formation runs through described silicon epitaxy layer 102 and extends to the groove 103 of described silicon chip 101 certain depths, this degree of depth can be between 2～20 μ m, in the present embodiment, the degree of depth that described groove 103 extends to described silicon chip 101 is 10 μ m, certainly, this degree of depth also can exceed this scope, can determine according to device performance.The width of the described groove 103 of described groove 103 is 0.18～0.8 μ m, and in the present embodiment, the width of described groove 103 is 0.5 μ m.
The flat shape of described groove 103 can be trap shape, continuous strip, discontinuous strip or the shapes such as the rectangle sealed, circle.The cross sectional shape of described groove 103 can be circular-arc polygon etc. for rectangle, trapezoidal or bottom.
As shown in Figures 1 and 5, then carry out step 3) S13, in the surface of described groove 103, form silicon dioxide layer 104.
As example, form silicon dioxide layers 104 by thermal oxidation process in the surperficial and described silicon epitaxy layer of described groove 103 102 surfaces, the thickness of described silicon dioxide layer 104 is between 5 nanometer to 250 nanometers.
As shown in Fig. 1 and Fig. 6～Fig. 7, then carry out step 4) S14, in the full conductive layer bed of material of the interior filling of described groove 103.
As example, the silicon dioxide layer heavily doped polysilicon layer of 104 surface deposition N-type of silicon dioxide layer in described groove 103 104 surfaces and described silicon epitaxy layer 102 is until fill up described groove 103, and the doping content of described polysilicon layer is 10
19～10
21/ cm
3, then adopt back carving technology that the polysilicon layer on described silicon epitaxy layer 102 surfaces and silicon dioxide layer 104 are removed, expose described silicon epitaxy layer 102, and described silicon epitaxy layer 102 surfaces are cleaned.
As shown in Fig. 1 and Fig. 8～Fig. 9, then carry out step 5) S15, form schottky metal layer 106 in described silicon epitaxy layer 102 surfaces, and make described schottky metal layer 106 react formation metal silicide layer 107 with described silicon epitaxy layer 102 by Technology for Heating Processing.
As example, adopt sputtering technology to form schottky metal layer 106 in described silicon epitaxy layer 102 surfaces, then adopt the mode of rapid thermal treatment or furnace annealing to make described schottky metal layer 106 react formation metal silicide layer 107 with described silicon epitaxy layer 102, form schottky junction.
As example, the material of described schottky metal layer 106 is Pt, Ni, Ti, Cr, W, Mo or Co, and in the present embodiment, the material of described schottky metal layer 106 is Pt.
As shown in Fig. 1 and Figure 10, then carry out step 6) S16, form the front electrode layer in described metal silicide layer 107 surfaces.
As example, the TiN/AlSiCu/Ti/TiN/Ti/Ni/Ag lamination of described front electrode layer for stacking gradually from bottom to top, be followed successively by from bottom to top TiN layer 108, AlSiCu layer 109, Ti layer 110, TiN layer 111, Ti layer 112, Ni layer 113, reach Ag layer 114.
Certainly, in other embodiments, the TiN/AlSi/Ti/TiN/Ti/Ni/Ag lamination of described front electrode for stacking gradually from bottom to top, described front electrode is followed successively by from bottom to top TiN layer, AlSi layer, Ti layer, TiN layer, Ti layer, Ni layer, reaches the Ag layer; Can be also the TiN/Al/Ti/TiN/Ti/Ni/Ag lamination stacked gradually from bottom to top, described front electrode be followed successively by from bottom to top TiN layer, Al layer, Ti layer, TiN layer, Ti layer, Ni layer, reaches the Ag layer.
As shown in Figure 1, then carry out step 7) S17, adopt photoetching process to carry out etching to the front electrode layer; form the front electrode figure; and, at positive deposit protective layer medium, again adopt photoetching process to the etching of carrying out property of protective layer medium, form positive lead-in wire graph window.
As shown in Figure 1, finally carry out step 8) S18, attenuate is carried out in the back side of the heavily doped silicon chip 101 of described N-type, then at the heavily doped substrate back of described N-type, form the Ti/Ni/Ag lamination, after the heating alloying, form backplate.
As shown in figure 10, the present embodiment also provides a kind of punch trench schottky device structure, comprising:
The heavily doped silicon chip 101 of N-type;
The lightly doped silicon epitaxy layer 102 of N-type, be incorporated into described N-type heavy doping silicon chip 101 surfaces;
At least two grooves 103, at least run through described silicon epitaxy layer 102;
The front electrode layer, be formed at described metal silicide layer 107 surfaces.
As example, the resistivity of the heavily doped silicon chip 101 of described N-type is no more than 0.01 ohmcm, and the thickness of the lightly doped silicon epitaxy layer 102 of described N-type is that between 2 μ m to 20 μ m, ion doping concentration is 10
14～10
17/ cm
3between, in the present embodiment, the resistivity of the heavily doped silicon chip 101 of described N-type is 0.005 ohmcm, and the thickness of the lightly doped silicon epitaxy layer 102 of described N-type is 20 μ m, and ion doping concentration is 10
15/ cm
3.
As example, described groove 103 runs through described silicon epitaxy layer 102 and extends to described silicon chip 101 certain depths, this degree of depth can be between 2～20 μ m, in the present embodiment, the degree of depth that described groove 103 extends to described silicon chip 101 is 10 μ m, certainly, this degree of depth also can exceed this scope, can determine according to device performance.The width of the described groove 103 of described groove 103 is 0.18～0.8 μ m, and in the present embodiment, the width of described groove 103 is 0.5 μ m.
The flat shape of described groove 103 can be trap shape, continuous strip, discontinuous strip or the shapes such as the rectangle sealed, circle.The cross sectional shape of described groove 103 can be circular-arc polygon etc. for rectangle, trapezoidal or bottom.
As example, the thickness of described silicon dioxide layer 104 is between 5 nanometer to 250 nanometers.
As example, described conductive material layer 105 is the heavily doped polysilicon layer of N-type, and the doping content of described polysilicon layer is 10
19～10
21/ cm
3.
As example, the metal material that forms described metal silicide is Pt, Ni, Ti, Cr, W, Mo or Co.
As example, the TiN/AlSiCu/Ti/TiN/Ti/Ni/Ag lamination of described front electrode layer for stacking gradually from bottom to top, be followed successively by from bottom to top TiN layer 108, AlSiCu layer 109, Ti layer 110, TiN layer 111, Ti layer 112, Ni layer 113, reach Ag layer 114.
Certainly, in other embodiments, the TiN/AlSi/Ti/TiN/Ti/Ni/Ag lamination of described front electrode for stacking gradually from bottom to top, described front electrode is followed successively by from bottom to top TiN layer, AlSi layer, Ti layer, TiN layer, Ti layer, Ni layer, reaches the Ag layer; Can be also the TiN/Al/Ti/TiN/Ti/Ni/Ag lamination stacked gradually from bottom to top, described front electrode be followed successively by from bottom to top TiN layer, Al layer, Ti layer, TiN layer, Ti layer, Ni layer, reaches the Ag layer.
Certainly, described punch trench schottky device structure also comprises the backplate that is incorporated into described silicon chip 101 back sides, in the present embodiment, and the alloy cpd that described backplate is comprised of Ti, Ni, Ag.
In addition, can be at device periphery zone deposit silicon dioxide separator, described electrode structure at right side covers this silicon dioxide separator zone from schottky device region extension part, forms the high voltage protective ring, further improves puncture voltage.
As mentioned above, the invention provides a kind of punch trench schottky device structure and manufacture method thereof, comprising: the heavily doped silicon chip 101 of N-type; The lightly doped silicon epitaxy layer 102 of N-type, be incorporated into described N-type heavy doping silicon chip 101 surfaces; At least two grooves 103, at least run through described silicon epitaxy layer 102; Silicon dioxide layer 104, be formed at described groove 103 surfaces; Conductive material layer 105, be filled in described groove 103; Metal silicide layer 107, be formed at described silicon epitaxy layer 102 surfaces; And the front electrode layer, be formed at described metal silicide layer 107 surfaces.The present invention utilizes the advantage of silicon epitaxy layer 102 thickness, produce the degree of depth and surpass the groove 103 of described silicon epitaxy layer 102 thickness fully, when not improving gate oxide thickness, improved the reverse breakdown ability, can not increase forward conduction voltage drop, be conducive to the optimization of device performance simultaneously.The present invention and traditional cmos process compatibility, be applicable to industrial production.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, be modified or be changed above-described embodiment.Therefore, such as in affiliated technical field, have and usually know that the knowledgeable, not breaking away from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (12)
1. the manufacture method of a punch trench schottky device structure, is characterized in that, at least comprises the following steps:
1) provide a N-type heavily doped silicon chip, in described substrate surface, form the lightly doped silicon epitaxy layer of N-type;
2) form at least two grooves that at least run through described silicon epitaxy layer;
3) form silicon dioxide layer in the surface of described groove;
4) fill the full conductive layer bed of material in described groove;
5) form schottky metal layer in described silicon epitaxy layer surface, and make described schottky metal layer react the formation metal silicide layer with described silicon epitaxy layer by Technology for Heating Processing;
6) form the front electrode layer in described metal silicide layer surface.
2. the manufacture method of punch trench schottky device structure according to claim 1 is characterized in that: a kind of in the TiN/AlSiCu/Ti/TiN/Ti/Ni/Ag lamination, TiN/AlSi/Ti/TiN/Ti/Ni/Ag lamination and the TiN/Al/Ti/TiN/Ti/Ni/Ag lamination that stack gradually from bottom to top of described front electrode layer.
3. the manufacture method of punch trench schottky device structure according to claim 1, it is characterized in that: the thickness of the lightly doped silicon epitaxy layer of described N-type is 2～20 μ m, and ion doping concentration is 10
14～10
17/ cm
3.
4. the manufacture method of punch trench schottky device structure according to claim 1, is characterized in that: described groove
Width is 0.18～0.8 μ m, and described groove runs through described silicon epitaxy layer and extends to described silicon chip certain depth.
5. the manufacture method of punch trench schottky device structure according to claim 1, it is characterized in that: described conductive material layer is the heavily doped polysilicon layer of N-type, and the doping content of described polysilicon layer is 10
19～10
21/ cm
3.
6. the manufacture method of punch trench schottky device structure according to claim 1, it is characterized in that: the material of described schottky metal layer is Pt, Ni, Ti, Cr, W, Mo or Co.
7. the manufacture method of punch trench schottky device structure according to claim 1 is characterized in that: further comprising the steps of:
7) adopt photoetching process to carry out etching to the front electrode layer, form the front electrode figure, and, at positive deposit protective layer medium, again adopt photoetching process to the etching of carrying out property of protective layer medium, form positive lead-in wire graph window;
8) attenuate is carried out in the back side of the heavily doped silicon chip of described N-type, then at the heavily doped substrate back of described N-type, form the Ti/Ni/Ag lamination, after the heating alloying, form backplate.
8. a punch trench schottky device structure is characterized in that: comprising:
The heavily doped silicon chip of N-type;
The lightly doped silicon epitaxy layer of N-type, be incorporated into described N-type heavy doping silicon chip surface;
At least two grooves, at least run through described silicon epitaxy layer;
Silicon dioxide layer, be formed at described flute surfaces;
Conductive material layer, be filled in described groove;
Metal silicide layer, be formed at described silicon epitaxy layer surface; And
The front electrode layer, be formed at described metal silicide layer surface.
9. punch trench schottky device structure according to claim 8 is characterized in that: a kind of in the TiN/AlSiCu/Ti/TiN/Ti/Ni/Ag lamination, TiN/AlSi/Ti/TiN/Ti/Ni/Ag lamination and the TiN/Al/Ti/TiN/Ti/Ni/Ag lamination that stack gradually from bottom to top of described front electrode layer.
10. punch trench schottky device structure according to claim 8, the thickness of the lightly doped silicon epitaxy layer of described N-type is 2～20 μ m, ion doping concentration is 10
14～10
17/ cm
3.
11. punch trench schottky device structure according to claim 8 is characterized in that: the width of described groove is 0.18～0.8 μ m, and described groove runs through described silicon epitaxy layer and extends to described silicon chip certain depth.
12. punch trench schottky device structure according to claim 8 is characterized in that: described conductive material layer is the heavily doped polysilicon layer of N-type, and the doping content of described polysilicon layer is 10
19～10
21/ cm
3.
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