CN103472115A - Ion-sensitive field effect transistor and preparation method thereof - Google Patents
Ion-sensitive field effect transistor and preparation method thereof Download PDFInfo
- Publication number
- CN103472115A CN103472115A CN2013103596892A CN201310359689A CN103472115A CN 103472115 A CN103472115 A CN 103472115A CN 2013103596892 A CN2013103596892 A CN 2013103596892A CN 201310359689 A CN201310359689 A CN 201310359689A CN 103472115 A CN103472115 A CN 103472115A
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- ion
- effect transistor
- field effect
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims description 8
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 239000004065 semiconductor Substances 0.000 claims abstract description 83
- 150000002500 ions Chemical class 0.000 claims abstract description 76
- 230000005669 field effect Effects 0.000 claims abstract description 35
- 239000012528 membrane Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 37
- 239000000377 silicon dioxide Substances 0.000 claims description 34
- 229910052681 coesite Inorganic materials 0.000 claims description 23
- 229910052906 cristobalite Inorganic materials 0.000 claims description 23
- 229910052682 stishovite Inorganic materials 0.000 claims description 23
- 229910052905 tridymite Inorganic materials 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 22
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 17
- 238000001312 dry etching Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Chemical compound O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 229910052593 corundum Inorganic materials 0.000 claims description 10
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 20
- 239000001257 hydrogen Substances 0.000 abstract description 20
- -1 hydrogen ions Chemical class 0.000 abstract description 20
- 238000005259 measurement Methods 0.000 abstract description 15
- 230000005672 electromagnetic field Effects 0.000 abstract description 7
- 239000010408 film Substances 0.000 description 28
- 230000000694 effects Effects 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 238000001179 sorption measurement Methods 0.000 description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000011161 development Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 229910021607 Silver chloride Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- HKZLPVFGJNLROG-UHFFFAOYSA-M silver monochloride Chemical compound [Cl-].[Ag+] HKZLPVFGJNLROG-UHFFFAOYSA-M 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a transistor, and discloses an ion-sensitive field effect transistor. The ion-sensitive field effect transistor comprises a semiconductor substrate 202, and a source 101 and a drain 102 which are located on the semiconductor substrate 202 and formed by doping; a groove structure etched to the interior of the semiconductor substrate 202 is arranged between the source 101 and the drain 102, an ion-sensitive membrane 103 is formed on the surface of the groove structure, and thus a gate insulating layer is formed. Because the groove structure is etched to the interior of the semiconductor substrate 202 with a certain depth, the structure can play a role of shielding and protecting measured hydrogen ions in a solution 201, so that interference of an electromagnetic field in the surrounding environment can be avoided when the concentration of the hydrogen ions is measured, and thus the accuracy and the repeatability of measurement results are effectively improved.
Description
Technical Field
The invention relates to a field effect transistor, in particular to an ion sensitive field effect transistor and a preparation method thereof.
Background
In the prior art, the structure of an ion sensitive field effect transistor ISFET device is very similar to a metal oxide semiconductor field effect transistor MOSFET without a metal gate, as shown in fig. 1 and 2, a gate insulating layer of the ion sensitive field effect transistor ISFET device is a planar part between a source 101 and a drain 102, a sensitive layer 103 covered on the gate insulating layer is directly contacted with a solution 201 to be detected, and due to the existence of hydrogen ions in the solution 201 to be detected, a tiny Nernst response potential sensitive to the hydrogen ions is induced on the interface between an ion sensitive film 103 and the solution 201 to be detected:
the Nernst potential induced by more hydrogen ions in the solution is larger, the channel is more fully opened, and the source-drain current is larger. The concentration or activity of hydrogen ions in the solution 201 to be tested can be detected by measuring the source-drain current, and the pH value can be measured.
Because the concentration of hydrogen ions existing in the solution 201 is easily interfered by a surrounding electromagnetic field when being measured, in the prior art, because a gate insulating layer of an ISFET device is a plane area, the gate insulating layer cannot play a role of shielding the surrounding electromagnetic field from the hydrogen ions in the solution 201 to be measured, and moreover, the Nernst response potential between the ion sensitive film 103 and the interface of the solution 201 to be measured is very small, and a slight deviation can cause unstable measurement results, poor repeatability and low reliability.
In the prior art, the formation of the source and the drain also has a great defect, and the current process is to dope the positions corresponding to the source and the drain on the semiconductor substrate 202, and a space of a gate insulating layer is left in the middle, so that the source and the drain are doped to diffuse into a channel region, and the actual effective size of the channel is affected. The groove structure of the invention automatically separates the source electrode region from the drain electrode region, thus the size of the channel region can be accurately controlled.
Disclosure of Invention
The invention aims to provide an ion-sensitive field effect transistor and a preparation method thereof, which can prevent hydrogen ions in a detected solution from being interfered by an electromagnetic field in the surrounding environment when the transistor is used for detecting the pH value, so that the measurement result is more accurate and the repeatability is higher.
In order to solve the technical problem, the invention provides an ion sensitive field effect transistor, which comprises a semiconductor substrate, a groove extending into the semiconductor substrate, and a source electrode and a drain electrode which are positioned on the semiconductor substrate and formed by doping;
the groove is positioned between the source electrode and the drain electrode, and the depth of the groove is greater than the junction depth of the source electrode and the drain electrode;
the surface of the groove is provided with an ion sensitive film.
The invention also provides a preparation method of the ion sensitive field effect transistor, which comprises the following steps:
providing a semiconductor substrate;
doping is carried out on the semiconductor substrate to form a doped region;
etching a groove on the doped region and the semiconductor substrate, wherein the doped regions on two sides of the groove form a source electrode and a drain electrode; wherein the depth of the groove is greater than the junction depth of the source electrode and the drain electrode;
and generating an ion sensitive film on the surface of the groove.
Compared with the prior art, the ISFET is structurally improved, a groove is arranged between a source electrode and a drain electrode, the groove is etched into a semiconductor, the source electrode and the drain electrode are separated, an ion sensitive film is arranged on the surface of the groove, when the ISFET is used for detecting the pH value, a solution to be detected is injected into the groove, and a relatively closed space can be formed for the solution to be detected due to the fact that the etching depth of the groove is deep, so that the hydrogen ions in the solution to be detected can be shielded and protected, the hydrogen ion concentration can be prevented from being interfered by an electromagnetic field in the surrounding environment when being measured, and the accuracy and repeatability of a measuring result are effectively improved.
Preferably, in the invention, the doping region is defined on the surface of the whole semiconductor substrate through a photoetching process, then doping is carried out, a groove structure is formed at the corresponding position, and the doping region is divided into the source electrode and the drain electrode; in addition, the doping process does not generate defects formed by uneven doping between the source electrode and the drain electrode and the groove wall in the subsequent groove forming process.
Secondly, the ion sensitive film in the ion sensitive field effect transistor is a single-layer insulating medium layer, and the ion sensitive film material is SiO2、Si3N4、Al2O3Or Ta2O5These are away fromThe sub-sensitive membrane material is sensitive to hydrogen ions, has strong adsorption effect, high adsorption concentration and good sensitivity, and thus, the measurement result is more timely and effective.
Thirdly, the ion sensitive film in the ion sensitive field effect transistor can also be at least two insulating medium layers, wherein the layer in contact with the semiconductor substrate is made of silicon dioxide SiO2The material adopted by the outermost layer is silicon nitride Si3N4Aluminum oxide Al2O3Or tantalum pentoxide Ta2O5Any one of them. Because of SiO2The ion sensitive film has good binding property with the semiconductor substrate, and the surface adopts a material which is sensitive to hydrogen ions and has strong adsorption effect, so that the ion sensitive film can adopt a laminated structure, and the ion sensitive film not only has good binding property with the semiconductor substrate, but also has strong adsorption effect on the hydrogen ions.
In addition, the ion sensitive field effect transistor also comprises a source leading-out terminal, a drain leading-out terminal and a substrate leading-out terminal which are metal silicide contact regions respectively positioned on the source electrode, the drain electrode and the back surface of the semiconductor substrate so as to connect the source electrode, the drain electrode and the semiconductor substrate with an external circuit.
As a further improvement of the invention, before the doping of the semiconductor substrate, an insulating layer SiO is formed on the semiconductor substrate2Or from SiO2And Si3N4The source electrode and the drain electrode are well isolated from the solution to be detected on the semiconductor substrate by the insulating layer, the solution to be detected is prevented from permeating into the source electrode and the drain electrode area, leakage current is generated between the solution and the source electrode and the drain electrode, and the stability of the working state of the ion sensitive field effect transistor is further ensured.
As a further improvement of the present invention, the selection of the semiconductor substrate in the present invention is also important, and if the semiconductor substrate is P-type, the source and the drain are N-type doped; if the semiconductor substrate is N-type, the source and the drain are P-type doped. In the invention, the scheme that the substrate is P-type and the source electrode and the drain electrode are N-type doped is preferred, because the mobility of electrons is far greater than that of holes, the N-type doping with electrons as majority carriers is used as the source electrode and the drain electrode, and the current passing capability is much stronger; in addition, from the control point of view, the N-type ISFET can be started by positive voltage, and the use is convenient.
The source electrode and the drain electrode are positioned through the channel groove structure self-alignment effect, the precision control of the positions between the source electrode and the drain electrode and the channel is very accurate by adopting the mode, and the definition of the source electrode, the drain electrode and the channel region can be realized only through one step of glue homogenizing, exposure, development and etching.
In addition, the groove extending to the inside of the semiconductor substrate in the ion sensitive field effect transistor is formed by dry etching or a mode of combining wet etching and dry etching, and the groove is accurately and quickly etched by utilizing the advantages of good anisotropy, high etching rate and capability of transferring photoetching patterns with high fidelity of the dry etching; the wet etching and the dry etching are combined, so that some residual substances on the surface of the semiconductor substrate can be removed by the wet etching first, and then the grooves in the semiconductor substrate are etched by the dry etching, and the etching effect is more obvious.
Finally, the ion sensitive film involved in the invention is formed by thermal oxidation, chemical vapor deposition or atomic layer deposition, and compared with the method for forming the film, the method for forming the ion sensitive film is simpler and easier to implement.
Drawings
FIG. 1 is a schematic diagram of the working principle of an ISFET solid-state pH sensor in the prior art;
FIG. 2A is a schematic diagram of an ion sensitive field effect transistor according to a first embodiment of the present invention;
FIG. 2B is a schematic diagram of an external reference electrode during an ion sensitive field effect transistor test according to the first embodiment of the present invention;
FIG. 3A is a flow chart of a method for fabricating an ion sensitive field effect transistor according to a second embodiment of the present invention;
FIGS. 3B to 3K are schematic diagrams illustrating a method for fabricating an ion sensitive field effect transistor according to a second embodiment of the present invention;
FIG. 3L is a schematic diagram of an additional reference electrode during testing in a method for fabricating an ion sensitive field effect transistor according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solutions claimed in the claims of the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.
The first embodiment of the present invention relates to an ion sensitive field effect transistor, as shown in fig. 2A, the left drawing is a top view, and the right drawing is a schematic cross-sectional view corresponding to a-a' plane in the left drawing. The ion sensitive field effect transistor comprises a semiconductor substrate 202 and a doped region 203 formed on the semiconductor substrate 202 through doping, wherein a source electrode 101 and a drain electrode 102 are both positioned in the doped region 203, a groove structure extending into the semiconductor substrate 202 is arranged between the source electrode 101 and the drain electrode 102, an ion sensitive film 103 is generated on the surface of the groove, the groove structure and the ion sensitive film 103 jointly form a gate insulating layer on a channel, and metal silicide contact regions are respectively manufactured on the back surfaces of the source electrode 101, the drain electrode 102 and the semiconductor substrate 202 after the gate insulating layer is formed so as to connect the source electrode 101, the drain electrode 102 and the semiconductor substrate 202 with an external circuit.
In this embodiment, when the ISFET device is measured, the measured solution 201 is injected into the groove, a tiny Nernst response potential is generated on the interface between the ion sensitive film 103 and the measured solution 201, the Nernst potential causes a certain potential difference between the surface of the gate insulating layer and the source 101, when the potential difference increases to the threshold voltage of the transistor, the channel is opened, a fixed voltage is applied between the source 101 and the drain 102, a current is formed therebetween, the more hydrogen ions in the measured solution 201 induce a larger Nernst potential, the more the channel is opened, the larger the source-drain current is, because the above-mentioned Nernst response potential is very tiny, the potential measurement may not be accurate due to a small influence factor in the external environment, while the groove is deep in the embodiment, a relatively closed space may be formed for the measured solution, so that the function of shielding and protecting the hydrogen ions in the measured solution 201 can be achieved, the hydrogen ions are prevented from being interfered by electromagnetic fields in the surrounding environment during measurement, and the accuracy and the repeatability of the measurement result are effectively improved.
The forming process of the doped region 203 in this embodiment is different from the prior art, and includes doping in a predetermined region on the surface of the semiconductor substrate 202, forming a groove structure at a corresponding position, and separating the source 101 from the drain 102, so that the doping in the entire source and drain regions is relatively uniform, and the defect of the source 101 and the drain 102 due to uneven doping is avoided, which affects the device performance; in addition, in the subsequent groove forming process of the doping process, defects caused by uneven doping between the source electrode 101 and the drain electrode 102 and the groove wall can not occur. In addition, the doping of the semiconductor substrate may be implemented by using a conventional mature method such as ion implantation, which is not described herein again.
The ion sensitive membrane 103 in this embodiment is a single-layer insulating dielectric layer, and the ion sensitive membrane material is SiO2、Si3N4、Al2O3Or Ta2O5The ion sensitive membrane materials are sensitive to hydrogen ions, have strong adsorption effect, high adsorption concentration and good sensitivity, so that the detection is realizedThe quantitative result is more timely and effective. The ion sensitive film 103 may also be at least two insulating dielectric layers, wherein the layer in contact with the semiconductor substrate 202 is made of silicon dioxide SiO2Due to SiO2The surface layer is preferably made of silicon nitride (Si)3N4Aluminum oxide Al2O3Or tantalum pentoxide Ta2O5Any one of them. In this embodiment, the ion sensitive film 103 may be formed by thermal oxidation, chemical vapor deposition or atomic layer deposition, which are relatively simple and easy to implement, and have low requirements on film forming equipment, so as to reduce the manufacturing cost of the whole device.
In addition, the ISFET device of the present invention further includes an insulating layer 204, and the insulating layer 204 covers the region of the semiconductor substrate 202 where doping is not performed. The insulating layer 204 may be silicon dioxide, SiO2Silicon nitride Si3N4Or a stacked structure composed of them. If the insulating layer 204 is silicon dioxide SiO2It may be formed using a high temperature oxidation technique, a Tetraethylorthosilicate (TEOS) Low Pressure Chemical Vapor Deposition (LPCVD) technique, or a combination of both techniques. LPCVD SiO2With high-temperature thermal oxidation of SiO2Compared with the prior art, the film has loose quality, but can compensate the formation of thicker SiO by high-temperature oxidation technology to a certain extent2Stress and defects caused by layer formation and overhigh process temperature. Therefore, the combination of LPCVD technology and high-temperature oxidation technology can ensure SiO2The compactness of the film and the adhesive capacity with the semiconductor substrate 202 can improve the electrical property and the yield of the device.
The choice of the semiconductor substrate 202 is also important in the present invention, the semiconductor substrate 202 may be P-type or N-type, and if the semiconductor substrate 202 is P-type, the source 101 and the drain 102 are formed by doping; if the semiconductor substrate 202 is N-type, then it is the source 101 and drain 102 that are P-type formed by doping. In this embodiment, the P-type semiconductor substrate 202 is used, and the N-type source 101 and the N-type drain 102 are formed by doping, because the mobility of electrons is much higher than that of holes, the current passing capability is much stronger when the N-type doping with electrons as the majority carriers is used as the source 101 and the drain 102; in addition, from the control point of view, the N-type ISFET can be switched on by positive voltage, and the use is convenient.
In this embodiment, when the ISFET device performs measurement, a reference electrode 205 may be additionally inserted into the solution 201 to be measured, the reference electrode 205 is an Ag/AgCl reference electrode filled with 3.5M KCl solution, and the reference electrode 205 has the function of stabilizing the potential of the solution to be measured, thereby further improving the accuracy and reliability of the measurement result, as shown in fig. 2B.
A second embodiment of the present invention relates to a method for manufacturing an ion sensitive field effect transistor, and fig. 3A is a flowchart of the method for manufacturing an ion sensitive field effect transistor according to the present embodiment, and fig. 3B to 3K are schematic top views (left) corresponding to steps in the method for manufacturing an ion sensitive field effect transistor according to the present embodiment and schematic cross-sectional views (right) of a-a' plane in the corresponding top views. The following describes a method for manufacturing an ion sensitive field effect transistor according to this embodiment with reference to fig. 3A to 3K.
In step S1, a semiconductor substrate 202 is provided, and an insulating layer 204 is formed on the substrate, as shown in fig. 3A to 3C.
The semiconductor substrate 202 may be P-type or N-type, and if the semiconductor substrate 202 is P-type, the source 101 and the drain 102 are formed by doping; if the semiconductor substrate 202 is N-type, then it is the source 101 and drain 102 that are P-type formed by doping. In this embodiment, the P-type semiconductor substrate 202 is used, and the N-type source 101 and the N-type drain 102 are formed by doping, because the mobility of electrons is much higher than that of holes, the current passing capability is much stronger when the N-type doping with electrons as the majority carriers is used as the source 101 and the drain 102; in addition, from the control point of view, the N-type ISFET can be switched on by positive voltage, and the use is convenient.
Wherein, inAn insulating layer or a plurality of insulating layers may be formed on the semiconductor substrate; wherein the insulating layer is made of silicon dioxide SiO2Silicon nitride Si3N4Or a stacked structure composed of them. For example, the insulating layer 204 may be SiO2Can be formed by high temperature oxidation technique, Tetraethylorthosilicate (TEOS) Low Pressure Chemical Vapor Deposition (LPCVD) technique or a combination of the two techniques, using TEOSLPCVD technique to achieve SiO2The deposition on the surface of the semiconductor substrate compensates for the formation of thicker SiO by high-temperature oxidation technology to a certain extent2Too long layer time, too high process temperature, stress and defects. By adopting the reasonable application of TEOS LPCVD technology and high-temperature oxidation technology, SiO is ensured2The compactness of the film and the adhesive capacity with the semiconductor substrate 202 improve the electrical property and the yield of the device.
In step S2, doping is performed on the semiconductor substrate 202 to form a doped region 203.
Specifically, the step of doping the semiconductor substrate 202 to form the doped region 203 further includes the following sub-steps:
in step S201, a layer of photoresist 301 is coated on the insulating layer 204, as shown in fig. 3C. The layer of photoresist 301 may be spin coated over the insulating layer 204.
Step S202, preparing a strip pattern as shown in FIG. 3D by exposure and development processes to expose SiO to be removed2。
Step S203, etching off the exposed SiO in step S202 by dry etching or combination of wet etching and dry etching2The strip-shaped semiconductor substrate 202 is exposed, as shown in fig. 3E.
Step S204, doping the surface to form a strip-shaped doped region 203, where the doped region 203 lays a foundation for forming the source 101 and the drain 102 later, as shown in fig. 3F. If the semiconductor substrate 202 provided in step S1 is P-type, the doped region 203 is N-type after doping in this step; if the semiconductor substrate 202 provided in step S1 is N-type, the doped region 203 after doping is P-type. In this embodiment, the P-type semiconductor substrate 202 is used, and the N-type source 101 and the N-type drain 102 are formed by doping, because the mobility of electrons is much higher than that of holes, the current passing capability is much stronger when the N-type doping with electrons as the majority carriers is used as the source 101 and the drain 102; in addition, from the control point of view, the N-type ISFET can be switched on by positive voltage, and the use is convenient.
In step S3, a recess is etched in the doped region 203 and the semiconductor substrate 202 to form the source 101 and the drain 102.
Specifically, a groove is etched in the doped region 203 and the semiconductor substrate 202, and the step S3 of forming the source 101 and the drain 102 further includes the following sub-steps:
step S301, the photoresist 301 is removed, exposing the insulating layer 204 protected by the photoresist 301, as shown in fig. 3G.
Step S302, as shown in fig. 3H, performing glue leveling, alignment exposure, development and etching (i.e. repeating steps 201 to 203, and only replacing one mask), to obtain 4 (4 are shown in the schematic diagram, and actually there are many grooves) etched into the semiconductor substrate 202, where the etching depth of the groove is greater than the junction depth of the source 101 or the drain 102, so that the source 101 and the drain 102 are formed.
During measurement, the solution 201 to be measured is injected into the groove, and the groove can play a role in shielding and protecting hydrogen ions in the solution 201 to be measured, so that the hydrogen ions are prevented from being interfered by an electromagnetic field in the surrounding environment during measurement, and the accuracy and repeatability of the measurement result are effectively improved.
This recess is ready for the subsequent gate insulator layer formation. The source electrode and the drain electrode are positioned through the channel groove structure self-alignment effect, the precision control of the positions between the source electrode and the drain electrode and the channel is very accurate by adopting the mode, and the definition of the source electrode, the drain electrode and the channel region can be realized only through one step of glue spreading, exposure, development and etching.
The groove structure is etched into the semiconductor substrate 202 by using a dry etching method or a combination of the wet etching method and the dry etching method, and the groove is accurately and quickly etched by using the advantages of good anisotropy, high etching rate and high fidelity of the dry etching method and the transfer of photoetching patterns; the wet etching and the dry etching are combined, so that some residual substances on the surface of the semiconductor substrate 202 can be removed by the wet etching first, and then the grooves in the semiconductor substrate 202 are etched by the dry etching, so that the etching effect is more obvious. The self-alignment effect adopted in the second embodiment can very accurately control the relative positions of the source electrode, the drain electrode and the groove, and the positions can be positioned only through one step of glue spreading, exposure, development and etching.
And step S4, generating an ion sensitive film on the surface of the groove. The ion sensitive film 103 is formed in the doped region 203 and the groove portion, and after the photoresist is removed, it is shown in fig. 3I.
The ion sensitive membrane 103 may be a single-layer insulating medium layer, and the ion sensitive membrane material is SiO2、Si3N4、Al2O3Or Ta2O5The ion sensitive membrane materials are sensitive to hydrogen ions, have strong adsorption effect, high adsorption concentration and good sensitivity, so that the measurement result is more timely and effective. The ion-sensitive film may also be at least two insulating dielectric layers, wherein the layer in contact with the semiconductor substrate 202 is made of silicon dioxide SiO2Due to SiO2The surface layer is preferably made of silicon nitride (Si)3N4Aluminum oxide Al2O3Or tantalum pentoxide Ta2O5Any one of them. In this embodiment, the ion sensitive film 103 can be made into a thin film by thermal oxidation, chemical vapor deposition or atomic layer deposition, which are relatively simple and easy to implement, have low requirement on film forming equipment, and can reduce the total device sizeThe preparation cost of (2).
After the above four steps are completed, metal silicide contact regions 302 are respectively manufactured under the source electrode 101, the drain electrode 102 and the semiconductor substrate 202 through a standard photoetching process, finally, a layer of metal nickel Ni is plated, and metal silicide contact is formed after annealing, so that the connection of the whole device and an external circuit is facilitated.
In this embodiment, a reference electrode 205 may be additionally inserted into the solution 201 to be measured when the ISFET device is performing the measurement, as shown in fig. 3L. The reference electrode 205 is an Ag/AgCl reference electrode 205 filled with 3.5M KCl solution, and the reference electrode 205 has the function of stabilizing the potential of the solution 201 to be measured, so that the accuracy and reliability of the measurement result are further improved.
It will be readily appreciated that this embodiment may be implemented in conjunction with the first embodiment. The related technical details and the preparation steps mentioned in the first embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (14)
1. An ion sensitive field effect transistor, comprising: the semiconductor substrate, extend to the recess inside the said semiconductor substrate, and locate on said semiconductor substrate and form source and drain-source resistance through doping;
the groove is positioned between the source electrode and the drain electrode, and the depth of the groove is greater than the junction depth of the source electrode and the drain electrode;
the surface of the groove is provided with an ion sensitive film.
2. The ion sensitive field effect transistor of claim 1, wherein the source and drain are formed by doping a predetermined region of the semiconductor substrate and separating the doped region by the recess structure.
3. The ion-sensitive field effect transistor of claim 1, wherein the ion-sensitive film is a single-layer insulating dielectric layer, and the ion-sensitive film is made of any one of the following materials:
silicon dioxide SiO2Silicon nitride Si3N4Aluminum oxide Al2O3Or tantalum pentoxide Ta2O5。
4. The ion-sensitive field effect transistor according to claim 1, wherein the ion-sensitive film is an insulating dielectric layer having at least two layers,
the layer in contact with the semiconductor substrate is made of silicon dioxide SiO2The material adopted by the outermost layer is any one of the following materials:
silicon nitride Si3N4Aluminum oxide Al2O3Or tantalum pentoxide Ta2O5。
5. The ion sensitive field effect transistor of claim 1, further comprising: and the source leading-out terminal, the drain leading-out terminal and the substrate leading-out terminal are metal silicide contact regions respectively positioned on the source electrode, the drain electrode and the back surface of the semiconductor substrate.
6. The ion sensitive field effect transistor of claim 1, wherein the semiconductor substrate is P-type, and the source and drain are N-type doped; or,
the semiconductor substrate is N-type, and the source electrode and the drain electrode are doped in P-type.
7. A preparation method of an ion sensitive field effect transistor is characterized by comprising the following steps:
providing a semiconductor substrate;
doping is carried out on the semiconductor substrate to form a doped region;
etching a groove in the doped region, wherein the groove separates the doped region, and the doped regions on two sides form a source electrode and a drain electrode; wherein the depth of the groove is greater than the junction depth of the source electrode and the drain electrode;
and generating an ion sensitive film on the surface of the groove.
8. The method according to claim 7, wherein in the step of forming the ion-sensitive film on the surface of the recess, an insulating dielectric layer is formed as the ion-sensitive film;
wherein the ion sensitive membrane is made of any one of the following materials:
silicon dioxide SiO2Silicon nitride Si3N4Aluminum oxide Al2O3Or tantalum pentoxide Ta2O5。
9. The method according to claim 7, wherein in the step of forming the ion-sensitive film on the surface of the recess, at least two layers of insulating dielectric layers are formed as the ion-sensitive film;
wherein the layer in contact with the semiconductor substrate is made of silicon dioxide SiO2The material adopted by the outermost layer is any one of the following materials:
silicon nitride Si3N4Aluminum oxide Al2O3Or tantalum pentoxide Ta2O5。
10. The method as claimed in claim 7, wherein in the step of forming the ion-sensitive film on the surface of the recess, the ion-sensitive film is formed by thermal oxidation, chemical vapor deposition or atomic layer deposition.
11. The method according to claim 7, further comprising the following steps after the step of forming the ion-sensitive film on the surface of the recess:
and forming metal silicide contact regions on the source electrode, the drain electrode and the back surface of the semiconductor substrate, wherein the metal silicide contact regions are respectively used as leading-out ends of the source electrode, the drain electrode and the semiconductor substrate.
12. The method of claim 7, wherein in the step of etching a recess in the doped region and the semiconductor substrate, the recess is formed by dry etching or by a combination of wet and dry etching.
13. The ion sensitive field effect transistor of claim 7, further comprising, prior to the step of doping, the steps of:
forming an insulating layer on the semiconductor substrate; wherein the insulating layer is silicon dioxide SiO2Silicon nitride Si3N4Or a laminate of both.
14. The ion sensitive field effect transistor of claim 7, wherein in the step of doping on the semiconductor substrate, the semiconductor substrate is P-type and N-type doped; or,
the semiconductor substrate is N-type and is doped P-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310359689.2A CN103472115B (en) | 2013-08-16 | 2013-08-16 | Ion-sensitive field effect transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310359689.2A CN103472115B (en) | 2013-08-16 | 2013-08-16 | Ion-sensitive field effect transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103472115A true CN103472115A (en) | 2013-12-25 |
| CN103472115B CN103472115B (en) | 2018-02-27 |
Family
ID=49797043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310359689.2A Expired - Fee Related CN103472115B (en) | 2013-08-16 | 2013-08-16 | Ion-sensitive field effect transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103472115B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103940884A (en) * | 2014-03-18 | 2014-07-23 | 复旦大学 | Ion sensitive field effect transistor and preparation method thereof |
| CN115436436A (en) * | 2022-11-03 | 2022-12-06 | 南京元感微电子有限公司 | FET gas sensor and processing method thereof |
| CN115501920A (en) * | 2022-09-16 | 2022-12-23 | 中国人民解放军陆军特色医学中心 | Preparation method of nucleic acid amplification detection micro-fluidic chip with enhanced sensitivity of organic electrochemical transistor |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5911873A (en) * | 1997-05-02 | 1999-06-15 | Rosemount Analytical Inc. | Apparatus and method for operating an ISFET at multiple drain currents and gate-source voltages allowing for diagnostics and control of isopotential points |
| CN1577888A (en) * | 2003-07-24 | 2005-02-09 | 三星电子株式会社 | Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same |
| US20070095663A1 (en) * | 2005-11-01 | 2007-05-03 | National Yunlin University Of Science And Technology | Preparation of a PH sensor, the prepared PH sensor, system comprising the same and measurement using the system |
| CN101189507A (en) * | 2005-05-30 | 2008-05-28 | 梅特勒-托利多公开股份有限公司 | Electrochemical sensor |
| US20080283910A1 (en) * | 2007-05-15 | 2008-11-20 | Qimonda Ag | Integrated circuit and method of forming an integrated circuit |
| US20090184357A1 (en) * | 2008-01-18 | 2009-07-23 | Qimonda Ag | Soi based integrated circuit and method for manufacturing |
| CN101764155A (en) * | 2009-11-18 | 2010-06-30 | 上海宏力半导体制造有限公司 | Grooved field-effect tube and preparation method thereof |
| US20130204107A1 (en) * | 2012-01-23 | 2013-08-08 | The Ohio State University | Devices and methods for the rapid and accurate detection of analytes |
-
2013
- 2013-08-16 CN CN201310359689.2A patent/CN103472115B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5911873A (en) * | 1997-05-02 | 1999-06-15 | Rosemount Analytical Inc. | Apparatus and method for operating an ISFET at multiple drain currents and gate-source voltages allowing for diagnostics and control of isopotential points |
| CN1577888A (en) * | 2003-07-24 | 2005-02-09 | 三星电子株式会社 | Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same |
| CN101189507A (en) * | 2005-05-30 | 2008-05-28 | 梅特勒-托利多公开股份有限公司 | Electrochemical sensor |
| US20070095663A1 (en) * | 2005-11-01 | 2007-05-03 | National Yunlin University Of Science And Technology | Preparation of a PH sensor, the prepared PH sensor, system comprising the same and measurement using the system |
| US20080283910A1 (en) * | 2007-05-15 | 2008-11-20 | Qimonda Ag | Integrated circuit and method of forming an integrated circuit |
| US20090184357A1 (en) * | 2008-01-18 | 2009-07-23 | Qimonda Ag | Soi based integrated circuit and method for manufacturing |
| CN101764155A (en) * | 2009-11-18 | 2010-06-30 | 上海宏力半导体制造有限公司 | Grooved field-effect tube and preparation method thereof |
| US20130204107A1 (en) * | 2012-01-23 | 2013-08-08 | The Ohio State University | Devices and methods for the rapid and accurate detection of analytes |
Non-Patent Citations (1)
| Title |
|---|
| XIWEI HUANG 等: "《A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis》", 《IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103940884A (en) * | 2014-03-18 | 2014-07-23 | 复旦大学 | Ion sensitive field effect transistor and preparation method thereof |
| CN103940884B (en) * | 2014-03-18 | 2017-04-12 | 复旦大学 | Ion sensitive field effect transistor and preparation method thereof |
| CN115501920A (en) * | 2022-09-16 | 2022-12-23 | 中国人民解放军陆军特色医学中心 | Preparation method of nucleic acid amplification detection micro-fluidic chip with enhanced sensitivity of organic electrochemical transistor |
| CN115501920B (en) * | 2022-09-16 | 2024-04-05 | 中国人民解放军陆军特色医学中心 | Preparation method of nucleic acid amplification detection micro-fluidic chip of organic electrochemical crystal Guan Zengmin |
| CN115436436A (en) * | 2022-11-03 | 2022-12-06 | 南京元感微电子有限公司 | FET gas sensor and processing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103472115B (en) | 2018-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8878258B2 (en) | Detector of biological or chemical material and corresponding array of detectors | |
| US6617190B2 (en) | A-WO3-gate ISFET devices and method of making the same | |
| US20050186697A1 (en) | Fabrication method of an ion sensitive field effect transistor | |
| CN103940884B (en) | Ion sensitive field effect transistor and preparation method thereof | |
| CN103472115B (en) | Ion-sensitive field effect transistor and preparation method thereof | |
| CN105699463A (en) | Chemical field effect transistor gas-sensitive sensor and manufacturing method thereof | |
| CN108847424A (en) | Thin film transistor (TFT), sensor, biological monitor and method | |
| CN104380096A (en) | Isfet sensor with integrated control device | |
| CN105353000B (en) | Semiconductor devices and its detection method | |
| CN101022105B (en) | Semiconductor device testing device and substrate for producing tester | |
| US20080100311A1 (en) | Electrical Measurement Of The Thickness Of A Semiconductor Layer | |
| Yusof et al. | pH sensing characteristics of silicon nitride thin film and silicon nitride-based ISFET sensor | |
| US9322799B2 (en) | High-k metal gate device structure for human blood gas sensing | |
| JP2011133234A (en) | Sensor, and measuring method using the same | |
| KR102098288B1 (en) | Method for measuring doping concentration of semiconductor material , and recording medium for computer program using the same | |
| TWI600901B (en) | Ion-sensitive field-effect transistor | |
| CN116936543B (en) | Capacitance test structure, preparation method, test method and application | |
| Pregl et al. | Channel length dependent sensor response of Schottky-barrier FET pH sensors | |
| CN108732225A (en) | Ion-sensitive field effect transistor and forming method thereof | |
| US20210270769A1 (en) | Chemical sensor and detection apparatus | |
| KR101202015B1 (en) | pH Sensor Using SOI Substrate and Method for Fabricating the Same | |
| JPS62250353A (en) | Semiconductor chemical sensor | |
| JP2006093597A (en) | Method of evaluating semiconductor wafer | |
| CN117524898A (en) | Thermal effect device structure, forming method thereof and thermal resistance obtaining method | |
| KR100826761B1 (en) | Test pattern set and test method of cmos process step |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180227 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |