CN103472115B - Ion-sensitive field effect transistor and preparation method thereof - Google Patents
Ion-sensitive field effect transistor and preparation method thereof Download PDFInfo
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- CN103472115B CN103472115B CN201310359689.2A CN201310359689A CN103472115B CN 103472115 B CN103472115 B CN 103472115B CN 201310359689 A CN201310359689 A CN 201310359689A CN 103472115 B CN103472115 B CN 103472115B
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Abstract
The present invention relates to transistor, discloses a kind of ion-sensitive field effect transistor.The ion-sensitive field effect transistor includes Semiconductor substrate 202, and the source electrode 101 formed in Semiconductor substrate 202 by adulterating and drain electrode 102, there is a groove structure being etched into inside Semiconductor substrate 202 between source electrode 101 and drain electrode 102, in the groove structure Surface Creation ion sensitive membrane 103, gate insulation layer is formed.Because concave slot structure of the present invention is etched into the inside of Semiconductor substrate 202; there is certain depth; such structure can play a part of shielding protection to the tested hydrogen ion in solution 201; so that exempting from the interference of electromagnetic field in surrounding environment when measuring hydrogen ion concentration, and then the accuracy of measurement result and repeatability is set to be obtained for effective raising.
Description
Technical field
The present invention relates to field-effect transistor, more particularly to a kind of ion-sensitive field effect transistor and preparation method thereof.
Background technology
In the prior art, the structure of ion-sensitive field effect transistor ISFET devices aoxidizes with removing the metal of metal gate
Thing semiconductor field MOSFET is very much like, as depicted in figs. 1 and 2, its gate insulation layer be source electrode 101 with drain electrode 102 it
Between planar section, the one layer of sensitive layer 103 covered on gate insulation layer directly contacts with detected solution 201, due to detected solution
Hydrionic presence in 201, in ion sensitive membrane 103 with being induced on the interface of detected solution 201 to the small of hydrogen ion sensitivity
Energy this special Nernst response pctential：
This Nernstian potential causes gate electrode insulation surface to form certain electrical potential difference with source electrode, when this electrical potential difference increases to
Raceway groove may turn on after the threshold voltage of transistor, adds a fixed voltage between source electrode 101 and drain electrode 102, therebetween will
Electric current is formed, the Nernst current potentials that hydrogen ion more at most induces in solution are bigger, and raceway groove opens more abundant, source-drain current
It is bigger.The hydrogen ion concentration in the solution of detected solution 201 or activity are detected by the measurement can of source-leakage current,
Measure pH value.
Due to being highly susceptible to the interference of peripheral electromagnetic field when measuring hydrogen ion concentration present in solution 201, and show
Have in technology because the gate insulation layer of ISFET devices is a plane domain, it is impossible to which the hydrogen ion in detected solution 201 is played
Shielding action to peripheral electromagnetic field, moreover, energy this special response pctential between the interface of ion sensitive membrane 103- detected solutions 201
Very small, slightly deviation will make unstable measurement result, poor repeatability, reliability low.
In the prior art source electrode and drain electrode formation there is also it is very big the defects of, current technique is to Semiconductor substrate
The position that source electrode and drain electrode are corresponded on 202 is doped, and the space of gate insulation layer is left in centre, and such mode can cause source electrode
With diffusion of the drain implants to channel region, the actually active size of raceway groove is influenceed.And the groove structure in the present invention, automatically every
Increase income pole and drain region, so can accurately control the size of channel region.
The content of the invention
It is an object of the invention to provide a kind of ion-sensitive field effect transistor and preparation method thereof, is applying the crystal
When pipe carries out pH value detection, the hydrogen ion in detected solution is exempted from the interference of electromagnetic field in surrounding environment, make measurement result more
Accurately, repeatability is higher.
In order to solve the above technical problems, the invention provides a kind of ion-sensitive field effect transistor, served as a contrast comprising semiconductor
Bottom, the groove extended to inside the Semiconductor substrate, and in the Semiconductor substrate by adulterate formed source electrode and
Drain electrode；
For the groove between the source electrode and the drain electrode, the depth of the groove is more than the source electrode and drain electrode
Junction depth；
The groove surfaces have ion sensitive membrane.
Present invention also offers a kind of preparation method of ion-sensitive field effect transistor, comprise the steps of：
Semi-conductive substrate is provided；
It is doped on the semiconductor substrate, forms doped region；
A groove, the doped region shape of the groove both sides are etched on the doped region and the Semiconductor substrate
Into source electrode and drain electrode；Wherein, the depth of the groove is more than the source electrode and the junction depth of drain electrode；
Ion sensitive membrane is generated in the groove surfaces.
Compared with prior art, ISFET is improved in structure in the present invention, is had between source electrode and drain electrode recessed
Groove, the groove are etched into inside semiconductor, source electrode and drain electrode are separated, groove surfaces have ion sensitive membrane, using this hair
When bright ISFET carries out pH value detection, detected solution is injected in groove, because the etching depth of the groove is deeper, for quilt
The space of a comparison closing can be formed by surveying solution, and the work of shielding protection can be thus played to the hydrogen ion in detected solution
With so that exempt from the interference of electromagnetic field in surrounding environment when measuring hydrogen ion concentration, and then make measurement result accuracy and
Repeatability is obtained for effective raising.
Preferably, in the present invention, whole semiconductor substrate surface first passes through photoetching process and defines doped region, then enters again
Row doping, then forms groove structure on corresponding position, doped region is split up into source electrode and drain electrode, this technique can protect
The doping in whole source electrode and the region of drain electrode is demonstrate,proved all than more uniform, avoids source electrode and drain electrode because doping inequality causes defect,
Influence device performance；And this doping process afterwards groove formed during, between source electrode and drain electrode and groove walls
Be not in because the defects of doping is not respectively formed.
Secondly, the ion sensitive membrane in above-mentioned ion-sensitive field effect transistor is single layer dielectrics dielectric layer, ion-sensitive
Membrane material is SiO2、Si3N4、Al2O3Or Ta2O5, these ion-sensitive membrane materials are more sensitive to hydrogen ion and suction-operated ratio
Relatively strong, adsorption concentration is higher, and sensitivity is good, thus makes measurement result effective much sooner.
Again, the ion sensitive membrane in above-mentioned ion-sensitive field effect transistor can also be at least two layers of dielectric
Layer, wherein, the material that the layer contacted with Semiconductor substrate uses is silica SiO2, the material that the layer of most surface uses is nitrogen
SiClx Si3N4, aluminium oxide Al2O3Or tantalum pentoxide Ta2O5In any one.Because SiO2With the associativity of Semiconductor substrate compared with
It is good, and surface uses material more sensitive to hydrogen ion and that suction-operated is stronger, it is therefore possible to use laminated construction, makes
Ion sensitive membrane can be preferable with the associativity of Semiconductor substrate, and and can has stronger suction-operated to hydrogen ion.
In addition, the ion-sensitive field effect transistor in the present invention is also drawn comprising source exit, leakage exit and substrate
End, to be located at the Metal-silicides Contact area of above-mentioned source electrode, drain electrode and the Semiconductor substrate back side respectively, in order to by source electrode, leak
Pole and Semiconductor substrate are connected with external circuitses.
As a further improvement on the present invention, also to be given birth to before semiconductor sinks to the bottom and is doped in the Semiconductor substrate
Into a layer insulating SiO2Or by SiO2And Si3N4The laminated insulation layer of composition, the insulating barrier on a semiconductor substrate leak source electrode
Well isolate between pole and detected solution, prevent detected solution from penetrating into source electrode and drain region, between solution and source drain
Leakage current is produced, is further ensured that the stability of ion-sensitive field effect transistor working condition.
As more further improving for the present invention, the selection of the Semiconductor substrate in the present invention is also particularly important, if partly leading
Body substrate is p-type, and source electrode and drain electrode are just n-type doping；If Semiconductor substrate is N-type, the source electrode and the drain electrode are mixed for p-type
It is miscellaneous.Preferred substrate is the scheme of p-type, source electrode and drain electrode for n-type doping in the present invention, because the mobility of electronics is much larger than sky
The mobility in cave, therefore source electrode and drain electrode are done with the n-type doping that electronics is majority carrier, it is much better than by current capacity；
In addition, for control angle, N-type ISFET can be opened with positive voltage, be easy to use.
Source electrode and drain electrode in the present invention are positioned by channel grooves structure self-aligning effect, right in this way
The precision controlling of position is very accurate between source electrode and drain electrode and raceway groove, as long as and by a step spin coating, exposure, development and quarter
Erosion step can realizes the definition of source electrode, drain electrode and channel region.
In addition, the groove extended in intermediate ion sensitive field effect transistor of the present invention inside Semiconductor substrate is logical
Dry etching or wet etching is crossed to be formed with the mode that dry etching is combined, using dry etching anisotropic it is good, etching
Speed is high and can be with the transfer litho pattern of high-fidelity the advantages of, accurately and rapidly etch above-mentioned groove；Wet etching is with doing
The mode that method etching combines first can first remove some residuals of semiconductor substrate surface with wet etching, then be carved with dry method
Erosion etches the groove inside Semiconductor substrate, and etching effect is more notable.
Finally, the ion sensitive membrane being related in the present invention is by thermal oxide, chemical vapor deposition or ald side
Formula is formed, and comparatively speaking the method for these film forming is simpler easy.
Brief description of the drawings
Fig. 1 is ISFET solid pH sensors operation principle schematic diagram in the prior art；
Fig. 2A is the ion-sensitive field effect transistor schematic diagram in first embodiment of the invention；
Fig. 2 B additional reference electricity when being the ion-sensitive field effect transistor test in first embodiment of the invention
The schematic diagram of pole；
Fig. 3 A are the ion-sensitive field effect transistor preparation method flow charts in second embodiment of the invention；
Fig. 3 B~3K are the ion-sensitive field effect transistor preparation method signals in second embodiment of the invention
Figure；
Fig. 3 L are when being tested in the ion-sensitive field effect transistor preparation method in second embodiment of the invention
The schematic diagram of additional reference electrode.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, each reality below in conjunction with accompanying drawing to the present invention
The mode of applying is explained in detail.However, it will be understood by those skilled in the art that in each embodiment of the present invention,
In order that reader more fully understands the application and proposes many ins and outs.But even if without these ins and outs and base
Many variations and modification in following embodiment, each claim of the application technical side claimed can also be realized
Case.
The first embodiment of the present invention is related to a kind of ion-sensitive field effect transistor, as shown in Figure 2 A, left figure in figure
For top view, right figure is the diagrammatic cross-section in a-a ＇ faces in corresponding left figure.The ion-sensitive field effect transistor includes semiconductor
Substrate 202 and doped region 203 is formed by doping in the Semiconductor substrate 202, source electrode 101 and drain electrode 102 are respectively positioned on
In doped region 203, there are a groove structure extended to inside Semiconductor substrate 202, groove between source electrode 101 and drain electrode 102
Surface Creation ion sensitive membrane 103, the groove structure and the ion sensitive membrane 103 together constitute the gate insulation layer on raceway groove,
Formed after gate insulation layer will also produce metal silicide and connect at source electrode 101, drain electrode 102 and the back side of Semiconductor substrate 202 respectively
Area is touched, in order to which source electrode 101, drain electrode 102 and Semiconductor substrate 202 are connected with external circuitses.
ISFET devices detected solution 201 in measurement is injected in groove in the present embodiment, in ion sensitive membrane 103 and quilt
Small Nernst response pctentials can be produced by surveying on the interface of solution 201, and this Nernst current potential causes gate electrode insulation surface and source
Pole 101 forms certain electrical potential difference, be may turn on after this electrical potential difference increases to transistor threshold voltage in raceway groove, in source electrode
Plus will form electric current after fixed voltage therebetween between 101 and drain electrode 102, the more sensings of hydrogen ion in detected solution 201
The Nernst current potentials gone out are bigger, and raceway groove unlatching is more abundant, then source-drain current is bigger, because above-mentioned Nernst response pctentials are non-
Chang Wei little, a slight influence factor this may result in this potential measurement and be forbidden in external environment, and institute in the present embodiment
The groove stated is deeper, and the space of a comparison closing can be formed for detected solution, thus can be in detected solution 201
Hydrogen ion plays a part of shielding protection so that in measurement, hydrogen ion exempts from the interference of electromagnetic field in surrounding environment, and then makes
The accuracy and repeatability of measurement result are obtained for effective raising.
The formation process and prior art of doped region 203 described in the present embodiment are different, first in semiconductor
The predeterminable area doping on the surface of substrate 202, then forms groove structure, source electrode 101 and drain electrode 102 on corresponding position again
Separate, this technique can ensure to avoid source electrode 101 and drain electrode 102 all than more uniform in whole source electrode and drain region doping
Because doping inequality causes defect, device performance is influenceed；And this doping process afterwards groove formed during, source electrode
Also be not in the defects of formation because adulterating inequality between 101 and drain electrode 102 and groove walls.In addition, Semiconductor substrate is entered
Row doping can use the method for the existing comparative maturities such as ion implanting to realize, will not be repeated here.
Ion sensitive membrane 103 in the present embodiment is single layer dielectrics dielectric layer, and ion-sensitive membrane material is SiO2、Si3N4、
Al2O3Or Ta2O5, these ion-sensitive membrane materials are more sensitive to hydrogen ion and suction-operated is stronger, and adsorption concentration is higher,
Sensitivity is good, thus makes measurement result effective much sooner.The ion sensitive membrane 103 can also be at least two layers of dielectric
Layer, wherein, the material that the layer contacted with Semiconductor substrate 202 uses is silica SiO2, because SiO2With Semiconductor substrate
202 associativity is preferable, and the material that the layer of most surface uses is silicon nitride Si3N4, aluminium oxide Al2O3Or tantalum pentoxide Ta2O5In
Any one.The present embodiment intermediate ion sensitive membrane 103 can pass through the side of thermal oxide, chemical vapor deposition or ald
Film is made in above-mentioned material by formula, and these modes are comparatively all relatively simple, is required also not high to film-forming apparatus, can be dropped
The preparation cost of low whole device.
In addition, the ISFET devices in the present invention also include insulating barrier 204, the insulating barrier 204 covers Semiconductor substrate
The region not being doped on 202.The insulating barrier 204 can be silica SiO2, silicon nitride Si3N4Or they are formed
Laminated construction.If insulating barrier 204 is silica SiO2, high-temperature oxydation technology, tetraethyl orthosilicate (TEOS) can be used low
Press chemical vapor deposition（LPCVD）The combination of technology or two kinds of technologies is formed.LPCVD SiO2With high-temperature thermal oxidation SiO2Phase
Than film quality is more loose, but can make up high-temperature oxydation technology to a certain extent and form thicker SiO2The stress brought during layer
The drawbacks of with defect and too high technological temperature.Therefore, can using the R. concomitans of LPCVD technologies and high-temperature oxydation technology
Ensure SiO2The compactness of film and the adhesive capacity with Semiconductor substrate 202, and can improve the electrical property and finished product of device
Rate.
The selection of Semiconductor substrate 202 is also particularly important in the present invention, and the Semiconductor substrate 202 can be p-type or N
Type, if Semiconductor substrate 202 is p-type, by adulterate formed be exactly N-type source electrode 101 and drain 102；If semiconductor serves as a contrast
Bottom 202 is N-type, then what is formed by adulterating is exactly source electrode 101 and the drain electrode 102 of p-type.It is that p-type is partly led in the present embodiment
Body substrate 202, source electrode 101 and the drain electrode 102 of N-type are formed by doping, because the mobility of electronics is much larger than the migration in hole
Rate, thus with the n-type doping that electronics is majority carrier do source electrode 101 and drain electrode 102 if, by current capacity be eager to excel
It is more；In addition, for control angle, N-type ISFET can be opened with positive voltage, be used more convenient.
A reference can be inserted in present embodiment in detected solution 201 in addition when ISFET devices measure
Electrode 205, the reference electrode 205 are an Ag/AgCl reference electrode for being filled with 3.5M KCl solution, the reference electrode 205
There is stable detected solution potential, so as to further increase the accuracy of measurement result and reliability, as shown in Figure 2 B.
Second embodiment of the invention is related to a kind of preparation method of ion-sensitive field effect transistor, if Fig. 3 A are this realities
The flow chart of the preparation method for the ion-sensitive field effect transistor that the mode of applying provides, Fig. 3 B to Fig. 3 K provide for present embodiment
Ion-sensitive field effect transistor preparation method in top view corresponding to each step（It is left）With a-a ＇ faces in corresponding top view
Diagrammatic cross-section（It is right）.With reference to Fig. 3 A to Fig. 3 K, the ion-sensitive field effect transistor that provides present embodiment
Preparation method is specifically described.
Step S1, there is provided Semiconductor substrate 202, and insulating barrier 204 is formed on substrate, as shown in fig.3 a 3 c.
Above-mentioned Semiconductor substrate 202 can be p-type or N-type, if Semiconductor substrate 202 is p-type, by adulterating what is formed
It is exactly source electrode 101 and the drain electrode 102 of N-type；If Semiconductor substrate 202 is N-type, by adulterate formed be exactly p-type source electrode
101 and drain electrode 102.It is P-type semiconductor substrate 202 in the present embodiment, source electrode 101 and the drain electrode of N-type is formed by doping
102, because the mobility of electronics is much larger than the mobility in hole, therefore source electrode is done with the n-type doping that electronics is majority carrier
101 and drain electrode 102 if, it is much better than by current capacity；In addition, for control angle, N-type ISFET can use positive electricity
Press off and open, use more convenient.
Wherein, a layer insulating or multilayer dielectric layer can be formed on a semiconductor substrate；Wherein, the material of insulating barrier is
Silica SiO2, silicon nitride Si3N4Or their laminated construction for forming.Such as insulating barrier 204 therein can be SiO2,
High-temperature oxydation technology, tetraethyl orthosilicate (TEOS) low-pressure chemical vapor phase deposition can be passed through（LPCVD）Technology or two kinds of technologies
With reference to being formed, using TEOSLPCVD technologies SiO is realized2In the deposit of semiconductor substrate surface, compensate for a certain extent
High-temperature oxydation technology forms thicker SiO2Layer overlong time, technological temperature are too high and produce the drawback such as stress and defect.Using
The reasonable utilization of TEOS LPCVD technologies and high-temperature oxydation technology, both ensure that SiO2The compactness of film and and Semiconductor substrate
202 adhesive capacity, the electrical property and yield rate of device are improved again.
Step S2, it is doped in Semiconductor substrate 202, forms doped region 203.
Specifically, be doped in Semiconductor substrate 202, formed doped region 203 the step of in, also comprising following son
Step：
Step S201, one layer of photoresist 301 is coated on insulating barrier 204, as shown in Figure 3 C.This layer of photoresist 301 can be with
Coated on the insulating barrier 204 by the way of rotary coating.
Step S202, flagpole pattern as shown in Figure 3 D is prepared by exposure, developing process, exposing needs what is removed
SiO2。
Step S203, the mode combined with dry etching or wet etching with dry etching are etched away in step S202
The SiO leaked cruelly2, strip Semiconductor substrate 202 is exposed, as shown in FIGURE 3 E.
Step S204, is doped to surface, forms the doped region 203 of strip, and this doped region 203 forms source electrode for after
101 lay the foundation with drain electrode 102, as illustrated in Figure 3 F.If the Semiconductor substrate 202 provided in step S1 is p-type, this step
Doped region 203 is N-type after middle doping；If the Semiconductor substrate 202 provided in step S1 is N-type, doped region 203 after doping
For p-type.It is P-type semiconductor substrate 202 in the present embodiment, source electrode 101 and the drain electrode 102 of N-type is formed by doping, because
The mobility in hole is much larger than for the mobility of electronics, therefore source electrode 101 and leakage are done with the n-type doping that electronics is majority carrier
It is much better than by current capacity if pole 102；In addition, for control angle, N-type ISFET can be opened with positive voltage,
Use more convenient.
Step S3, a groove is etched on doped region 203 and Semiconductor substrate 202, form source electrode 101 and drain electrode 102.
A groove is specifically etched on doped region 203 and Semiconductor substrate 202, forms source electrode 101 and drain electrode 102
Step S3 in also include following sub-step：
Step S301, photoresist 301 is removed, manifest the insulating barrier 204 for being photo-etched the protection of glue 301, as shown in Figure 3 G.
Step S302, as shown in figure 3h, then by a spin coating, alignment exposure, develop and etch（That is repeat step 201
~step 203, simply change a mask plate）, obtain 4（4 are shown in schematic diagram, actually has many）Etch into half
Groove inside conductor substrate 202, the etching depth of the groove are more than source electrode 101 or the junction depth of drain electrode 102, so far, source electrode 101
Formed with drain electrode 102.
In measurement, detected solution 201 injects groove, and groove just can play shielding to the hydrogen ion in detected solution 201
The effect of protection so that hydrogen ion exempts from the interference of electromagnetic field in surrounding environment in measurement, and then makes the accurate of measurement result
Property and repeatability be obtained for effective raising, this point is also the most important inventive point of the present invention.
This groove just get ready for after by gate insulation layer formation.Wherein source electrode and drain electrode are by channel grooves knot
The positioning of structure self alignment effect, it is very accurate to the precision controlling of position between source electrode and drain electrode and raceway groove in this way,
As long as the definition of source electrode, drain electrode and channel region is realized by a step spin coating, exposure, development and etch step can.
Groove structure is that the mode combined with dry etching or wet etching with dry etching is etched to Semiconductor substrate 202
It is internal, using dry etching anisotropic is good, etch rate is high and can be with the transfer litho pattern of high-fidelity the advantages of, it is accurate
Really, above-mentioned groove is quickly etched；The mode that wet etching is combined with dry etching can be first the surface of Semiconductor substrate 202
Some residuals are first removed with wet etching, then etch the groove inside Semiconductor substrate 202, etching effect with dry etching
Fruit is more notable.Secondly the self alignment effect used in the present embodiment can point-device control source electrode and it of drain electrode and groove
Between relative position, as long as and realizing the positioning of this position by a step spin coating, exposure, development and etch step can.
Step S4, ion sensitive membrane is generated in groove surfaces.In doped region 203 and groove part generation ion sensitive membrane
103, after removing photoresist as shown in fig. 31.
Ion sensitive membrane 103 therein can be single layer dielectrics dielectric layer, and ion-sensitive membrane material is SiO2、Si3N4、
Al2O3Or Ta2O5, these ion-sensitive membrane materials are more sensitive to hydrogen ion and suction-operated is stronger, and adsorption concentration is higher,
Sensitivity is good, thus makes measurement result effective much sooner.The ion sensitive membrane can also be at least two layers of insulating medium layer,
Wherein, the material that the layer contacted with Semiconductor substrate 202 uses is silica SiO2, because SiO2With Semiconductor substrate 202
Associativity is preferable, and the material that the layer of most surface uses is silicon nitride Si3N4, aluminium oxide Al2O3Or tantalum pentoxide Ta2O5In it is any
It is a kind of.The present embodiment intermediate ion sensitive membrane 103 can be by modes such as thermal oxide, chemical vapor deposition or alds upper
State material and film is made, these modes are comparatively all relatively simple, require also not high to film-forming apparatus, can reduce whole
The preparation cost of device.
After the completion of above-mentioned four main steps, then by standard photolithography process respectively in source electrode 101, drain electrode 102 and half
Metal-silicides Contact area 302 is produced under conductor substrate 202, finally, layer of metal nickel is plated, metallic silicon is formed after annealing
Compound contacts, the connection of whole device and external circuit after being easy to.
A ginseng can be inserted in detected solution 201 in addition when ISFET devices measure in the present embodiment
Than electrode 205, as shown in figure 3l.The reference electrode 205 is an Ag/AgCl reference electrode for being filled with 3.5M KCl solution
205, the reference electrode 205 plays the role of the stable potential of detected solution 201, so as to further increase the accuracy of measurement result
And reliability.
The implementation it is seen that present embodiment can work in coordination with first embodiment.Mentioned in first embodiment
Relevant technical details and preparation process are still effective in the present embodiment, in order to reduce repetition, repeat no more here.Accordingly
Ground, the relevant technical details mentioned in present embodiment are also applicable in first embodiment.
It will be understood by those skilled in the art that the respective embodiments described above are to realize the specific embodiment of the present invention,
And in actual applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (14)
1. a kind of ion-sensitive field effect transistor, it is characterised in that include：Semiconductor substrate, extend to the semiconductor lining
Groove inside bottom, and by adulterating the source electrode formed and drain electrode in the Semiconductor substrate；
For the groove between the source electrode and the drain electrode, the depth of the groove is more than the source electrode and the knot of drain electrode
It is deep；
The groove surfaces have ion sensitive membrane.
2. a kind of ion-sensitive field effect transistor according to claim 1, it is characterised in that the source electrode and drain electrode are
By first being adulterated on a semiconductor substrate in predeterminable area, then by the groove structure the separated mode of the doped region
Formed.
3. a kind of ion-sensitive field effect transistor according to claim 1, it is characterised in that the ion sensitive membrane is
Single layer dielectrics dielectric layer, the material of the ion sensitive membrane for it is following any one：
Silica SiO2, silicon nitride Si3N4, aluminium oxide Al2O3Or tantalum pentoxide Ta2O5。
4. a kind of ion-sensitive field effect transistor according to claim 1, it is characterised in that the ion sensitive membrane is
With at least two layers of insulating medium layer,
The material that the layer contacted with the Semiconductor substrate uses is silica SiO2, material that the layer of most surface uses be with
Descend any one：
Silicon nitride Si3N4, aluminium oxide Al2O3Or tantalum pentoxide Ta2O5。
5. a kind of ion-sensitive field effect transistor according to claim 1, it is characterised in that also include：Source exit,
Exit and substrate exit are leaked, to be located at the metal silicide of the source electrode, drain electrode and the Semiconductor substrate back side respectively
Contact zone.
6. a kind of ion-sensitive field effect transistor according to claim 1, it is characterised in that the Semiconductor substrate is
P-type, the source electrode and the drain electrode are n-type doping；Or
The Semiconductor substrate is N-type, and the source electrode and the drain electrode are adulterated for p-type.
7. a kind of preparation method of ion-sensitive field effect transistor, it is characterised in that comprise the steps of：
Semi-conductive substrate is provided；
It is doped on the semiconductor substrate, forms doped region；
A groove is etched in the doped region, the groove separates the doped region, and the doped region of its both sides is formed
Source electrode and drain electrode；Wherein, the depth of the groove is more than the source electrode and the junction depth of drain electrode；
Ion sensitive membrane is generated in the groove surfaces.
8. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterised in that described
Groove surfaces were generated in the step of ion sensitive membrane, and one layer of insulating medium layer of generation is as the ion sensitive membrane；
Wherein, the material of the ion sensitive membrane for it is following any one：
Silica SiO2, silicon nitride Si3N4, aluminium oxide Al2O3Or tantalum pentoxide Ta2O5。
9. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterised in that described
Groove surfaces were generated in the step of ion sensitive membrane, and generation at least two layers of insulating medium layer is as the ion sensitive membrane；
Wherein, the material that the layer contacted with the Semiconductor substrate uses is silica SiO2, the material of the layer use of most surface
For it is following any one：
Silicon nitride Si3N4, aluminium oxide Al2O3Or tantalum pentoxide Ta2O5。
10. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterised in that in institute
In the step of stating groove surfaces generation ion sensitive membrane, obtained by the method for thermal oxide, chemical vapor deposition or ald
To the ion sensitive membrane.
11. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterised in that in institute
After the step of stating groove surfaces generation ion sensitive membrane, also comprise the steps of：
Form Metal-silicides Contact area at the source electrode, drain electrode and the Semiconductor substrate back side, respectively as the source electrode,
Drain electrode and the exit of the Semiconductor substrate.
12. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterised in that in institute
State in the step of etching a groove in doped region and the Semiconductor substrate, using dry etching or wet method and dry etching knot
The mode of conjunction forms groove.
13. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterised in that in institute
Before stating the step of being doped in Semiconductor substrate, also comprise the steps of：
Insulating barrier is formed on the semiconductor substrate；Wherein, the insulating barrier is silica SiO2, silicon nitride Si3N4Or two
The laminated construction of person's composition.
14. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterised in that in institute
State in the step of being doped in Semiconductor substrate, the Semiconductor substrate is p-type, carries out n-type doping；Or
The Semiconductor substrate is N-type, carries out p-type doping.
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| CN103940884B (en) * | 2014-03-18 | 2017-04-12 | 复旦大学 | Ion sensitive field effect transistor and preparation method thereof |
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