CN103457348A

CN103457348A - Semiconductor integrated circuit and operating method thereof

Info

Publication number: CN103457348A
Application number: CN201310199909XA
Authority: CN
Inventors: 鹿山正规
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2012-05-28
Filing date: 2013-05-27
Publication date: 2013-12-18
Anticipated expiration: 2033-05-27
Also published as: US9276404B2; JP2013246679A; US20130313904A1; KR20130133137A; CN103457348B; JP5902998B2; US20160164284A1

Abstract

A semiconductor integrated circuit and its operating method are provided. The present circuit has first and second supply terminals capable of supplying first and second power supply voltages respectively, an input voltage selection circuit coupled to the first and second supply terminals, and first and second power supply switches. The input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit and a control circuit. When the supply of the first or second power supply voltage to one of both supply terminals is detected upon completion of a power on reset operation, one of both power supply switches and the other thereof are controlled to on and off respectively. When the supply of both power supply voltages to both supply terminals is detected, the one thereof and the other thereof are respectively controlled to on and off according to the preset order of precedence.

Description

Semiconductor integrated circuit and method of operation thereof

Cross-reference to related applications

By reference, the disclosure that comprises specification, accompanying drawing and summary of the Japanese patent application No.2012-120696 on May 28th, 2012 submitted to intactly is contained in this.

Technical field

The present invention relates to semiconductor integrated circuit and method of operation thereof, particularly for realizing for the effective technology of electronic circuit from a plurality of power supplys power supply that selection will be used automatically.

Background technology

Described in each of the patent documentation 1 below for example and 2, IC-card is equipped with semiconductor integrated circuit and aerial coil, be by received the RF signal of the read/write device output from being called as " card reader/writer " by aerial coil to the power supply of IC-card, and by rectification circuit, this RF signal carried out that rectification carries out.Therefore, block at it IC-card that there is no power supply on side and become general in automatic ticket selling system, electronic money, logistics management etc.So, because this IC-card is powered by RF, and on the other hand, stored unique identification information (id information) in built-in nonvolatile memory, so it is called as " rfid card ".

On the other hand, be widely used the wireless power conveying system that is called as " only needing to place charging (just-to-place charging) ", wherein portable set (as smart phone) is in the situation that need not be couple to power cable by this portable set, be simply placed in special-purpose charging platen, thereby make it possible to portable set is charged.The reply of such wireless power conveying system intention is called as " smart phone " the large fact of battery consumption of cellular phone.That is to say, smart phone be with the Internet closely in conjunction with and the Multifunctional honeycomb phone of function based on personal computer, or having added the Multifunctional honeycomb phone of PDA function outside phone/mail, it can be abbreviated as " smapho " or " smaho ".The international standard that is called Qi (chi) that the wireless charging alliance (WPC) of wireless power conveying system based on by the sector group sets up.Sending ending equipment and receiving device both are respectively arranged with coil, make it possible to thus supply power from sending ending equipment to receiving device by EM induction system.The advantage of wireless power conveying system is not need insert or extract power connector to be charged, and particularly can omit the operation of the connector shielding thing of the power connector that opens and closes portable set.

In addition, in patent documentation 3 below, described, optionally be couple to the power supply of two or more types with the electronic equipment that battery is charged in, after coupling of the power supply with having carried out the power supply is released soon, with controller, this electronic equipment is couple to another power supply, thereby starts the charging to this battery.That is to say, the control provided by controller is, when from AC power supplies to the AC coupling, providing electric current, by AC power supplies, battery is charged, and while when from external equipment to outside devices, coupled, partly providing electric current, from AC power supplies to the AC coupling, not providing electric current, by the power supply of external equipment, battery is charged.When by AC power supplies, battery being charged, the external equipment coupling is couple to external equipment, controller and external equipment are carried out initial communication especially, thereby carry out by external equipment the battery needed charging setting of being charged.Especially, the external equipment coupling is the USB coupling, also can adopt the interface such as other standards such as IEEE1394.Due to when electronic equipment is couple to AC power supplies and external equipment simultaneously, be greater than the electric current from external equipment from the electric current of AC power supplies, so working, controller by AC power supplies, battery is charged.

The related art document

Patent documentation

Patent documentation 1: the open No.2009-4949 of Japanese unexamined patent

Patent documentation 2: the open No.2010-9353 of Japanese unexamined patent

Patent documentation 3: the open No.2011-155830 of Japanese unexamined patent

Summary of the invention

Before making the present invention, the present inventor has participated in the research and development of the semiconductor integrated circuit of controlling for battery charging, and a plurality of supply voltages that the supply voltage that this semiconductor integrated circuit can be carried with the AC power supplies voltage by from AC power supplies, the USB supply voltage coupled from USB and the wireless power based on above-mentioned wireless power conveying system carry out the AC-DC supply voltage that rectification and smoothing produce are operated.

In its R&D process, the present inventor has discussed the method for battery being charged by the power supply of describing in patent documentation 3.Yet the discussion of carrying out according to the present inventor, disclosed following problems, the implementation method of used power supply is selected in the supply that patent documentation 3 is not described a plurality of power supplys according to whether automatically.That is to say, the semiconductor integrated circuit of controlling for the battery charging that can be operated with above-described supply voltage need to be realized from the electronic circuit of a plurality of power supplys power supply that selection will be used automatically.

Although means for addressing this problem etc. are described below, according to description and the accompanying drawing of this specification, other purpose of the present invention and novel feature will become obvious.

The summary of the disclosed exemplary embodiment of the application is as follows by brief description:

According to the semiconductor integrated circuit (212) of exemplary embodiments, be equipped with the first power supply terminal (T1) that can supply the first supply voltage, the second source terminal (T2) that can supply second source voltage, input voltage to select circuit (2124), the first mains switch (SW1, SW2) and second source switch (SW3) (referring to Fig. 2).

Input voltage selects circuit (2124) to comprise power-on reset circuit (21244), input voltage detection circuit (21248) and control circuit (21245,21246) (referring to Fig. 4).

When the power-on reset operation at power-on reset circuit finishes by input voltage detection circuit detect first or second source voltage to first or the confession of second source terminal seasonable, by control circuit in response to its testing result by one in the first and second power supply terminals and wherein another to control respectively be conducting state and off-state.

Both are seasonable to both confessions of the first and second power supply terminals respectively the first and second supply voltages to be detected by input voltage detection circuit when the power-on reset operation at power-on reset circuit finishes, by control circuit according to the priority orders that sets in advance, by one in the first and second mains switches with wherein another is controlled respectively as conducting state and off-state.

Below by a typical advantageous effects obtained in disclosed embodiment in brief description the application:

According to this semiconductor integrated circuit (212), can realize for the electronic circuit from a plurality of power supplys power supply that selection will be used automatically.

The accompanying drawing explanation

Fig. 1 illustrates the figure of configuration that is equipped with the Multifunctional honeycomb phone of the semiconductor integrated circuit 212 of controlling for battery charging according to the first embodiment;

Fig. 2 is the figure of the configuration of the diagram semiconductor integrated circuit 212 of controlling for the battery charging according to the first embodiment illustrated in fig. 1;

Fig. 3 is the figure of function that the outside terminal of the semiconductor integrated circuit 212 of controlling for battery charging according to the first embodiment illustrated in fig. 2 is shown;

Fig. 4 illustrates the semiconductor integrated circuit according to the first embodiment 212 illustrated in fig. 2 figure for the configuration of the input voltage detection circuit 2124 of select operating mode when starting;

Fig. 5 is the figure of diagram by the operation of Fig. 2 and the 4 shown semiconductor integrated circuit according to the first embodiment 212 power supply that selection will be used automatically from a plurality of power supplys;

Fig. 6 is the figure illustrated by the operation of Fig. 2 and the 4 shown semiconductor integrated circuit according to the second embodiment 212 power supply that selection will be used automatically from a plurality of power supplys;

Fig. 7 is step S506, S507, S602 and the S603 that is illustrated in the operating period according to the second embodiment power supply that selection will be used automatically from a plurality of power supplys illustrated in fig. 6, the figure of the waveform of the each several part of Fig. 2 and the 4 shown semiconductor integrated circuit according to the second embodiment 212; And

Fig. 8 is the figure of diagram by the operation of Fig. 2 and the 4 shown semiconductor integrated circuit according to the 3rd embodiment 212 power supply that selection will be used automatically from a plurality of power supplys;

Embodiment

1. embodiment general introduction

At first the general introduction of disclosed exemplary embodiments of the present invention in the application will be described.The element that the concept that Reference numeral in the accompanying drawing of quoting in bracket in description to the general introduction of exemplary embodiments only shows to give the assembly of this Reference numeral to it comprises.

[1] according to the semiconductor integrated circuit (212) of exemplary embodiments the first power supply terminal (T1) that can supply the first supply voltage, the second source terminal (T2) that can supply second source voltage be equipped with, the input voltage that is couple to the first power supply terminal and second source terminal selects circuit (2124), the first mains switch (SW1, SW2) and second source switch (SW3) (referring to Fig. 2).

Supply in response to the first supply voltage to the supply of the first power supply terminal (T1) and from second source voltage to second source terminal (T2), power-on reset circuit (21244) produces power-on reset signal (POR).

Input voltage detection circuit (21248) produces the first voltage detecting output signal (Vdet1) in response to the first supply voltage to the supply of the first power supply terminal (T1).Input voltage detection circuit (21248) produces second voltage and detects output signal (Vdet2) to the supply of second source terminal (T2) in response to second source voltage.

Control circuit (21245,21246) detects output signal (Vdet2) in response to power-on reset signal (POR), the first voltage detecting output signal (Vdet1) and second voltage, controls the first mains switch and second source switch.

The timing that finishes in response to the power-on reset operation of power-on reset circuit (21244) at the level of power-on reset signal (POR) and change, input voltage detection circuit (21248) detects the supply of the first supply voltage to the supply of the first power supply terminal (T1) and second source voltage to second source terminal (T2).

The timing changed at the level of power-on reset signal, input voltage detection circuit detects the supply of the first supply voltage to the first power supply terminal, and second source voltage do not detected in the first situation of the supply of second source terminal, after power-on reset operation finishes, control circuit controls respectively the first mains switch and second source switch into conducting state and off-state (Fig. 5: S504 and S505).

After power-on reset operation finishes, the first mains switch and second source switch are controlled respectively as conducting state and off-state, the first mains switch that is controlled as thus conducting state will be supplied to the first supply voltage of the first power supply terminal (T1) to be supplied to load (3,26) (Fig. 5: S505).

When the level of power-on reset signal changes, input voltage detection circuit detects the supply of second source voltage to the second source terminal, and the first supply voltage do not detected in the second situation of the supply of the first power supply terminal, after power-on reset operation finishes, control circuit controls respectively the first mains switch and second source switch into off-state and conducting state (Fig. 5: S506 and S507).

After power-on reset operation finishes, the first mains switch and second source switch are controlled respectively as off-state and conducting state, the second source switch that is controlled as thus conducting state will be supplied to the second source voltage of second source terminal to be supplied to load (3,26) (Fig. 5: S507).

The timing changed at the level of power-on reset signal, input voltage detection circuit detect the first supply voltage to the supply of the first power supply terminal and second source voltage in the third situation of the supply of second source terminal, after power-on reset operation finishes, control circuit is controlled respectively as conducting state and off-state (Fig. 5: S508 and S509) with its another one in the first mains switch and second source switch.

In the third situation, according to the priority orders that sets in advance control circuit, by a control in the first mains switch and second source switch, be conducting state, and be off-state by another control in the first mains switch and second source switch.

One that is controlled as conducting state in the first mains switch and second source switch will be supplied to the first supply voltage of the first power supply terminal or second source terminal or second source voltage to be supplied to load (3,26) (Fig. 5: S505).

According to this embodiment, can realize for the electronic circuit from a plurality of power supplys power supply that selection will be used automatically.

According to the semiconductor integrated circuit (212) of preferred embodiment, also comprise: the first outside lead-out terminal (T4) and the second outside lead-out terminal (T3), supply the first supply voltage or second source voltage to the first external loading (3) that is taken as respectively load and the second external loading (26).

This semiconductor integrated circuit (212) also comprises output P channel MOS transistor (Mp0), is coupled between the first outside lead-out terminal and the second outside lead-out terminal.

When after power-on reset operation finishes, when any one in the first mains switch and second source switch is controlled as conducting state, output P channel MOS transistor (Mp0) is controlled circuit (21245,21246) and is controlled as conducting state.

Output P channel MOS transistor is controlled as conducting state and makes it possible to, by output P channel MOS transistor and the second outside lead-out terminal (T3), the first supply voltage or second source voltage are supplied to the second external loading (referring to Fig. 2 and 4).

In a further advantageous embodiment, the first outside lead-out terminal (T4) is configured to supply the first supply voltage or second source voltage to first external loading (3) of another semiconductor integrated circuit corresponding to being taken as active equipment.

Output P channel MOS transistor and the second outside lead-out terminal are configured to supply the first supply voltage or second source voltage (referring to Fig. 2) to the second external loading (26) that is taken as battery.

In a further advantageous embodiment, input voltage selects circuit (2124) also to comprise input voltage selector switch (21242) and gate driver circuit (21249).

The input voltage selector switch comprises the first input P channel MOS transistor (Mp1) and the second input P channel MOS transistor (Mp2).The source electrode of the first input P channel MOS transistor is couple to the first power supply terminal.The source electrode of the second input P channel MOS transistor is couple to the second source terminal.

During the power-on reset period of power-on reset circuit (21244), gate driver circuit (21249) both controls the first input P channel MOS transistor of input voltage selector switch and the second input P channel MOS transistor into conducting state.

During the power-on reset period, from the drain electrode of the first input P channel MOS transistor or the drain electrode of the second input P channel MOS transistor, produce the operating voltage (Vcc) (referring to Fig. 4) that will be supplied to power-on reset circuit.

In a further advantageous embodiment, in the first situation, gate driver circuit controls respectively the first input P channel MOS transistor of input voltage selector switch and the second input P channel MOS transistor into conducting state and off-state.

In the second situation, gate driver circuit controls respectively the first input P channel MOS transistor of input voltage selector switch and the second input P channel MOS transistor into conducting state and off-state.

In the third situation, gate driver circuit is according to setting in advance the priority orders of control circuit, by one in the first input P channel MOS transistor of input voltage selector switch and the second input P channel MOS transistor with wherein another is controlled respectively as conducting state and off-state.

In a further advantageous embodiment, input voltage select circuit (2124) also comprise voltage ratio/select circuit (21243), voltage ratio/select circuit to there is first input end (Node1), the second input terminal (Node2) and lead-out terminal.

Voltage ratio/select first input end (Node1) of circuit to be coupled to the drain electrode of the first input P channel MOS transistor of input voltage selector switch.

Voltage ratio/select second input terminal (Node2) of circuit to be coupled to the drain electrode of the second input P channel MOS transistor of input voltage selector switch.

The operating voltage that is supplied to power-on reset circuit be from voltage ratio/select the lead-out terminal of circuit to produce.

Voltage ratio/select the circuit relatively voltage of first input end and the voltage of the second input terminal, to select high voltage, thereby output HIGH voltage is as the operating voltage that is supplied to power-on reset circuit from lead-out terminal (with reference to figure 4).

In a further advantageous embodiment, when the first situation occurring, after power-on reset operation finishes, the first mains switch and second source switch are controlled as respectively conducting state and off-state (Fig. 6: S505) afterwards, occur that input voltage detection circuit (21248) detects second source voltage the 4th kind of situation (Fig. 6: S600) to the supply of second source terminal.

Appearance in response to the 4th kind of situation, the same with the third situation, control circuit is according to setting in advance the priority orders of control circuit, by one in the first mains switch and second source switch with wherein another is controlled respectively as conducting state and off-state.

When the second situation occurring, after power-on reset operation finishes, the first mains switch and second source switch are controlled as respectively off-state and conducting state (Fig. 6: S507) afterwards, occur that input voltage detection circuit (21248) detects the first supply voltage the 5th kind of situation (Fig. 6: S602) to the supply of the first power supply terminal.

Appearance in response to the 5th kind of situation, the same with the third situation, control circuit is according to setting in advance the priority orders of control circuit, by one in the first mains switch and second source switch with wherein another is controlled respectively as conducting state and off-state (Fig. 6: S603).

When the third situation occurring, after power-on reset operation finishes in the first mains switch and second source switch one and wherein another is controlled as respectively conducting state and off-state (Fig. 6: S509) afterwards, occur that input voltage detection circuit (21248) detects second source voltage the 6th kind of situation (Fig. 6: S604) to the supply of second source terminal.

Appearance in response to the 6th kind of situation, the same with the third situation, control circuit is according to setting in advance the priority orders of control circuit, by one in the first mains switch and second source switch with wherein another is controlled respectively as conducting state and off-state (Fig. 6: S605).

In a further advantageous embodiment, when the first situation occurring, after power-on reset operation finishes, the first mains switch and second source switch are controlled as respectively conducting state and off-state (Fig. 8: S505) afterwards, occur that input voltage detection circuit (21248) detects second source voltage the 4th kind of situation (Fig. 8: S600) to the supply of second source terminal.

In response to the appearance of the 4th kind of situation, this semiconductor integrated circuit can be notified to above-mentioned another semiconductor integrated circuit that is taken as the first external loading appearance (Fig. 8: S800) of the 4th kind of situation.

The first notice that occurs the 4th kind of situation in response to indication, control circuit, according to the first indication provided to this semiconductor integrated circuit from above-mentioned another semiconductor integrated circuit, is controlled the first mains switch and second source switch (Fig. 8: S801-S802).

According to the first indication, control circuit controls respectively the first mains switch and second source switch into conducting state and off-state (Fig. 8: S505), or the first mains switch and second source switch are controlled respectively as off-state and conducting state (Fig. 8: S802).

When the second situation occurring, after power-on reset operation finishes, the first mains switch and second source switch are controlled as respectively off-state and conducting state (Fig. 8: S507) afterwards, occur that input voltage detection circuit (21248) detects the first supply voltage the 5th kind of situation (Fig. 8: S602) to the supply of the first power supply terminal.

In response to the appearance of the 5th kind of situation, this semiconductor integrated circuit can be notified to above-mentioned another semiconductor integrated circuit that is taken as the first external loading appearance (Fig. 8: S803) of the 5th kind of situation.

The second notice that occurs the 5th kind of situation in response to indication, control circuit, according to the second indication provided to this semiconductor integrated circuit from above-mentioned another semiconductor integrated circuit, is controlled the first mains switch and second source switch (Fig. 8: S804-S805).

According to the second indication, control circuit controls respectively the first mains switch and second source switch into off-state and conducting state (Fig. 8: S507), or the first mains switch and second source switch are controlled respectively as conducting state and off-state (Fig. 8: S805).

When the third situation occurring, after power-on reset operation finishes in the first mains switch and second source switch one and wherein another is controlled as respectively conducting state and off-state (Fig. 8: S509) afterwards, occur that input voltage detection circuit (21248) detects second source voltage the 6th kind of situation (Fig. 8: S604) to the supply of second source terminal.

In response to the appearance of the 6th kind of situation, this semiconductor integrated circuit can be notified to above-mentioned another semiconductor integrated circuit that is taken as the first external loading appearance (Fig. 8: S806) of the 6th kind of situation.

The third notice that occurs the 6th kind of situation in response to indication, control circuit, according to the 3rd indication provided to this semiconductor integrated circuit from above-mentioned another semiconductor integrated circuit, is controlled the first mains switch and second source switch (Fig. 8: S807-S808).

According to the 3rd indication, control circuit controls respectively the first mains switch and second source switch into conducting state and off-state (Fig. 8: S509), or the first mains switch and second source switch are controlled respectively as off-state and conducting state (Fig. 8: S808).

Also comprise step-down (step-down) DC-DC transducer (2121) and the linear regulator (2122) of coupled in parallel between the first power supply terminal (T1) and the first mains switch (SW1, SW2) according to the semiconductor integrated circuit (212) of a specific embodiment.

Linear regulator plays series controller, and series controller is fast operating after powering up to the supply of the first power supply terminal based on the first supply voltage immediately.

Buck DC-DC transducer (2121) plays switching regulaor, and the power efficiency of switching regulaor is higher than linear regulator (referring to Fig. 2).

As specific embodiment more, a kind of semiconductor integrated circuit is provided, wherein the first power supply terminal (T1) is configured to the supply voltage that can carry based on wireless power to the first power supply terminal (T1) supply by the first Schottky diode (D1), and can couple the AC-DC conversion electric power voltage of interface (24) from AC power supplies to its supply by the second Schottky diode (D2).

Second source terminal (T2) is configured to couple the USB supply voltage (referring to Fig. 2) of interface (23) from USB to second source terminal (T2) supply.

[2] according to exemplary embodiments on the other hand, be the method for operation of a kind of semiconductor integrated circuit (212), the input voltage that this semiconductor integrated circuit (212) is equipped with the first power supply terminal (T1) that can supply the first supply voltage, the second source terminal (T2) that can supply second source voltage, be couple to the first power supply terminal and second source terminal is selected circuit (2124), the first mains switch (SW1, SW2) and second source switch (SW3) (referring to Fig. 2).

Input voltage selects circuit (2124) to comprise power-on reset circuit (21244), input voltage detection circuit (21248) and control circuit (21245,21246).

Input voltage detection circuit (21248) supply to the first power supply terminal (T1) in response to the first supply voltage, produce the first voltage detecting output signal (Vdet1), and the supply in response to second source voltage to second source terminal (T2), produce second voltage and detect output signal (Vdet2).

Detect output signal (Vdet2) in response to power-on reset signal (POR), the first voltage detecting output signal (Vdet1) and second voltage, control circuit (21245,21246) is controlled the first mains switch and second source switch.

The timing changed at the level of power-on reset signal (POR), input voltage detection circuit detects the supply of the first supply voltage to the first power supply terminal, and second source voltage do not detected in the first situation of the supply of second source terminal, after power-on reset operation finishes, control circuit controls respectively the first mains switch and second source switch into conducting state and off-state (Fig. 5: S504 and S505).

After power-on reset operation finishes, the first mains switch and second source switch are controlled respectively as conducting state and off-state, thereby the first mains switch that is controlled as conducting state will be supplied to the first supply voltage of the first power supply terminal to be supplied to load (3,26) (Fig. 5: S505).

The timing changed at the level of power-on reset signal, input voltage detection circuit detects the supply of second source voltage to the second source terminal, and the first supply voltage do not detected in the second situation of the supply of the first power supply terminal, after power-on reset operation finishes, control circuit controls respectively the first mains switch and second source switch into off-state and conducting state (Fig. 5: S506 and S507).

After power-on reset operation finishes, the first mains switch and second source switch are controlled respectively as off-state and conducting state, thereby the second source switch that is controlled as conducting state will be supplied to the second source voltage of second source terminal to be supplied to load (3,26) (Fig. 5: S507).

The timing changed at the level of power-on reset signal, input voltage detection circuit detect the first supply voltage to the supply of the first power supply terminal and second source voltage in the third situation of the supply of second source terminal, after power-on reset operation finishes, control circuit is conducting state by a control in the first mains switch and second source switch, and is off-state (Fig. 5: S508 and S509) by another control in the first mains switch and second source switch.

2. embodiment is described in more detail

Below will illustrate in greater detail embodiment.By the way, in explanation, carry out in institute's drawings attached of optimal mode of the present invention, identical Reference numeral invests respectively in accompanying drawing the assembly with identical function, and will omit its corresponding description.

[the first embodiment]

The configuration of<<Multifunctional honeycomb phone > >

Fig. 1 illustrates the figure of configuration that is equipped with the Multifunctional honeycomb phone of the semiconductor integrated circuit 212 of controlling for battery charging according to the first embodiment.

Multifunctional honeycomb phone shown in Fig. 1 comprises that power transtation mission circuit 1, power receiving circuit 2 and power receive side system 3.Particularly, in the Multifunctional honeycomb phone shown in Fig. 1, from the RF signal of power transmitter side aerial coil 13, by power receiver side aerial coil 25, received, thereby carry out the charging of secondary cell 26 and the power supply that power is received to side system 3.

The power transtation mission circuit of<<transmitter side > >

As shown in Figure 1, the power transtation mission circuit 1 of the transmitter side of wireless power transmitting system is equipped with AC power supplies by AC adapter 10.Power transtation mission circuit 1 comprises micro controller unit (MCU) 11 and power sending controling circuit 12.Micro controller unit (MCU) 11 has authentication processing function 111 and cipher processing function 112.Power sending controling circuit 12 comprises rectification circuit 121 and RF driver 122.RF driver 122 is couple to power transmitter side aerial coil 13.

By being undertaken by 121 pairs of AC power supplies that provide via AC adapter 10 of rectification circuit, DC supply voltage that rectification and smoothing produce is supplied to micro controller unit (MCU) 11 in power transtation mission circuit 1, RF driver 122 etc.Authentication processing function 111 and the cipher processing function 112 of the micro controller unit in power transtation mission circuit 1 (MCU) 11 are carried out respectively mutual authentication processing and cipher processing, mutually authentication processing is for determining whether the user who has corresponding to the Multifunctional honeycomb phone of power receiving circuit 2 is to have legal usufructuary user etc., and cipher processing is for preventing distorting communication data.That is to say the relevant crucial bookkeepings such as the generation of the authentication processing function 221 of the micro controller unit (MCU) 22 that the micro controller unit of power transtation mission circuit 1 (MCU) 11 execution comprise with relevant power receiving circuit 2 and the cipher key of the communication protocol between cipher processing function 222, maintenance, renewal, deletion.

Result, determine that when the micro controller unit (MCU) 11 of power transtation mission circuit 1 user corresponding to the Multifunctional honeycomb phone of power receiving circuit 2 is while having legal usufructuary user, RF driver 122 produces the RF that will offer power transmitter side aerial coil 13 and drives signal in response to the RF oscillation output signal produced from unshowned RF oscillator.In addition, be passed RF driver 122, power transmitter side aerial coil 13 and power receiver side aerial coil 25 from the communication data relevant with authentication processing and cipher processing of the micro controller unit (MCU) 11 of power transtation mission circuit 1 and offer power receiving circuit 2.

The power receiving circuit of<<receiver side > >

As shown in Figure 1, the power receiving circuit 2 of the receiver side of wireless power transmitting system comprises power reception control circuit 21 and micro controller unit (MCU) 22.Micro controller unit (MCU) 22 has authentication processing function 221 and cipher processing function 222.Power reception control circuit 21 comprises rectification circuit 211 and the semiconductor integrated circuit 212 of controlling for the battery charging.

In the wireless power transmitting system shown in Fig. 1, at first by carrying out the communication according to above-mentioned communication protocol between the micro controller unit (MCU) 22 of power transmitter side aerial coil 13 and power receiver side aerial coil 25 micro controller units at power transtation mission circuit 1 (MCU) 11 and power receiving circuit 2.For such communication, provide power receiving circuit 2 so that can between power reception control circuit 21 and micro controller unit (MCU) 22, carry out serial communication, power supply etc.Determine that when the micro controller unit (MCU) 11 of power transtation mission circuit 1 user corresponding to the Multifunctional honeycomb phone of power receiving circuit 2 is while having legal usufructuary user, the RF produced from RF driver 122 drives signal to be passed power transmitter side aerial coil 13 and power receiver side aerial coil 25 offers power receiving circuit 2.

Be supplied to semiconductor integrated circuit 212 and micro controller unit (MCU) 22 by making rectification circuit 211 to drive signal carry out the DC supply voltage that rectification and smoothing produce to the RF that provides via power transmitter side aerial coil 13 and power receiver side aerial coil 25.From rectification circuit 211, be supplied to the DC supply voltage of semiconductor integrated circuit 212 for secondary cell 26 is charged, and even for power being received to side system 3 supply power.

When the power receiver side of wireless power transmitting system is the Multifunctional honeycomb phone, power receive side system 3 comprise application processor, baseband processor, LCD driver IC, RF signal processing semiconductor integrated circuit (RFIC), main storage, such as nonvolatile memory of flash memory etc. etc.

When the power receiver side of wireless power transmitting system is portable personal computer (as dull and stereotyped PC), power receives the hard disk substituted type flash memory that side system 3 also comprises CPU (CPU) and has the mass memory capacity.

In addition, except the DC supply voltage produced by rectification circuit 211, can also couple the USB supply voltage of interface 23 and carry out by the AC power supplies voltage to couple interface 24 from AC power supplies the AC-DC conversion electric power voltage that rectification and smoothing produce from USB semiconductor integrated circuit 212 supplies controlling for the battery charging and this system is provided to power.Correspondingly, for battery charging, control and the semiconductor integrated circuit 212 of system power supply has DC supply voltage from rectification circuit 211, from USB, couples the USB supply voltage of interface 23 and automatically select for battery charging control with to the function of the supply voltage of system supply power from a plurality of supply voltages such as AC-DC conversion electric power voltage that AC power supplies couples interface 24.By the way, USB is the abbreviation of USB

The configuration of the semiconductor integrated circuit of<<control for the battery charging > >

Fig. 2 is the figure that the configuration of the semiconductor integrated circuit 212 of controlling for the battery charging according to the first embodiment illustrated in fig. 1 is shown.

As shown in Figure 2, control for battery charging and the semiconductor integrated circuit 212 of system supply power is comprised to buck DC-DC transducer 2121, linear regulator 2122, USB type detection circuit 2123, input voltage detection circuit 2124, external interface 2125, built-in adjuster 2126 and grid Drive and Control Circuit 2127.In addition, semiconductor integrated circuit 212 comprises P channel MOS transistor Mp0 and switch SW 1, SW2, SW3 and SW4.

Power supply terminal T1 for the first input voltage 1 is supplied the supply voltage of carrying via the wireless power based on power transtation mission circuit 1 of the first Schottky diode D1 and couples the AC-DC conversion electric power voltage of interface 24 by the second Schottky diode D2 from AC power supplies.Power supply terminal T2 for the second input voltage 2 is supplied the USB supply voltage that couples interface 23 from USB.Schottky diode D1 and D2 are used separately as the anti-return equipment between the supply voltage that wireless power based on power transtation mission circuit 1 carries and the AC-DC conversion electric power voltage that couples interface 24 from AC power supplies, on the other hand, also as the voltage transmission equipment for the low forward voltage of comparing with the PN junction diode by power delivery.By the way, the supply voltage that the wireless power based on power transtation mission circuit 1 is carried be scope at 5.5V to the voltage between 20V.The AC-DC conversion electric power voltage that couples interface 24 from AC power supplies is the voltage of about 7V.The USB supply voltage that couples interface 23 from USB is the voltage of 5V.

Inductor L1 and capacitor C1 are couple to buck DC-DC transducer 2121 by outside terminal DDOUT1 (T5) and DDOUT2 (T6).Therefore, buck DC-DC transducer 2121 plays a part powering up while starting the switch mode regulator slower than linear regulator 2122, but has the power efficiency higher than linear regulator 2122.On the other hand, linear regulator 2122 plays the series controller of adjacent immediate operation after powering up.

That is to say the supply voltage of the 5.5V to 20V that buck DC-DC transducer 2121 and linear regulator 2122 are carried from the wireless power of power transtation mission circuit 1 or produce the system power supply voltage of scope at 3.5V to 5V from the AC-DC conversion electric power voltage of about 7V of coupling interface 24 from AC power supplies.Therefore, being passed switch SW 2 and SW4 and outside terminal SYS (T4) from the system power supply voltage of the 5V of buck DC-DC transducer 2121 and linear regulator 2122 is supplied to power to receive side system 3.On the other hand, the USB supply voltage that couples the 5V of interface 23 from USB is passed switch SW 3 and outside terminal SYS (T4) is supplied to power to receive side system 3.

USB type detection circuit 2123 couples the bit rate of the differential data signals D+ of interface 23 and D-or detects USB for the power delivery ability of the power supply terminal T2 of the second input voltage 2 according to USB and couples interface 23 whether corresponding to any one of USB1.1, USB1.0, USB2.0 and USB3.0.

Operator scheme in order to select to start, input voltage detection circuit 2124 is carried out for the voltage detecting of the power supply terminal T1 of the first input voltage 1 with for the voltage detecting of the power supply terminal T2 of the second input voltage 2, and further carries out the switch of switch SW1, SW2, SW3 and SW4 is controlled and to the control of buck DC-DC transducer 2121, built-in adjuster 2126 and grid Drive and Control Circuit 2127.In addition, input voltage detection circuit 2124 has execution provides from the function of the USB type detection data of USB type detection circuit 2123 outputs to micro controller unit (MCU) 22 and power reception side system 3 to the control of USB type detection circuit 2123 with by external interface 2125.

Therefore, external interface 2125 is carried out clock and the serial data interactive communication that receives side system 3 and micro controller unit (MCU) 22 with power.

Built-in adjuster 2126 is by the supply voltage of the wireless power conveying based on power transtation mission circuit 1 via buck DC-DC transducer 2121 or linear regulator 2122 supplies, perhaps supply the AC-DC conversion electric power voltage that couples interface 24 from AC power supplies, or supply couples the USB supply voltage of interface 23 from USB.As a result, produce the operating voltage V of 1.8V from built-in adjuster 2126 _dD18 and the operating voltage V of 3.0V _dD30, and be supplied to micro controller unit (MCU) 22.

P channel MOS transistor Mp0 is transfused to

voltage detecting circuit

2124 and 2127 drivings of grid Drive and Control Circuit are controlled to on-state, thereby the system power supply voltage of the 3.5V to 5V located to secondary cell 26 supply outside terminal SYS (T4) by outside terminal BAT (T3), carry out the charging to secondary cell 26 thus.For example, secondary cell 26 is to be built in lithium ion battery in the Multifunctional honeycomb phone etc., and its charging current is the relatively large electric current of scope from about 0.5A to about 1.0A.

In addition, grid Drive and Control Circuit 2127 so that the P channel MOS transistor Mp0 mode of two-way admittance between terminal SYS (T4) and outside terminal BAT (T3) externally, produces the output signal of the grid for driving P channel MOS transistor Mp0.Therefore, during carrying out the charging of secondary cell 26, the charging current of secondary cell 26 flows to outside terminal BAT (T3) from outside terminal SYS (T4).On the other hand, in contrast, during the battery-operated period that secondary cell 26 is discharged, the discharging current of secondary cell 26 flows to outside terminal SYS (T4) from outside terminal BAT (T3).In addition, thus grid Drive and Control Circuit 2127 has carries out to the charging and discharging electric current in the charging and discharging operating period to secondary cell 26 that Current Control prevents from overcharging or the function of over-discharge can.

The function of the outside terminal of<<semiconductor integrated circuit > >

Fig. 3 is the figure of function that the outside terminal of the semiconductor integrated circuit 212 of controlling for battery charging according to the first embodiment illustrated in fig. 2 is shown.

As shown in Figure 3, the external power terminal for the first input voltage 1 has the supply voltage of the wireless power conveying of supply based on power transtation mission circuit 1 or couples the function of the AC-DC conversion electric power voltage of interface 24 from AC power supplies by the first Schottky diode D1 and the second Schottky diode D2 supply.

In addition, there is supply for the external power terminal of the second input voltage 2 and couple the function of the USB supply voltage of interface 23 from USB.

Have and couple the function that interface 23 provides the noninverting input signal D+ of differential data for USB for the external power terminal of differential data D+.

In addition, have and couple the function that interface 23 provides the rp input signal D-of differential data for USB for the external power terminal of differential data D-.

Outside input/output terminal for clock has the function of carrying out about the interactive communication of clock for external interface 2125.

In addition, the outside input/output terminal for serial data has the function of carrying out about the interactive communication of serial data for external interface 2125.

Outside terminal DDOUT1 has the function of the switching regulaor operation output switch output signal based on buck DC-DC transducer 2121 places.

In addition, outside terminal DDOUT2 has the function of the output voltage of output buck DC-DC transducer 2121, the low pass filter of this output voltage through consisting of inductor L1 and capacitor C1.

Outside terminal SYS has the function that receives side system 3 output supply voltages to power.

Outside terminal BAT has the function that couples secondary cell 26.

Outside terminal V _dD18 have to the operating voltage V of micro controller unit (MCU) 22 output 1.8V _dD18 function.

Outside terminal V _dD30 have to the operating voltage V of micro controller unit (MCU) 22 output 3.0V _dD30 function.

The configuration of the input voltage detection circuit of<<semiconductor integrated circuit > >

Fig. 4 illustrates the semiconductor integrated circuit according to the first embodiment 212 illustrated in fig. 2 figure for the configuration of the input voltage detection circuit 2124 of select operating mode when starting.

As shown in Figure 4, input voltage detection circuit 2124 comprise linear regulator 21241, input voltage selector switch 21242, voltage ratio/select circuit 21243, the first reference voltage generator Ref_Gen1, the first buffer circuit BA1, the second buffer circuit BA2 and power-on reset circuit 21244.In addition, input voltage detection circuit 2124 comprises control logic circuit 21245, input voltage selector switch control logic circuit 21246, clock generator 21247, input voltage detection circuit 21248 and gate driver circuit 21249.

As shown in the upper left quarter of Fig. 4, for the power supply terminal T1 of input voltage 1, be supplied the supply voltage that the wireless power based on power transtation mission circuit 1 carries and the AC-DC conversion electric power voltage that couples interface 24 from AC power supplies.Power supply terminal T2 for the second input voltage 2 is supplied the USB supply voltage that couples interface 23 from USB.

Voltage range is converted to the output supply voltage Vout of about 5V for the supply voltage of carrying based on wireless power from 5.5V to 20V or for the AC-DC conversion electric power voltage of the power supply terminal T1 of the first input voltage 1 by linear regulator 21241.Approximately the output supply voltage of 5V is supplied to the source electrode of the P channel MOS transistor Mp1 of gate driver circuit 21249 and input voltage selector switch 21242.

The USB supply voltage that to be supplied to voltage for the power supply terminal T2 of the second input voltage 2 be 5V couples interface 23 from USB is supplied to the source electrode of the P channel MOS transistor Mp2 of input voltage selector switch 21242.

The grid of the P channel MOS transistor Mp1 of input voltage selector switch 21242 is driven by the first grid drive output signal Mp1_G of gate driver circuit 21249.The grid of the P channel MOS transistor Mp2 of input voltage selector switch 21242 is driven by the second grid drive output signal Mp2_G of gate driver circuit 21249.By during the power-on reset period of describing in detail, when powering up, the first grid drive output signal Mp1_G of gate driver circuit 21249 and second grid drive output signal Mp2_G are set to low level below.Therefore, the P channel MOS transistor Mp1 of input voltage selector switch 21242 and P channel MOS transistor Mp2 are controlled as conducting state.

Voltage ratio/select circuit 21243 to comprise P channel MOS transistor Mp3, P channel MOS transistor Mp4 and differential amplifier DA1.Therefore, voltage ratio/select the circuit 21243 relatively voltage of first node Node1 and the voltage of Section Point Node2, select thus the high voltage in these two voltages, and produce it as output voltage V cc.First node Node1 is couple to the drain electrode of P channel MOS transistor Mp3 and the inverting input "-" of differential amplifier DA1.Section Point Node2 is couple to the drain electrode of P channel MOS transistor Mp4 and the non-inverting input "+" of differential amplifier DA1.The noninverting output "+" of differential amplifier DA1 and reversed-phase output "-" are couple to respectively the grid of P channel MOS transistor Mp3 and the grid of P channel MOS transistor Mp4.The source electrode of P channel MOS transistor Mp3 with together with the source electrode of P channel MOS transistor Mp4 is coupled in to produce output voltage V cc.

Voltage ratio/select the output voltage V cc of circuit 21243 to be supplied to differential amplifier DA1, the first reference voltage generator Ref_Gen1, the first buffer circuit BA1 and the second buffer circuit BA2, as operating power voltage.

The first reference voltage generator Ref_Gen1 make from voltage ratio/select the output voltage V cc of circuit 21243 outputs can be used as operating power voltage, thereby generation reference voltage V _rEF.

The first buffer circuit BA1 and the second buffer circuit BA2 are in response to the reference voltage V produced from the first reference voltage generator Ref_Gen1 _rEFproduce and reference voltage V respectively _rEFthe proportional analog circuit supply voltage of level AV _dDwith digital circuit power source voltage DV _dD.

Power-on reset circuit 21244 comprises the second reference voltage generator Ref_Gen2, differential amplifier DA2, resistor Rp, capacitor Cp and the 3rd buffer circuit BA3.The second reference voltage generator Ref_Gen2 of power-on reset circuit 21244 and differential amplifier DA2 are supplied the digital circuit power source voltage DV produced by the second buffer circuit BA2 _dD.The non-inverting input "+" of differential amplifier DA2 and inverting input "-" are provided respectively digital circuit power source voltage DV _dDwith the reference voltage V produced from the second reference voltage generator Ref_Gen2 _bB.

The output voltage of the differential amplifier DA2 of power-on reset circuit 21244 is supplied to resistor R _pan end.Resistor R _pthe other end be couple to capacitor C _pan end and the input of the 3rd buffer circuit BA3.Capacitor C _pthe other end be couple to earth potential.The low level power-on reset signal POR produced from the 3rd buffer circuit BA3 during the power-on reset period is provided for the inverted reset input terminal/Reset of control logic circuit 21245 and the inverted reset input terminal/Reset of input voltage selector switch control logic circuit 21246.

From be supplied by voltage ratio/select the output voltage V cc that circuit 21243 carries and the digital circuit power source voltage DV carried by the second buffer circuit BA2 _dDthe clock signal that produces of clock generator 21247 be provided for the clock input terminal CLK of control logic circuit 21245 and the clock input terminal CLK of input voltage selector switch control logic circuit 21246.

The all operations were of the semiconductor integrated circuit according to the first embodiment 212 shown in control logic circuit 21245 control charts 2 of input voltage detection circuit 2124.That is to say, the analog circuit that is couple to input voltage detection circuit 2,124 2128 shown in Fig. 4 comprises the analog circuit of buck DC-DC transducer 2121, linear regulator 2122, USB type detection circuit 2123, built-in adjuster 2126 and the grid Drive and Control Circuit 2127 of the semiconductor integrated circuit 212 shown in Fig. 2.Therefore, the operation of these analog circuits all the control logic circuit 21245 of input voltage detection circuit 2124 as shown in Figure 4 control.By the way, analog circuit 2128 be supplied from voltage ratio/select output voltage V cc that circuit 21243 carries and from the analog circuit supply voltage AV of the first buffer circuit BA1 output _dD.

In addition, similarly, the operation of the input voltage selector switch control logic circuit 21246 also control logic circuit 21245 of input voltage detection circuit 2124 is as shown in Figure 4 controlled.

In addition, similarly, the operation of switch SW 1, SW2, SW3 and the SW4 shown in Fig. 2, built-in adjuster 2126 and the grid Drive and Control Circuit 2127 also control logic circuit 21245 of input voltage detection circuit 2124 is as shown in Figure 4 controlled.

Input voltage detection circuit 21248 be supplied from voltage ratio/select output voltage V cc that circuit 21243 carries and from the analog circuit supply voltage AV of the first buffer circuit BA1 output _dD.The power-on reset period in the past after, input voltage detection circuit 21248 detects that power supply terminal T1 place for the first input voltage 1 carries based on wireless power or the level of the supply voltage that AC-DC changes and for the level of the power supply terminal T2 USB of the place supply voltage of the second input voltage 2.Voltage detecting output signal Vdet1 and the Vdet2 of 2 positions of exporting from input voltage detection circuit 21248 as a result, are provided for control logic circuit 21245 and input voltage selector switch control logic circuit 21246.That is to say, voltage detecting output signal Vdet1 indicates whether to have supplied to the power supply terminal T1 for the first input voltage 1 testing result of the supply voltage based on wireless power conveying or AC-DC conversion.And voltage detecting output signal Vdet2 indicates whether to have supplied to the power supply terminal T2 for the second input voltage 2 testing result of USB supply voltage.

After past power-on reset period, in the first grid drive output signal Mp1_G of gate driver circuit 21249 and second grid drive output signal Mp2_G one and another signal by input voltage selector switch control logic circuit 21246 outputs from responding 2 voltage detecting output signal Vdet1 and Vdet2 wherein are set to respectively low level and high level, carry out thus the automatic selection of the power supply to using.

Consideration detects output signal Vdet1 detection by high level voltage and has supplied supply voltage to the power supply terminal T1 for the first input voltage 1, detects output signal Vdet2 by low level voltage and detects the situation of to the power supply terminal T2 for the second input voltage 2, not supplying supply voltage.In this case, different voltage detecting output signal Vdet1 and the Vdet2 in response to level, control logic circuit 21245 will be positioned at the switch SW 2 of 212 inside of the semiconductor integrated circuit according to the first embodiment shown in Fig. 2 and control as conducting state, on the other hand, switch SW 3 is controlled as off-state.As a result, from the voltage of the supply of the power supply terminal T1 for the first input voltage 1, be used to via buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.In addition, in this case, gate driver circuit 21249 is set to respectively low level and high level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.In addition, voltage ratio/select circuit 21243 to detect the voltage of the voltage of first node Node1 higher than Section Point Node2, and produce from the voltage of the first node Node1 of the supply of the power supply terminal T1 for the first input voltage 1, as voltage ratio/select the output voltage V cc of circuit 21243.

Consideration detects output signal Vdet1 detection by low level voltage and does not supply supply voltage to the power supply terminal T1 for the first input voltage 1, detects output signal Vdet2 by high level voltage and detects the situation of to the power supply terminal T2 for the second input voltage 2, having supplied supply voltage.In this case, different voltage detecting output signal Vdet1 and the Vdet2 in response to level, control logic circuit 21245 will be positioned at the switch SW 2 of 212 inside of the semiconductor integrated circuit according to the first embodiment shown in Fig. 2 and control as off-state, on the other hand, switch SW 3 is controlled as conducting state.As a result, from the voltage of the supply of the power supply terminal T2 for the second input voltage 2, be used to via switch SW 3 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.In addition, in this case, gate driver circuit 21249 is set to respectively high level and low level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.In addition, voltage ratio/select circuit 21243 to detect the voltage of the voltage of Section Point Node2 higher than first node Node1, and produce from the voltage of the Section Point Node2 of the supply of the power supply terminal T2 for the second input voltage 2, as voltage ratio/select the output voltage V cc of circuit 21243.

2 the voltage detecting output signal Vdet1 of consideration by input voltage detection circuit 21248 and Vdet2 detect based on wireless power simultaneously and carry or the supply voltage of the AC-DC conversion situation to the supply of the power supply terminal T1 for the first input voltage 1 and USB supply voltage to the supply of the power supply terminal T2 for the second input voltage 2.In this case, in response to the level of voltage detecting output signal Vdet1 and Vdet2, be all high, the level of the output supply voltage Vout of about 5V of control logic circuit 21245 linear adjustment adjusters 21241.

That is to say, when the supply voltage of the power supply terminal T1 for the first input voltage 1 simultaneously be detected when the supply voltage of the power supply terminal T2 with for the second input voltage 2 has precedence over for the supply voltage of the power supply terminal T2 of the second input voltage 2, the output supply voltage Vout of about 5V of linear regulator 21241 is set to for example 5.2V higher than the USB supply voltage that couples interface 23 from USB, and wherein this USB supply voltage has the 5V voltage be supplied to for the power supply terminal T2 of the second input voltage 2.First grid drive output signal Mp1_G and the second grid drive output signal Mp2_G of the gate driver circuit 21249 of being controlled by control logic circuit 21245 in addition, are respectively set to low level and high level.Result, voltage ratio/select circuit 21243 to detect the voltage of the voltage of first node Node1 higher than Section Point Node2, and produce for the supply voltage of the power supply terminal T1 of the first input voltage 1 as voltage ratio/select the output voltage V cc of circuit 21243.In addition, control logic circuit 21245 will be arranged in the switch SW 2 of the semiconductor integrated circuit according to the first embodiment 212 shown in Fig. 2 to be controlled as conducting state, on the other hand, switch SW 3 is controlled as off-state.As a result, from the voltage of the supply of the power supply terminal T1 for the first input voltage 1, be used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

In contrast, when the priority of the supply voltage of the power supply terminal T2 for the second input voltage 2 during higher than the supply voltage of the power supply terminal T1 for the first input voltage 1, the output supply voltage Vout of about 5V of linear regulator 21241 is set to for example 4.8V lower than the USB supply voltage that couples interface 23 from USB, and wherein this USB supply voltage has the 5V voltage be supplied to for the power supply terminal T2 of the second input voltage 2.First grid drive output signal Mp1_G and the second grid drive output signal Mp2_G of the gate driver circuit 21249 of being controlled by control logic circuit 21245 in addition, are respectively set to high level and low level.Result, voltage ratio/select circuit 21243 to detect the voltage of the voltage of Section Point Node2 higher than first node Node1, and produce from the voltage of the Section Point Node2 of the power supply terminal T2 for the second input voltage 2 as voltage ratio/select the output voltage V cc of circuit 21243.In addition, control logic circuit 21245 will be arranged in the switch SW 2 of the semiconductor integrated circuit according to the first embodiment 212 shown in Fig. 2 to be controlled as off-state, on the other hand, switch SW 3 is controlled as conducting state.As a result, from the voltage of the supply of the power supply terminal T2 for the second input voltage 2, be used to by switch SW 3 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

On the other hand, before past power-on reset period, the first grid drive output signal Mp1_G of gate driver circuit 21249 and second grid drive output signal Mp2_G are set to low level by the output signal of the input voltage selector switch control logic circuit 21246 in response to low level power-on reset signal POR.As a result, input voltage selector switch 21242 comprises P channel MOS transistor Mp1 and P channel MOS transistor Mp2 are controlled as conducting state.

The automatic selection operation of the voltage of<<use > >

Fig. 5 is the figure that the operation of Fig. 2 and the 4 shown semiconductor integrated circuit according to the first embodiment 212 power supply that selection will be used automatically from a plurality of power supplys is shown.

As shown in the step S500 of Fig. 5, at supply voltage, be supplied to for the power supply terminal T1 of the first input voltage 1 with for the initial setting up state before the power supply terminal T2 of the second input voltage 2, the first grid drive output signal Mp1_G of gate driver circuit 21249 and second grid drive output signal Mp2_G are set to low level.As a result, the P channel MOS transistor Mp1 of input voltage selector switch 21242 and P channel MOS transistor Mp2 are controlled as conducting state.

At following step S501, to the power supply terminal T1 for the first input voltage 1 with at least any one supply supply voltage of the power supply terminal T2 of the second input voltage 2.That is to say the supply voltage of carrying to the wireless power of the supply of the power supply terminal T1 for the first input voltage 1 based on power transtation mission circuit 1 and the AC-DC conversion electric power voltage that couples interface 24 from AC power supplies.Alternatively, couple the USB supply voltage of interface 23 from USB to the supply of the power supply terminal T2 for the second input voltage 2.

At following step S502, due to digital circuit power source voltage DV _dDin response to the power supply of step S501, rise, so carry out the power-on reset operation of power-on reset circuit 21244.

When the power-on reset operation of step S502 finishes, at following step S503, carry out the detection to a plurality of supply voltages.That is to say, at step S503, input voltage detection circuit 21248 detects that power supply terminal T1 place for the first input voltage 1 carries based on wireless power or the level of the supply voltage that AC-DC changes and for the level of the USB supply voltage at the power supply terminal T2 place of the second input voltage 2.As a result, produce voltage detecting output signal Vdet1 and the Vdet2 of two from input voltage detection circuit 21248.Voltage detecting output signal Vdet1 indicates whether to have supplied to the power supply terminal T1 for the first input voltage 1 testing result of the supply voltage based on wireless power conveying or AC-DC conversion.Voltage detecting output signal Vdet2 indicates whether to have supplied to the power supply terminal T2 for the second input voltage 2 testing result of USB supply voltage.

In the situation that above-mentioned steps S503 detects supply voltage, when the power supply terminal T1 only detected to for the first input voltage 1 has supplied supply voltage, and do not detect while to the power supply terminal T2 for the second input voltage 2, supplying supply voltage, automatically select the processing of operation to advance to step S504.

That is to say, at following step S505, gate driver circuit 21249 is carried in response to wireless power only detected at step S504, and first grid drive output signal Mp1_G and second grid drive output signal Mp2_G are set to respectively to low level and high level.Therefore, P channel MOS transistor Mp1 and the P channel MOS transistor Mp2 due to input voltage selector switch 21242 is controlled as respectively conducting and off-state, the initial operation that the startup wireless power is carried.In addition, at step S505, control logic circuit 21245 will be arranged in the switch SW 2 of the semiconductor integrated circuit according to the first embodiment 212 shown in Fig. 2 to be controlled as conducting state, on the other hand, switch SW 3 is controlled as off-state.Therefore, the supply voltage that the wireless power of power supply terminal T1 based on from for the first input voltage 1 is carried is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

In the situation that above-mentioned steps S503 detects supply voltage, when the power supply terminal T2 only detected to for the second input voltage 2 has supplied supply voltage, and do not detect while to the power supply terminal T1 for the first input voltage 1, supplying supply voltage, automatically select the processing of operation to advance to step S506.

That is to say, at following step S507, gate driver circuit 21249, in response at step S506, the USB power delivery only being detected, is set to respectively high level and low level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.Therefore, P channel MOS transistor Mp1 and the P channel MOS transistor Mp2 due to input voltage selector switch 21242 is controlled as respectively disconnection and conducting state, the initial operation of startup USB power delivery.In addition, at step S507, control logic circuit 21245 will be arranged in the switch SW 2 of the semiconductor integrated circuit according to the first embodiment 212 shown in Fig. 2 to be controlled as off-state, on the other hand, switch SW 3 is controlled as conducting state.Therefore, the supply voltage of the USB power delivery of the power supply terminal T2 based on from for the second input voltage 2 is used to by switch SW 3 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

In the situation that above-mentioned steps S503 detects supply voltage, when both detecting to the supply of the power supply terminal T1 for the first input voltage 1 supply voltage, detect again while to the power supply terminal T2 for the second input voltage 2, having supplied supply voltage, automatically select the processing of operation to advance to step S508.

That is to say, at following step S509, in response to wireless power detected at step S508, carry and the USB power delivery, gate driver circuit 21249 is set to respectively low level and high level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G, in order to carry and authorize the priority higher than the USB power delivery to wireless power.Correspondingly, P channel MOS transistor Mp1 and the P channel MOS transistor Mp2 due to input voltage selector switch 21242 is controlled as respectively conducting and off-state, the initial operation that the startup wireless power is carried.In addition, at step S509, control logic circuit 21245 will be arranged in the switch SW 2 of the semiconductor integrated circuit according to the first embodiment 212 shown in Fig. 2 to be controlled as conducting state, on the other hand, switch SW 3 is controlled as off-state.Correspondingly, the supply voltage that the wireless power of power supply terminal T1 based on from for the first input voltage 1 is carried is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.Therefore, at step S509, to wireless power, carry the reason authorize higher than the priority of USB power delivery to be, the current driving ability that carries out the wireless power conveying by power transmitter side aerial coil 13 and power receiver side aerial coil 25 from power receiving circuit 2 generally couples the current driving ability of interface 23 higher than USB.

[the second embodiment]

The another kind operation of the voltage that selection will be used of<<automatically > >

Fig. 6 is the figure that the operation of the power supply of automatic choice for use from a plurality of power supplys by Fig. 2 and the 4 shown semiconductor integrated circuit according to the second embodiment 212 is shown.

The initial operation of the power supply that selection will be used automatically for the first time from a plurality of power supplys shown in the 212 executed Fig. 5 of the semiconductor integrated circuit according to the first embodiment shown in Fig. 2 and 4.

As shown in Figure 6, below the semiconductor integrated circuit according to the second embodiment 212 shown in Fig. 2 of description and 4 can be carried out to the initial operation of the power supply of choice for use automatically for the first time from a plurality of power supplys, and can carry out even in the situation that additionally supply the subsequent operation of the follow-up supply voltage voltage that further selection is used automatically.

Due in the content of operation of the S500 to S509 of each step according to the second embodiment shown in Fig. 6 and Fig. 5, describe the content of operation of the S500 to S509 of the corresponding steps according to the first embodiment identical, so will the descriptions thereof are omitted.

After the initial operation of carrying at the wireless power of the step S505 shown in Fig. 6, at following step S600, to the supply of the power supply terminal T2 for the second input voltage 2, couple the USB supply voltage of interface 23 from USB.As a result, at step S600, after detecting the wireless power conveying, the USB power delivery additionally detected.

Following step S601 after step S600 additionally detects the USB power delivery, gate driver circuit 21249 is set to respectively low level and high level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G, in order to carry and authorize the priority higher than the USB power delivery to wireless power, this is with just the same according to the step S509 in Fig. 5 of the first embodiment.Correspondingly, at step S601, the P channel MOS transistor Mp1 of input voltage selector switch 21242 and P channel MOS transistor Mp2 are controlled respectively as conducting state and off-state.So start the continuation operation that wireless power is carried.In addition, at step S601, the switch SW 2 that control logic circuit 21245 will be arranged in the semiconductor integrated circuit according to the first embodiment 212 shown in Fig. 2 remains on conducting state, on the other hand, switch SW 3 is remained on to off-state.Correspondingly, the supply voltage that the wireless power of power supply terminal T1 based on from for the first input voltage 1 is carried is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.Therefore, even also to wireless power, carry the reason authorize higher than the priority of USB power delivery to be at step S601, the current driving ability that carries out the wireless power conveying by the power transmitter side aerial coil 13 shown in Fig. 1 and power receiver side aerial coil 25 from power receiving circuit 2 generally couples the current driving ability of interface 23 higher than USB.

After the initial operation of the USB of the step S507 shown in Fig. 6 power delivery, at following step S602, the supply voltage of carrying to the wireless power of the supply of the power supply terminal T1 for the first input voltage 1 based on power transtation mission circuit 1.As a result, at step S602, after the USB power delivery being detected, wireless power additionally detected and carry.

Wireless power additionally detected at step S602 and carry following step S603 afterwards, gate driver circuit 21249 is changed into low level by first grid drive output signal Mp1_G from high level, and second grid drive output signal Mp2_G is changed into to high level from low level, in order to carry and authorize the priority higher than the USB power delivery to wireless power.As a result, at step S603, carry out the conversion operations of carrying from the USB power delivery to wireless power.At this step S603, control logic circuit 21245 will be arranged in the switch SW 2 of the semiconductor integrated circuit according to the first embodiment 212 shown in Fig. 2 and change into conducting state from off-state, on the other hand, switch SW 3 is changed into to off-state from conducting state.Result, the supply voltage that the wireless power of power supply terminal T1 based on from for the first input voltage 1 is carried is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.Therefore, even also to wireless power, carry the reason authorize higher than the priority of USB power delivery to be at step S603, the current driving ability that carries out the wireless power conveying by power transmitter side aerial coil 13 and power receiver side aerial coil 25 from power receiving circuit 2 generally couples the current driving ability of interface 23 higher than USB.

After the initial operation of carrying at the wireless power of the step S509 shown in Fig. 6, at following step S604, to the supply of the power supply terminal T2 for the second input voltage 2, couple the USB supply voltage of interface 23 from USB.As a result, at this step S604, after the wireless power conveying being detected, the USB power delivery additionally again detected.

Following step S605 after step S604 detects the USB power delivery again, gate driver circuit 21249 is set to respectively low level and high level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G, in order to carry and to authorize the priority higher than the USB power delivery to wireless power, identical according to the step S509 of the first embodiment shown in this and Fig. 5.Correspondingly, at step S605, the P channel MOS transistor Mp1 of input voltage selector switch 21242 and P channel MOS transistor Mp2 are controlled as respectively conducting state and off-state.So start the continuation operation that wireless power is carried.In addition, at this step S605, the switch SW 2 that control logic circuit 21245 will be arranged in the semiconductor integrated circuit according to the first embodiment 212 shown in Fig. 2 remains on conducting state, on the other hand, switch SW 3 is remained on to off-state.Correspondingly, the supply voltage that the wireless power of power supply terminal T1 based on from for the first input voltage 1 is carried is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.Therefore, even also to wireless power, carry the reason authorize higher than the priority of USB power delivery to be at step S601, the current driving ability that carries out the wireless power conveying by the power transmitter side aerial coil 13 shown in Fig. 1 and power receiver side aerial coil 25 from power receiving circuit 2 generally couples the current driving ability of interface 23 higher than USB.

The oscillogram of the each several part of<<semiconductor integrated circuit > >

Fig. 7 is illustrated in the operation of automatically selecting the power supply that uses according to the second embodiment from a plurality of power supplys illustrated in fig. 6 at step S506, S507, S602 and S603, the figure of the waveform of the each several part of Fig. 2 and the 4 shown semiconductor integrated circuit according to the second embodiment 212.

As shown in Figure 7, at step S506, by the power supply terminal T2 to for the second input voltage 2 supply supply voltage, for the USB supply voltage of the power supply terminal T2 of the second input voltage 2, start to rise.When the rising of USB supply voltage reaches the second detection threshold voltage, the voltage detecting output signal Vdet2 of input voltage detection circuit 21248 changes into high level from low level.

In response to the rising of USB supply voltage, voltage ratio/select the output voltage V cc of circuit 21243 to start to rise.In addition, in response to voltage ratio/select the rising of the output voltage V cc of circuit 21243, the digital circuit power source voltage DV produced from the second buffer circuit BA2 _dDstart to rise.As digital circuit power source voltage DV _dDreach the reference voltage V corresponding to the second reference voltage generator Ref_Gen2 _bBthe 3rd detection threshold voltage the time, the output of the differential amplifier DA2 of power-on reset circuit 21244 is changed into high level from low level, thus the power-on reset period of the charging of the resistor RP in the time-based constant circuit and capacitor CP starts.When the terminal voltage Vc applied as the capacitor CP across time constant circuit reaches corresponding to the 4th detection threshold voltage of the threshold voltage of the 3rd buffer circuit BA3, power-on reset signal POR changes into high level from low level, thereby the power-on reset operation of control logic circuit 21245 and input voltage selector switch control logic circuit 21246 completes.

Along with the end of power-on reset operation, the low level voltage of 21248 pairs of input voltage detection circuits 21248 of input voltage detection circuit detects output signal Vdet1 and high level voltage detection output signal Vdet2 makes response.Correspondingly, the control that first grid drive output signal Mp1_G and second grid drive output signal Mp2_G are undertaken by input voltage selector switch control logic circuit 21246 and gate driver circuit 21249 is set to respectively high level and low level.Correspondingly, because the P channel MOS transistor Mp1 of input voltage selector switch 21242 and P channel MOS transistor Mp2 are controlled respectively as off-state and conducting state, so, wireless power is carried and is controlled as off-state, the USB power delivery is controlled as conducting state, has carried out thus the automatic selection of the power supply to using.

In this state, at the step S602 of Fig. 6, by the supply of the power supply terminal T1 to the first input voltage 1 supply voltage, the supply voltage that the wireless power of the power supply terminal T1 based on from for the first input voltage 1 is carried starts to rise.When the supply voltage rising of carrying based on wireless power reaches the first detection threshold voltage, the voltage detecting output signal Vdet1 of input voltage detection circuit 21248 changes into high level from low level.

High level voltage in response to input voltage detection circuit 21248 detects output signal Vdet1 and Vdet2, and the input voltage switch index signal provided to input voltage selector switch control logic circuit 21246 from control logic circuit 21245 changes to high level from low level.By input voltage selector switch control logic circuit 21246 and gate driver circuit 21249 control that the change from low level to high level is carried out in response to the input voltage switch index signal, first grid drive output signal Mp1_G changes into low level from high level, and second grid drive output signal Mp2_G changes into high level from low level on the other hand.As a result, in input voltage selector switch 21242, P channel MOS transistor Mp1 changes into conducting state from off-state, and P channel MOS transistor Mp2 changes into off-state from conducting state.In addition, because the switch SW 2 that is arranged in semiconductor integrated circuit 212 enters conducting state, switch SW 3 enters off-state, and the USB power delivery that priority is low is controlled as off-state, and the high wireless power conveying of priority is controlled as conducting state.

[the 3rd embodiment]

Fig. 8 is the figure illustrated by the operation of Fig. 2 and the 4 shown semiconductor integrated circuit according to the 3rd embodiment 212 power supply that selection will be used automatically from a plurality of power supplys.

The advantage of the operation of the power supply that automatically selecting from a plurality of power supplys according to the second embodiment shown in Fig. 6 used is, this operation can be in the semiconductor integrated circuit according to the second embodiment 212 shown in Fig. 2 and 4 execution of almost Perfect, but on the other hand, the problem of this operation is, the degree of freedom of automatically selecting is low.That is to say, battery-operated electronic equipment (such as Multifunctional honeycomb phone, dull and stereotyped PC etc.) needs to improve the degree of freedom of the operation of the power supply that selection is used automatically from a plurality of power supplys, so that reply user's miscellaneous thoughts.

Automatically the program of selecting the operation of the power supply used can receive by the power that is couple to the semiconductor integrated circuit according to the 3rd embodiment 212 shown in Fig. 2 and 4 in the nonvolatile memory etc. of side system 3 shown in Fig. 8 according to the 3rd embodiment from a plurality of power supplys improves the degree of freedom.That is to say, because nonvolatile memory (as flash memory etc.) is couple to application processor and baseband processor that power receives side system 3, can use nonvolatile memory to improve the degree of freedom of automatically selecting the operation of the power supply that uses from a plurality of power supplys.

Identical from the content of operation of the content of operation of each step of step S500 to S604 and the corresponding steps according to the second embodiment shown in Fig. 6 according to the 3rd embodiment due to shown in Fig. 8, so the descriptions thereof are omitted.

After the S600 of step shown in Fig. 8 additionally detects the USB power delivery, at following step S800, the information about the USB power delivery additionally detected at this step S600 is received to application processor and the baseband processor of side system 3 from semiconductor integrated circuit 212 by external interface 2125 notices to power.

Following step S801 after step S800 notice power receives side system 3, receive the indication information that the outputs such as the application processor of side system 3 or baseband processor indicate whether to exist the conversion between USB power delivery and wireless power conveying from power.

When step S801 output indication is transformed into the indication information of USB power delivery from the wireless power conveying, at following step S802, gate driver circuit 21249 is set to respectively high level and low level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.Correspondingly, because the P channel MOS transistor Mp1 of input voltage selector switch 21242 and P channel MOS transistor Mp2 are controlled as off-state and conducting state respectively, so carry the operation that is converted to the USB power delivery to be performed from wireless power.In addition, at step S802, control logic circuit 21245 will be arranged in shown in Fig. 2 according to the switch SW 2 of the semiconductor integrated circuit 212 of the 3rd embodiment changes into off-state from conducting state, on the other hand, switch SW 3 is changed into to conducting state from off-state.Correspondingly, the supply voltage of the USB power delivery of the power supply terminal T2 based on from for the second input voltage 2 is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

On the other hand, when step S801 output indication not from wireless power carry be transformed into the USB power delivery do not change indication information the time, automatically select the processing of operation to turn back to step S505, wherein gate driver circuit 21249 remains on respectively low level and high level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.Correspondingly, because P channel MOS transistor Mp1 and the P channel MOS transistor Mp2 of input voltage selector switch 21242 remains on respectively conducting state and off-state, so the initial operation that keeps wireless power to carry.In addition, at this step S505, the switch SW 2 that control logic circuit 21245 will be arranged in the semiconductor integrated circuit according to the 3rd embodiment 212 shown in Fig. 2 remains on on-state, on the other hand, switch SW 3 is remained on to off-state.Correspondingly, the supply voltage that the wireless power of power supply terminal T1 based on from for the first input voltage 1 is carried is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

After the step S602 shown in Fig. 8 additionally detects the wireless power conveying, at following step S803, the information about the wireless power conveying additionally detected at this step S602 is received to application processor and the baseband processor of side system 3 from semiconductor integrated circuit 212 by external interface 2125 notices to power.

Following step S804 after step S803 notice power receives side system 3, receive the indication information that the outputs such as the application processor of side system 3 or baseband processor indicate whether to exist the conversion between USB power delivery and wireless power conveying from power.

When step S804 output indication is converted to the indication information of wireless power conveying from the USB power delivery, at following step S805, gate driver circuit 21249 is set to respectively low level and high level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.Correspondingly, because the P channel MOS transistor Mp1 of input voltage selector switch 21242 and P channel MOS transistor Mp2 are controlled as conducting state and off-state respectively, so carry out from the USB power delivery, be transformed into the operation that wireless power is carried.In addition, at step S805, control logic circuit 21245 will be arranged in shown in Fig. 2 according to the switch SW 2 of the semiconductor integrated circuit 212 of the 3rd embodiment changes into conducting state from off-state, on the other hand, switch SW 3 is changed into to off-state from conducting state.Correspondingly, the supply voltage that the wireless power of power supply terminal T1 based on from for the first input voltage 1 is carried is used to the charging to secondary cell 26 by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, and for power being received to side system 3 supply power.

On the other hand, when from the USB power delivery, be not transformed into that wireless power carries in step S804 output indication do not change indication information the time, automatically select the processing of operation to return to step S507, wherein gate driver circuit 21249 remains on respectively high level and low level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.Correspondingly, because P channel MOS transistor Mp1 and the P channel MOS transistor Mp2 of input voltage selector switch 21242 is maintained at respectively off-state and conducting state, so keep the initial operation of USB power delivery.In addition, at this step S507, the switch SW 2 that control logic circuit 21245 will be arranged in the semiconductor integrated circuit 212 of the 3rd embodiment shown in Fig. 2 remains on off-state, on the other hand, switch SW 3 is remained on to conducting state.Correspondingly, the supply voltage of the USB power delivery of the power supply terminal T2 based on from for the second input voltage 2 is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

After the step S604 shown in Fig. 8 additionally detects the USB power delivery, at following step S806, receive the application processor and the relevant information that the USB power delivery additionally detected of baseband processor notice of side system 3 to power by external interface 2125 from semiconductor integrated circuit 212.

Following step S807 after step S806 notice power receives side system 3, receive the indication information that the outputs such as the application processor of side system 3 or baseband processor indicate whether to exist the conversion between USB power delivery and wireless power conveying from power.

When step S807 output indication is converted to the indication information of USB power delivery from the wireless power conveying, at following step S808, gate driver circuit 21249 is set to respectively high level and low level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.Correspondingly, because the P channel MOS transistor Mp1 of input voltage selector switch 21242 and P channel MOS transistor Mp2 are controlled respectively as off-state and conducting state, carry out from wireless power and carry the operation that is transformed into the USB power delivery.In addition, at step S808, control logic circuit 21245 will be arranged in the switch SW 2 of the semiconductor integrated circuit according to the 3rd embodiment 212 shown in Fig. 2 and change into off-state from conducting state, on the other hand, switch SW 3 be changed into to conducting state from off-state.Correspondingly, the supply voltage of the USB power delivery of the power supply terminal T2 based on from for the second input voltage 2 is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

On the other hand, when step S807 output indication not from wireless power carry be converted to the USB power delivery do not change indication information the time, automatically select the processing of operation to return to step S509, wherein gate driver circuit 21249 remains on respectively low level and high level by first grid drive output signal Mp1_G and second grid drive output signal Mp2_G.Correspondingly, because P channel MOS transistor Mp1 and the P channel MOS transistor Mp2 of input voltage selector switch 21242 is maintained at respectively conducting state and off-state, so the initial operation that keeps wireless power to carry.In addition, at this step S509, the switch SW 2 that control logic circuit 21245 will be arranged in the semiconductor integrated circuit according to the 3rd embodiment 212 shown in Fig. 2 remains on conducting state, and on the other hand, switch SW 3 is remained on to off-state.Correspondingly, the supply voltage that the wireless power of power supply terminal T1 based on from for the first input voltage 1 is carried is used to by buck DC-DC transducer 2121, switch SW 2 and P channel MOS transistor Mp0, secondary cell 26 be charged, and for power being received to side system 3 supply power.

Although based on various, specifically described the foregoing invention that the present inventor makes, the invention is not restricted to embodiment above-mentioned.Undoubtedly, can in the scope that does not break away from its purport, to it, carry out various changes.

For example, the electronic equipment that is equipped with separately the semiconductor integrated circuit proposed to some extent is not limited to the portable personal computer as Multifunctional honeycomb phone, dull and stereotyped PC etc., but can be applied to digital video camcorder, digital still camera, portable music player, Portable DVD player etc.

In addition, the electronic equipment that is equipped with separately the semiconductor integrated circuit proposed to some extent can be applicable to have the functions such as automatic ticket selling system, electronic money the built-in cellular phone of rfid card.

Claims

1. a semiconductor integrated circuit comprises:

The first power supply terminal, can supply the first supply voltage;

The second source terminal, can supply second source voltage;

Input voltage is selected circuit, is couple to described the first power supply terminal and described second source terminal;

The first mains switch; And

The second source switch,

Wherein said input voltage selects circuit to comprise power-on reset circuit, input voltage detection circuit and control circuit,

The wherein supply to the supply of described the first power supply terminal and described second source voltage to described second source terminal in response to described the first supply voltage, described power-on reset circuit produces power-on reset signal,

Wherein said input voltage detection circuit produces the first voltage detecting output signal in response to described the first supply voltage to the supply of described the first power supply terminal, and produce second voltage in response to described second source voltage to the supply of described second source terminal and detect output signal

Wherein said control circuit detects output signal in response to described power-on reset signal, described the first voltage detecting output signal and described second voltage, controls described the first mains switch and described second source switch,

The timing that wherein at the level of described power-on reset signal, in response to the power-on reset operation of described power-on reset circuit, finishes and change, described input voltage detection circuit detects the supply of described the first supply voltage to the supply of described the first power supply terminal and described second source voltage to described second source terminal

The timing wherein changed at the level of described power-on reset signal, described input voltage detection circuit detects the supply of described the first supply voltage to described the first power supply terminal, and described second source voltage do not detected in the first situation of the supply of described second source terminal, after described power-on reset operation finishes, described control circuit controls respectively described the first mains switch and described second source switch into conducting state and off-state

Wherein by after described power-on reset operation finishes, described the first mains switch and described second source switch being controlled respectively as conducting state and off-state, described the first mains switch that is controlled as conducting state will be supplied to described first supply voltage of described the first power supply terminal to be supplied to load

The timing wherein changed at the level of described power-on reset signal, described input voltage detection circuit detects the supply of described second source voltage to described second source terminal, and described the first supply voltage do not detected in the second situation of the supply of described the first power supply terminal, after described power-on reset operation finishes, described control circuit controls respectively described the first mains switch and described second source switch into off-state and conducting state

Wherein by after described power-on reset operation finishes, described the first mains switch and described second source switch being controlled respectively as off-state and conducting state, the described second source switch that is controlled as conducting state will be supplied to the described second source voltage of described second source terminal to be supplied to described load

The timing wherein changed at the level of described power-on reset signal, described input voltage detection circuit detect described the first supply voltage to the supply of described the first power supply terminal and described second source voltage in the third situation of the supply of described second source terminal, after described power-on reset operation finishes, described control circuit controls respectively another in one in described the first mains switch and described second source switch and described the first mains switch and described second source switch into conducting state and off-state

Wherein in the third situation, according to the priority orders that sets in advance described control circuit, described another in described one and described the first mains switch and described second source switch in described the first mains switch and described second source switch controlled respectively as conducting state and off-state, and

Described one that is controlled as conducting state in wherein said the first mains switch and described second source switch will be supplied to described first supply voltage of described the first power supply terminal or described second source terminal or described second source voltage to be supplied to described load.

2. according to the semiconductor integrated circuit of claim 1, also comprise:

The first outside lead-out terminal and the second outside lead-out terminal, supply described the first supply voltage or described second source voltage to the first external loading that is taken as described load and the second external loading respectively; And

Output P channel MOS transistor, be coupled between the described first outside lead-out terminal and the described second outside lead-out terminal;

Wherein, when after described power-on reset operation finishes, when any one in described the first mains switch and described second source switch is controlled as conducting state, described output P channel MOS transistor is controlled as conducting state by described control circuit, and

Wherein said output P channel MOS transistor is controlled as conducting state and makes it possible to, by described output P channel MOS transistor and the described second outside lead-out terminal, described the first supply voltage or described second source voltage are supplied to described the second external loading.

3. according to the semiconductor integrated circuit of claim 2, the wherein said first outside lead-out terminal is configured to supply described the first supply voltage or described second source voltage to described first external loading of another semiconductor integrated circuit corresponding to being taken as active equipment, and

Wherein said output P channel MOS transistor and the described second outside lead-out terminal are configured to supply described the first supply voltage or described second source voltage to described the second external loading that is taken as battery.

4. according to the semiconductor integrated circuit of claim 3, wherein said input voltage selects circuit also to comprise input voltage selector switch and gate driver circuit,

Wherein said input voltage selector switch comprises the first input P channel MOS transistor and the second input P channel MOS transistor, the source electrode of described the first input P channel MOS transistor is couple to described the first power supply terminal, the source electrode of described the second input P channel MOS transistor is couple to described second source terminal

Wherein during the power-on reset period of described power-on reset circuit, described gate driver circuit both controls the described first input P channel MOS transistor of described input voltage selector switch and described the second input P channel MOS transistor into conducting state, and

Wherein, during the described power-on reset period, from the drain electrode of described the first input P channel MOS transistor or the drain electrode of described the second input P channel MOS transistor, produce the operating voltage that will be supplied to described power-on reset circuit.

5. according to the semiconductor integrated circuit of claim 4, wherein in described the first situation, described gate driver circuit controls respectively the described first input P channel MOS transistor of described input voltage selector switch and described the second input P channel MOS transistor into conducting state and off-state

Wherein, in described the second situation, described gate driver circuit controls respectively the described first input P channel MOS transistor of described input voltage selector switch and described the second input P channel MOS transistor into conducting state and off-state, and

Wherein in described the third situation, described gate driver circuit is according to the priority orders that sets in advance described control circuit, and another in one in the described first input P channel MOS transistor of described input voltage selector switch and described the second input P channel MOS transistor and described the first input P channel MOS transistor and described the second input P channel MOS transistor controlled respectively as conducting state and off-state.

6. according to the semiconductor integrated circuit of claim 5, wherein said input voltage select circuit also comprise voltage ratio/select circuit, described voltage ratio/select circuit to there is first input end, the second input terminal and lead-out terminal,

Wherein said voltage ratio/select described first input end of circuit to be coupled to the described drain electrode of the described first input P channel MOS transistor of described input voltage selector switch,

Wherein said voltage ratio/select described second input terminal of circuit to be coupled to the described drain electrode of the described second input P channel MOS transistor of described input voltage selector switch,

The described operating voltage that wherein is supplied to described power-on reset circuit be from described voltage ratio/select the described lead-out terminal of circuit to produce, and

Wherein said voltage ratio/select the voltage of more described first input end of circuit and the voltage of described the second input terminal, to select high voltage, thereby export described high voltage as be supplied to the operating voltage of described power-on reset circuit from described lead-out terminal.

7. according to the semiconductor integrated circuit of claim 3, wherein when described the first situation occurring, after after described power-on reset operation finishes, described the first mains switch and described second source switch are controlled as respectively conducting state and off-state, occur that described input voltage detection circuit detects the four kind situation of described second source voltage to described second source terminal supply

Wherein in response to the appearance of described the 4th kind of situation, the same with described the third situation, described control circuit is according to the priority orders that sets in advance described control circuit, described another in described one and described the first mains switch and described second source switch in described the first mains switch and described second source switch controlled respectively as conducting state and off-state

Wherein when described the second situation occurring, after after described power-on reset operation finishes, described the first mains switch and described second source switch are controlled as respectively off-state and conducting state, occur that described input voltage detection circuit detects the five kind situation of described the first supply voltage to described the first power supply terminal supply

Wherein in response to the appearance of described the 5th kind of situation, the same with described the third situation, described control circuit is according to the priority orders that sets in advance described control circuit, described another in described one and described the first mains switch and described second source switch in described the first mains switch and described second source switch controlled respectively as conducting state and off-state

Wherein when described the third situation occurring, after described another in described one and described the first mains switch and described second source switch after described power-on reset operation finishes in described the first mains switch and described second source switch is controlled as respectively conducting state and off-state, occur that described input voltage detection circuit detects the six kind situation of described second source voltage to the supply of described second source terminal

Wherein in response to the appearance of described the 6th kind of situation, the same with described the third situation, described control circuit is according to the priority orders that sets in advance described control circuit, and described another in described and described the first mains switch and described second source switch in described the first mains switch and described second source switch controlled respectively as conducting state and off-state.

8. according to the semiconductor integrated circuit of claim 3, wherein when described the first situation occurring, after after described power-on reset operation finishes, described the first mains switch and described second source switch are controlled as respectively conducting state and off-state, occur that described input voltage detection circuit detects the four kind situation of described second source voltage to described second source terminal supply

Wherein, in response to the appearance of described the 4th kind of situation, described semiconductor integrated circuit can be notified to described another semiconductor integrated circuit that is taken as described the first external loading the appearance of described the 4th kind of situation,

The first notice of described the 4th kind of situation wherein in response to indication, occurs, described control circuit, according to the first indication provided to described semiconductor integrated circuit from described another semiconductor integrated circuit, is controlled described the first mains switch and described second source switch,

Wherein according to described the first indication, described control circuit controls respectively described the first mains switch and described second source switch into conducting state and off-state, perhaps described the first mains switch and described second source switch are controlled respectively as off-state and conducting state

Wherein when described the second situation occurring, after after described power-on reset operation finishes, described the first mains switch and described second source switch are controlled as respectively off-state and conducting state, occur that described input voltage detection circuit detects the five kind situation of described the first supply voltage to the supply of described the first power supply terminal

Wherein, in response to the appearance of described the 5th kind of situation, described semiconductor integrated circuit can be notified to described another semiconductor integrated circuit that is taken as described the first external loading the appearance of described the 5th kind of situation,

The second notice of described the 5th kind of situation wherein in response to indication, occurs, described control circuit, according to the second indication provided to described semiconductor integrated circuit from described another semiconductor integrated circuit, is controlled described the first mains switch and described second source switch,

Wherein according to described the second indication, described control circuit controls respectively described the first mains switch and described second source switch into off-state and conducting state, perhaps described the first mains switch and described second source switch are controlled respectively as conducting state and off-state

Wherein, in response to the appearance of described the 6th kind of situation, described semiconductor integrated circuit can be notified to described another semiconductor integrated circuit that is taken as described the first external loading the appearance of described the 6th kind of situation,

The third notice of described the 6th kind of situation wherein appears in response to indication, described control circuit is according to the 3rd indication provided to described semiconductor integrated circuit from described another semiconductor integrated circuit, control described the first mains switch and described second source switch, and

Wherein according to described the 3rd indication, described control circuit controls respectively described the first mains switch and described second source switch into conducting state and off-state, or described the first mains switch and described second source switch are controlled respectively as off-state and conducting state.

9. according to the semiconductor integrated circuit of claim 3, also comprise buck DC-DC transducer and the linear regulator of coupled in parallel between described the first power supply terminal and described the first mains switch,

Wherein said linear regulator plays series controller, its adjacent after powering up to the supply of described the first power supply terminal based on described the first supply voltage fast operating, and

Wherein said buck DC-DC transducer plays switching regulaor, and it has the power efficiency higher than described linear regulator.

10. according to the semiconductor integrated circuit of claim 9, wherein said the first power supply terminal is configured to the supply voltage that can carry based on wireless power to described the first power supply terminal supply by the first Schottky diode, and can couple by the second Schottky diode the AC-DC conversion electric power voltage of interface to described the first power supply terminal supply AC power supplies, and

Wherein said second source terminal is configured to couple to second source terminal supply USB the USB supply voltage of interface.

11. the method for operation of a semiconductor integrated circuit, this semiconductor integrated circuit is equipped with the first power supply terminal, the second source terminal that can supply second source voltage that can supply the first supply voltage, the input voltage that is couple to described the first power supply terminal and described second source terminal to select circuit, the first mains switch and second source switch, and this method of operation comprises the following steps:

Make described input voltage select circuit to there is power-on reset circuit, input voltage detection circuit and control circuit;

To the supply of described the first power supply terminal and described second source voltage to the supply of described second source terminal, from described power-on reset circuit, produce power-on reset signal in response to described the first supply voltage;

Supply in response to from described the first supply voltage to described the first power supply terminal, produce the first voltage detecting output signal from described input voltage detection circuit, and the supply in response to described second source voltage to described second source terminal, produce second voltage from described input voltage detection circuit and detect output signal

Detect output signal in response to described power-on reset signal, described the first voltage detecting output signal and described second voltage, by described control circuit, control described the first mains switch and described second source switch;

The timing that finishes in response to the power-on reset operation of described power-on reset circuit at the level of described power-on reset signal and change, detect the supply of described the first supply voltage to the supply of described the first power supply terminal and described second source voltage to described second source terminal by described input voltage detection circuit;

The timing changed at the level of described power-on reset signal, described input voltage detection circuit detects the supply of described the first supply voltage to described the first power supply terminal, and described second source voltage do not detected in the first situation of the supply of described second source terminal, after described power-on reset operation finishes, by described control circuit, described the first mains switch and described second source switch being controlled respectively is conducting state and off-state;

After described power-on reset operation finishes, described the first mains switch and described second source switch are controlled respectively as conducting state and off-state, thereby made described the first mains switch that is controlled as conducting state will be supplied to described first supply voltage of described the first power supply terminal to be supplied to load;

The timing changed at the level of described power-on reset signal, described input voltage detection circuit detects the supply of described second source voltage to described second source terminal, and described the first supply voltage do not detected in the second situation of the supply of described the first power supply terminal, after described power-on reset operation finishes, by described control circuit, described the first mains switch and described second source switch being controlled respectively is off-state and conducting state;

After described power-on reset operation finishes, described the first mains switch and described second source switch are controlled respectively as off-state and conducting state, thereby made the described second source switch that is controlled as conducting state will be supplied to the described second source voltage of described second source terminal to be supplied to described load;

The timing changed at the level of described power-on reset signal, described input voltage detection circuit detect described the first supply voltage to the supply of described the first power supply terminal and described second source voltage in the third situation of the supply of described second source terminal, after described power-on reset operation finishes, described control circuit controls respectively another in one in described the first mains switch and described second source switch and described the first mains switch and described second source switch into conducting state and off-state;

In the third situation, according to the priority orders that sets in advance described control circuit, described another in described and described the first mains switch and described second source switch in described the first mains switch and described second source switch controlled respectively as conducting state and off-state; And

Described one that makes in described the first mains switch and described second source switch to be controlled as conducting state will be supplied to described first supply voltage of described the first power supply terminal or described second source terminal or described second source voltage to be supplied to described load.

12. according to the method for operation of claim 11, further comprising the steps of:

Make described semiconductor integrated circuit further have the first outside lead-out terminal and the second outside lead-out terminal, the described first outside lead-out terminal and the described second outside lead-out terminal are supplied described the first supply voltage or described second source voltage to the first external loading that is taken as described load and the second external loading respectively;

Make described semiconductor integrated circuit further have output P channel MOS transistor, it is coupled between the described first outside lead-out terminal and the described second outside lead-out terminal;

When after described power-on reset operation finishes, when any one in described the first mains switch and described second source switch is controlled as conducting state, by described control circuit, described output P channel MOS transistor being controlled is conducting state; And

Described output P channel MOS transistor is controlled as conducting state, thereby made it possible to, by described output P channel MOS transistor and the described second outside lead-out terminal, described the first supply voltage or described second source voltage are supplied to described the second external loading.

13. according to the method for operation of claim 12, further comprising the steps of:

Make the described first outside lead-out terminal supply described the first supply voltage or described second source voltage to described first external loading of another semiconductor integrated circuit corresponding to being taken as active equipment; And

Make described output P channel MOS transistor and the described second outside lead-out terminal supply described the first supply voltage or described second source voltage to described the second external loading that is taken as battery.

14. according to the method for operation of claim 13, further comprising the steps of:

Make described input voltage select circuit further to there is input voltage selector switch and gate driver circuit;

Make described input voltage selector switch there is the first input P channel MOS transistor and the second input P channel MOS transistor, the source electrode of described the first input P channel MOS transistor is couple to described the first power supply terminal, and the source electrode of described the second input P channel MOS transistor is couple to described second source terminal;

During the power-on reset period of described power-on reset circuit, by described gate driver circuit, the described first input P channel MOS transistor of described input voltage selector switch and described the second input P channel MOS transistor both being controlled is conducting state; And

During the described power-on reset period, from the drain electrode of described the first input P channel MOS transistor or the drain electrode of described the second input P channel MOS transistor, produce the operating voltage that will be supplied to described power-on reset circuit.

15. according to the method for operation of claim 14, further comprising the steps of:

In described the first situation, by described gate driver circuit, the described first input P channel MOS transistor of described input voltage selector switch and described the second input P channel MOS transistor being controlled respectively is conducting state and off-state;

In described the second situation, by described gate driver circuit, the described first input P channel MOS transistor of described input voltage selector switch and described the second input P channel MOS transistor being controlled respectively is conducting state and off-state; And

In described the third situation, by described gate driver circuit, according to the priority orders that sets in advance described control circuit, another in one in the described first input P channel MOS transistor of described input voltage selector switch and described the second input P channel MOS transistor and described the first input P channel MOS transistor and described the second input P channel MOS transistor controlled respectively as conducting state and off-state.

16. according to the method for operation of claim 15, further comprising the steps of:

Make described input voltage select circuit further have voltage ratio/select circuit, described voltage ratio/select circuit to there is first input end, the second input terminal and lead-out terminal;

By described voltage ratio/select described first input end of circuit to be couple to the described drain electrode of the described first input P channel MOS transistor of described input voltage selector switch;

By described voltage ratio/select described second input terminal of circuit to be couple to the described drain electrode of the described second input P channel MOS transistor of described input voltage selector switch;

From described voltage ratio/select the described lead-out terminal of circuit to produce the operating voltage that is supplied to described power-on reset circuit; And

By described voltage ratio/select the voltage of more described first input end of circuit and the voltage of described the second input terminal, to select high voltage, thereby export described high voltage as be supplied to the operating voltage of described power-on reset circuit from described lead-out terminal.

17. according to the method for operation of claim 13, further comprising the steps of:

When described the first situation occurring, after described the first mains switch and described second source switch are controlled as respectively conducting state and off-state after described power-on reset operation finishes, produce described input voltage detection circuit and the four kind situation of described second source voltage to the supply of described second source terminal detected;

Appearance in response to described the 4th kind of situation, the same with described the third situation, make described control circuit according to the priority orders that sets in advance described control circuit, by described the first mains switch and described second source switch described one and state the first mains switch and described second source switch in described another control respectively as conducting state and off-state;

When described the second situation occurring, after described the first mains switch and described second source switch are controlled as respectively off-state and conducting state after described power-on reset operation finishes, produce described input voltage detection circuit and the five kind situation of described the first supply voltage to the supply of described the first power supply terminal detected;

Appearance in response to described the 5th kind of situation, the same with described the third situation, make described control circuit according to the priority orders that sets in advance described control circuit, described another in described and described the first mains switch and described second source switch in described the first mains switch and described second source switch controlled respectively as conducting state and off-state;

When described the third situation occurring, described another in described one and described the first mains switch and described second source switch after described power-on reset operation finishes in described the first mains switch and described second source switch produces described input voltage detection circuit and the six kind situation of described second source voltage to the supply of described second source terminal detected after being controlled as respectively conducting state and off-state; And

Appearance in response to described the 6th kind of situation, the same with described the third situation, make described control circuit according to the priority orders that sets in advance described control circuit, described another in described and described the first mains switch and described second source switch in described the first mains switch and described second source switch controlled respectively as conducting state and off-state.

18. according to the method for operation of claim 13, further comprising the steps of:

In response to the appearance of described the 4th kind of situation, make described semiconductor integrated circuit can notify to described another semiconductor integrated circuit that is taken as described the first external loading the appearance of described the 4th kind of situation;

The first notice that occurs described the 4th kind of situation in response to indication, according to the first indication provided to described semiconductor integrated circuit from described another semiconductor integrated circuit, control described the first mains switch and described second source switch by described control circuit;

According to described the first indication, by described control circuit, described the first mains switch and described second source switch being controlled respectively is conducting state and off-state, or by described control circuit, described the first mains switch and described second source switch to be controlled respectively be off-state and conducting state;

In response to the appearance of described the 5th kind of situation, make described semiconductor integrated circuit can notify to described another semiconductor integrated circuit that is taken as described the first external loading the appearance of described the 5th kind of situation;

The second notice that occurs described the 5th kind of situation in response to indication, according to the second indication provided to described semiconductor integrated circuit from described another semiconductor integrated circuit, control described the first mains switch and described second source switch by described control circuit;

According to described the second indication, by described control circuit, described the first mains switch and described second source switch being controlled respectively is off-state and conducting state, or by described control circuit, described the first mains switch and described second source switch to be controlled respectively be conducting state and off-state;

When described the third situation occurring, described another in described one and described the first mains switch and described second source switch after described power-on reset operation finishes in described the first mains switch and described second source switch produces described input voltage detection circuit and the six kind situation of described second source voltage to the supply of described second source terminal detected after being controlled as respectively conducting state and off-state;

In response to the appearance of described the 6th kind of situation, make described semiconductor integrated circuit can notify to described another semiconductor integrated circuit that is taken as described the first external loading the appearance of described the 6th kind of situation;

The third notice that occurs described the 6th kind of situation in response to indication, according to the 3rd indication provided to described semiconductor integrated circuit from described another semiconductor integrated circuit, control described the first mains switch and described second source switch by described control circuit; And

According to described the 3rd indication, by described control circuit, described the first mains switch and described second source switch being controlled respectively is conducting state and off-state, or by described control circuit, described the first mains switch and described second source switch to be controlled respectively be off-state and conducting state.

19. according to the method for operation of claim 13, further comprising the steps of:

Make described semiconductor integrated circuit further there is buck DC-DC transducer and the linear regulator of coupled in parallel between described the first power supply terminal and described the first mains switch;

Make described linear regulator play series controller, its adjacent after powering up to the supply of described the first power supply terminal based on described the first supply voltage fast operating; And

Make described buck DC-DC transducer play switching regulaor, described switching regulaor has the power efficiency higher than described linear regulator.

20. according to the method for operation of claim 19, further comprising the steps of:

Described the first power supply terminal is configured to the supply voltage that can carry based on wireless power to described the first power supply terminal supply by the first Schottky diode, and can couples by the second Schottky diode the AC-DC conversion electric power voltage of interface to described the first power supply terminal supply AC power supplies; And

By described second source terminal arrangement, be to couple to second source terminal supply USB the USB supply voltage of interface.