JP5998025B2 - Semiconductor integrated circuit and operation method thereof - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and a method for operating the same, and is particularly effective in reducing the possibility that a DC-DC converter stops when a power supply power is small and a load current such as a charging current of a secondary battery (battery) is large. Technology.

  Conventionally, an IC card is equipped with a semiconductor integrated circuit and an antenna coil, and this IC card is powered by receiving and rectifying RF signals from a reading / writing device called a card reader / card writer using an antenna coil. This is performed by rectification by a circuit. As described above, IC cards having no power source on the card side are widely used in automatic ticket gate systems, electronic money, logistics management, and the like. Thus, while this IC card is RF-fed, unique identification information (ID information) is stored in the built-in nonvolatile memory, so it is called an RFID card. An IC card used in the fields of an automatic ticket gate system, electronic money, etc. uses NFC communication using an RF frequency of 13.56 MHz. NFC is an abbreviation for Near Field Communication.

  On the other hand, a wireless power feeding system called “just-on-placement charging” that allows charging of a mobile device by simply placing the mobile device on a dedicated charging table without connecting a power cable to the mobile device such as a smartphone has become widespread. This wireless power supply system corresponds to the fact that the battery of a mobile phone called a smartphone is consumed greatly. In other words, smartphones are multifunctional mobile phones that have high compatibility with the Internet and are based on the functions of a personal computer, or multi-function mobile phones that have a PDA function added to phone / mail. Sometimes abbreviated. The wireless power supply system is based on an international standard called Qi (Qi) established by the industry group Wireless Power Consortium (WPC). According to the method, power can be supplied from the transmitting device to the receiving device. The advantage of this wireless power supply system is that it is not necessary to connect and disconnect the power connector for charging, and in particular, the work of opening and closing the connector cover of the power connector of the portable device can be omitted.

  On the other hand, FIG. 2 of Patent Document 1 below and the related disclosure disclose that NFC communication is performed between a port device and a mobile device and that a secondary battery (battery) of the mobile device is charged from the port device. It describes performing contact power transfer. The mobile device has an NFC communication induction coil and a charging induction coil. The NFC communication induction coil is connected to the NFC chip, and the charging induction coil is connected to the charging power receiving unit, the charge controller, and the secondary battery. The The port device has an NFC communication induction coil and a charging induction coil. The NFC communication induction coil is connected to the NFC chip, and the charging induction coil is connected to the charging power supply unit.

  Further, FIG. 3 of the following Patent Document 1 and related disclosure include an operation timing of NFC communication between a port device and a mobile device, and a non-charge for charging a secondary battery (battery) of the mobile device from the port device. It is described that the operation timing of contact power transmission is repeated by time division. Since non-contact power transmission for charging is deactivated at the operation timing of NFC communication by time division, it is possible to reduce degradation of signal quality such as noise from non-contact power transmission to NFC communication It is guessed.

  Further, FIG. 7 of the following Patent Document 1 and related disclosure include other non-peripherals for performing NFC communication between a port device and a mobile device and charging a secondary battery (battery) of the mobile device from the port device. A contact power transmission scheme is described. The mobile device has one induction coil that is used for both NFC communication and charging, and this one induction coil is connected to the circuit selector, and the circuit selector is connected to the NFC chip and the charging power receiver. Is done. The circuit selector selects any one of the NFC chip and the charging power receiver, and the selected one is connected to one induction coil via the circuit selector. The port device has one induction coil that is used for both NFC communication and charging. The one induction coil is connected to a circuit selector, and the circuit selector includes an NFC chip, a charging power supply unit, Connected to. The circuit selector selects any one of the NFC chip and the charging power supply unit, and the selected one is connected to one induction coil via the circuit selector.

  Furthermore, in the following Patent Document 2, in an electronic device that charges a battery by being selectively connected to two or more types of power supplies, the connection with the power supply that is receiving power supply is immediately released. And using a controller to start charging the battery. That is, in the control by the controller, while the current is supplied from the AC power source to the AC connection unit, the battery is charged by the AC power source, and the current is not supplied from the AC power source to the AC connection unit. While the current is being supplied to the battery, the battery is charged by the power supply of the external device. In particular, the controller is necessary to charge the battery via the external device by performing initial communication with the external device when the external device connection unit is connected to the external device while the battery is being charged by the AC power source. To set the correct charge. Specifically, the external device connection unit is a USB connection unit, and an interface of another standard such as IEEE1394 can be used. When the electronic device is connected to both the AC power source and the external device, the current from the AC power source is larger than the current from the external device, so the controller charges the battery with the AC power source.

  Further, Patent Document 3 discloses control of a DC-DC converter that supplies operating power of a system device and charging power of a battery in order to save power of an electronic device and simplify control of a power supply circuit and the like. Describes that the control unit controls the sum of the operating power of the system device and the charging power of the battery to be substantially constant. The system equipment includes a CPU, a hard disk drive, a CD-ROM drive, a display unit, and the like.

JP 2009-253649 A JP 2011-155830 A JP 2000-228833 A

  Prior to the present invention, the present inventor engaged in the development of a wireless, non-contact charging method for a secondary battery (battery) mounted on a mobile communication device such as a smartphone.

  In this development, the present inventor first examined a past portable communication device and a past charging method.

  Previous mobile phones of smartphones are equipped with an antenna coil and NFC chip for NFC communication in order to realize application functions such as an automatic ticket gate system using an IC card using NFC communication and electronic money. It was. Therefore, an antenna coil and an NFC chip for NFC communication are also mounted on a mobile phone of a smart phone, following the previous mobile phone system. However, the power of the previous NFC communication is such that the antenna coil and the NFC chip are operated, and there is no room for charging the secondary battery (battery) mounted on the mobile phone.

  On the other hand, the Qi standard established by the industry group WPC uses a frequency of 100 KHz to 200 KHz which is considerably lower than the RF frequency of 13.56 MHz of NFC communication. Therefore, in order to install a charging method for a secondary battery (battery) compliant with a wireless power supply system based on the Qi standard on a mobile phone such as a smartphone, an antenna that receives a low frequency of the Qi standard is used for the previous NFC communication. It must be mounted on the mobile phone separately from the antenna coil. As a result, a problem that the mobile phone such as a smartphone has to be equipped with two types of antennas and it is difficult to secure a mounting space has been clarified by an examination by the present inventor prior to the present invention. In order to solve this problem, in the development by the inventor prior to the present invention, as described in FIG. 7 of Patent Document 1 and the related disclosure, the NFC communication and the charging are combined. A method of using one induction coil in a mobile device was adopted.

  Furthermore, in the development by the inventor prior to the present invention, the charging of the secondary battery (battery) of a portable electronic device such as a smartphone is an AC-DC power supply generated by rectifying and smoothing the AC power supply voltage from the AC power supply. It has been required to be possible by a plurality of power supply voltages such as a voltage, a USB power supply voltage from a USB connection, and a power supply voltage by wireless power feeding of the above-described wireless power feeding system. Furthermore, it is necessary to generate a substantially constant DC voltage from various power supply voltage levels of a plurality of power supply voltages. The substantially constant DC voltage is used to generate an operating voltage for an internal electronic circuit of a portable electronic device such as a smartphone. Used to generate secondary battery (battery) charge. Therefore, it was decided in the development by the present inventor prior to the present invention that a high-efficiency DC-DC converter is employed to generate a substantially constant DC voltage. However, when the power supplied from the transmitting system to the receiving system by wireless power feeding of the wireless power feeding system is smaller than the power consumed on the receiving system side, for example, a secondary battery (battery) set in advance on the receiving system side When the charging current is larger than the power supplied by the wireless power feeding, the receiving system side tries to perform the battery charging operation with the set charging current amount. However, since the power supplied by the wireless power feeding is insufficient, the power supply voltage of the DC-DC converter is lowered and the DC-DC converter is stopped. Therefore, the problem that it becomes impossible to charge the battery when the DC-DC converter is stopped has been clarified by the examination by the inventor prior to the present invention.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  The outline of the typical embodiment disclosed in the present application will be briefly described as follows.

  That is, the semiconductor integrated circuit (212) according to the representative embodiment includes an input terminal (T1), a DC-DC converter (2121), an output terminal (T3, T4), a power switch transistor (Path_SW), a current A limiting circuit (21241) and an input voltage detection circuit (21242) are provided.

A DC input voltage (V _IN ) generated by rectification and smoothing of the RF reception signal can be supplied to the input terminal (T1).

The DC-DC converter (2121) generates a DC output voltage (V _DDOUT2 ) having a desired voltage level from the converter output terminal (T6) from the DC input voltage (V _IN ) supplied to the input terminal (T1). .

The output terminals (T3, T4) can use the DC output voltage (V _DDOUT2 ) to charge the external battery (26) or to supply power to the external power receiving system (3).

  The power switch transistor (Path_SW) enables electrical continuity between the output terminals (T3, T4) and the converter output terminal (T6) of the DC-DC converter (2121).

  The current limiting circuit (21241) performs current limitation of the load current of the power switch transistor (Path_SW) flowing from the converter output terminal (T6) to the output terminals (T3, T4).

Input voltage detecting circuit (21242) generates an input voltage detection signal _{(V - DIV)} by the level detection of the DC input voltage supplied to the input terminal (T1) _{(V IN),} the input voltage detection signal _{(V - DIV} ) Is supplied to the current limiting circuit (21241).

The current limit circuit (21241) controls the value of the maximum current (I_limit) due to the current limit of the power switch transistor (Path_SW) in response to the input voltage detection signal (V _{IN_DIV} ).

When the DC input voltage (V _IN ) supplied to the input terminal (T1) is at a low level, the current limit circuit (21241) reduces the maximum current (I_limit) due to the current limit of the power switch transistor (Path_SW) to a small current. (See FIG. 5).

  The following is a brief description of an effect obtained by the typical embodiment of the embodiments disclosed in the present application.

  That is, according to this semiconductor integrated circuit (212), the possibility that the DC-DC converter stops when the power supply power is small and the load current is large can be reduced.

FIG. 1 is a diagram showing a configuration of a wireless power transmission system for a multi-function mobile phone on which a semiconductor integrated circuit 212 that executes a battery charging control operation according to the first embodiment is mounted. FIG. 2 is a diagram showing a configuration of semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG. FIG. 3 is a diagram showing functions of external terminals of semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG. FIG. 4 is a diagram showing a basic configuration for feeding power to the power receiving side system 3 of the semiconductor integrated circuit 212 and charging the secondary battery 26 for battery charging control according to the first embodiment shown in FIG. is there. FIG. 5 is a diagram showing a detailed configuration for feeding power to the power receiving side system 3 of the semiconductor integrated circuit 212 and charging the secondary battery 26 for battery charging control according to the first embodiment shown in FIG. . FIG. 6 is a diagram showing the characteristics of the current limiting operation of the current limiting circuit 21241 according to the first embodiment shown in FIG. 4 and FIG. FIG. 7 is a diagram showing the characteristic of the total current I_limit of the switch SW2 realized by the characteristic of the current limiting operation of the current limiting circuit 21241 according to the first embodiment shown in FIGS. FIG. 8 shows the operation of the semiconductor integrated circuit 212 in the case where the battery charge control semiconductor integrated circuit 212 does not include the current limiting circuit 21241 that executes the current limiting operation in response to the level of the DC power supply voltage _{VIN at} the supply terminal T1. FIG. FIG. 9 shows a battery integrated circuit for controlling the current limiting circuit 21241 that performs a current limiting operation in response to the level of the DC power supply voltage _{VIN at} the supply terminal T1 according to the first embodiment shown in FIGS. FIG. 6 is a diagram illustrating an operation of the semiconductor integrated circuit 212 when the reference numeral 212 is provided. FIG. 10 shows a maximum battery in which the current limiting current of the P-channel MOS transistor MP1 of the switch SW2 is adjusted by the resistor R _ICHG in a state where the intermediate level or high level DC power supply voltage _VIN is supplied to the supply terminal T1 by wireless power feeding. It is a figure which shows operation | movement of the semiconductor integrated circuit 212 at the time of setting higher than an electric current. FIG. 11 shows the current limit of the P-channel MOS transistor MP1 of the switch SW2 with the maximum battery current adjusted by the resistor R _ICHG in a state where the intermediate or high level DC power supply voltage _VIN is supplied to the supply terminal T1 by wireless power feeding. It is a figure which shows operation | movement of the semiconductor integrated circuit 212 at the time of setting higher than an electric current.

1. First, an outline of a typical embodiment disclosed in the present application will be described. The reference numerals of the drawings referred to in parentheses in the outline description of the representative embodiment merely exemplify what is included in the concept of the component to which the reference numeral is attached.

  [1] A semiconductor integrated circuit (212) according to a typical embodiment includes an input terminal (T1), a DC-DC converter (2121), output terminals (T3, T4), a power switch transistor (Path_SW), A current limiting circuit (21241) and an input voltage detecting circuit (21242).

A DC input voltage (V _IN ) generated by rectification and smoothing of the RF reception signal can be supplied to the input terminal (T1).

The DC-DC converter (2121) converts a DC output voltage (V _DDOUT2 ) having a desired voltage level from the DC input voltage (V _IN ) supplied to the input terminal (T1) to a converter output terminal (T6). It can be generated from.

The output terminals (T3, T4) can charge the external battery (26) or supply power to the external power receiving system (3) using the DC output voltage (V _DDOUT2 ).

  The power switch transistor (Path_SW) enables electrical continuity between the output terminals (T3, T4) and the converter output terminal (T6) of the DC-DC converter (2121).

  The current limiting circuit (21241) performs current limitation on the load current of the power switch transistor (Path_SW) flowing from the converter output terminal (T6) to the output terminals (T3, T4).

The input voltage detection circuit (21242) generates an input voltage detection signal (V _{IN_DIV} ) by detecting the level of the DC input voltage (V _IN ) supplied to the input terminal (T1), and the input voltage detection signal (V _{IN_DIV} ) is supplied to the current limiting circuit (21241).

The current limit circuit (21241) is responsive to the input voltage detection signal (V _{IN_DIV} ) supplied from the input voltage detection circuit (21242) to provide a maximum current (I_limit) due to the current limitation of the power switch transistor (Path_SW). ) To control the value.

When the DC input voltage (V _IN ) supplied to the input terminal (T1) is at a high level, the current limiting circuit (21241) responds to the input voltage detection signal (V _{IN_DIV} ) in response to the power supply. The value of the maximum current (I_limit) due to the current limitation of the switch transistor (Path_SW) is controlled to a large current.

When the DC input voltage (V _IN ) supplied to the input terminal (T1) is at a low level lower than the high level, the current limiting circuit (21241) is configured to detect the input voltage detection signal (V _{IN_DIV} ). In response, the value of the maximum current (I_limit) due to the current limitation of the power switch transistor (Path_SW) is controlled to be smaller than the large current (see FIG. 5).

  According to the embodiment, it is possible to reduce the possibility that the DC-DC converter stops when the supplied power is small and the load current is large.

  In a preferred embodiment, the power switch transistor (Path_SW) is a P-channel MOS transistor (MP1) whose source and drain are connected to the converter output terminal (T6) and the output terminal (T3, T4), respectively. (See FIG. 5).

  Another preferred embodiment is characterized in that the gate of the P-channel MOS transistor (MP1) of the power switch transistor (Path_SW) is controlled by the current limiting circuit (21241) (see FIG. 5).

  In still another preferred embodiment, the current limiting circuit (21241) includes a control P-channel MOS transistor (MP2), a detection resistor (R_limit), and a differential amplifier (212411).

  The source and drain of the control P-channel MOS transistor (MP2) are connected to the converter output terminal (T6) and one end of the detection resistor (R_limit), respectively, and the other end of the detection resistor (R_limit) is connected to the ground potential. Connected.

The first inverting input terminal (−), the second inverting input terminal (−), and the non-inverting input terminal (+) of the differential amplifier (212411) have a reference voltage (V _{REF — U} ) and the input voltage detection signal (V _{IN_DIV} ) and the detection voltage (V_limit) at the one end of the detection resistor (R_limit) are supplied.

  The gate of the P-channel MOS transistor (MP1) and the gate of the control P-channel MOS transistor (MP2) are controlled by the output signal of the differential amplifier (212411).

  The differential amplifier selects a low voltage level among the reference voltage of the first inverting input terminal and the input voltage detection signal of the second inverting input terminal, and the selected low voltage level The output signal of the differential amplifier controls the drain current of the control P-channel MOS transistor (MP2) so that the detected voltage at the non-inverting input terminal matches (see FIG. 5).

In a more preferred embodiment, the reference voltage (V _{REF_U} ) of the first inverting input terminal (−) is lower than the input voltage detection signal (V _{IN_DIV} ) of the second inverting input terminal (−). In this case, the drain current of the control P-channel MOS transistor (MP2) is controlled so that the detection voltage (V_limit) matches the reference voltage (V _{REF_U} ).

When the input voltage detection signal (V _{IN_DIV} ) of the second inverting input terminal (−) is lower than the reference voltage (V _{REF_U} ) of the first inverting input terminal (−), the input voltage detection signal The drain current of the control P-channel MOS transistor (MP2) is controlled so that the detection voltage (V_limit) matches the signal (V _{IN_DIV} ) (see FIG. 5).

  In another more preferred embodiment, the current limiting circuit (21241) further includes an offset voltage circuit (212412) that generates a first offset voltage (Voffset) and a second offset voltage (Voffset).

A first total voltage of the first offset voltage (Voffset) and the detection voltage (V_limit) is supplied to the non-inverting input terminal (+) of the differential amplifier (212411), and the second offset voltage (Voffset) The second total voltage of the reference voltage (V _{REF — U} ) is supplied to the first inverting input terminal (−) of the differential amplifier (212411) (see FIG. 5).

  In still another more preferred embodiment, the current limiting circuit (21241) further includes a voltage control circuit (212413) having a voltage comparison amplifier (AMP) and a comparison control transistor (MN4).

  The first input terminal and the second input terminal of the voltage comparison amplifier (AMP) are connected to the drain of the P channel MOS transistor (MP1) of the power switch transistor (Path_SW) and the control P channel MOS transistor (MP2). Each is connected to the drain.

  The output terminal of the voltage comparison amplifier (AMP) is connected to the control input terminal of the comparison control transistor (MN4), and the output current path of the comparison control transistor (MN4) is the drain of the control P channel MOS transistor (MP2). And the one end of the detection resistor (R_limit) (see FIG. 5).

  In another more preferred embodiment, the input voltage detection circuit (21242) includes a first voltage dividing resistor (R1) and a second voltage dividing resistor (R2).

One end of the first voltage dividing resistor (R1) is supplied with the DC input voltage (V _IN ) supplied to the input terminal (T1), and the other end of the first voltage dividing resistor (R1) is the first voltage dividing resistor (R1). The other end of the second voltage dividing resistor (R2) is connected to the ground potential.

From the connection node between the other end of the first voltage dividing resistor (R1) and the one end of the second voltage _dividing resistor (R2) of the input voltage detecting circuit (21242), the input voltage detection signal (V _{IN_DIV} ). Is generated (see FIG. 5).

The semiconductor integrated circuit (212) according to still another more preferred embodiment further includes a low-pass filter (21243) including a resistance element (R _LPF ) and a capacitance element (C _LPF ).

  The input voltage detection signal generated from the input voltage detection circuit (21242) is supplied to the input terminal of the low-pass filter (21243), and the input voltage detection signal transmitted to the output terminal of the low-pass filter (21243) is The second inverting input terminal (−) of the current limiting circuit (21241) is supplied (see FIG. 5).

  In a specific embodiment, an RF signal by NFC communication and an RF signal by wireless power feeding can be supplied to the input terminal (T1) in a time division manner (FIG. 1, (See FIG. 2).

  In another specific embodiment, the semiconductor integrated circuit (212) includes the DC-DC converter (2121) connected between the input terminal (T1) and the output terminal (T3, T4). It further includes a linear regulator (2122) connected in parallel.

The linear regulator (2122) operates immediately in response to the supply of the DC input voltage (V _IN ) at the input terminal (T1).

  The DC-DC converter (2121) operates as a switching regulator having higher power efficiency than the linear regulator (2122) (see FIG. 2).

In a more specific embodiment, the input terminal (T1) is connected to an AC power source via the first Schottky diode (D1) and the DC input voltage (V _IN ) and the second Schottky diode (D2). The input terminal (T1) is configured to supply the AC-DC conversion voltage of the interface (24) (see FIG. 2).

  In the most specific embodiment, the semiconductor integrated circuit (212) further includes another input terminal (T2) and a switch (SW3).

  The other input terminal (T2) is configured so that the USB power supply voltage of the USB connection interface (23) can be supplied to the other input terminal (T2).

  One end and the other end of the switch (SW3) are connected to the other input terminal (T2) and the output terminal (T3, T4), respectively (see FIG. 2).

  [2] A typical embodiment of another viewpoint is that an input terminal (T1), a DC-DC converter (2121), an output terminal (T3, T4), a power switch transistor (Path_SW), a current limiter This is an operation method of the semiconductor integrated circuit (212) including the circuit (21241) and the input voltage detection circuit (21242).

A DC input voltage (V _IN ) generated by rectification and smoothing of the RF reception signal can be supplied to the input terminal (T1).

The DC-DC converter (2121) converts a DC output voltage (V _DDOUT2 ) having a desired voltage level from the DC input voltage (V _IN ) supplied to the input terminal (T1) to a converter output terminal (T6). It can be generated from.

The output terminals (T3, T4) can charge the external battery (26) or supply power to the external power receiving system (3) using the DC output voltage (V _DDOUT2 ).

  The power switch transistor (Path_SW) enables electrical continuity between the output terminals (T3, T4) and the converter output terminal (T6) of the DC-DC converter (2121).

  The current limiting circuit (21241) performs current limitation on the load current of the power switch transistor (Path_SW) flowing from the converter output terminal (T6) to the output terminals (T3, T4).

The input voltage detection circuit (21242) generates an input voltage detection signal (V _{IN_DIV} ) by detecting the level of the DC input voltage (V _IN ) supplied to the input terminal (T1), and the input voltage detection signal (V _{IN_DIV} ) is supplied to the current limiting circuit (21241).

The current limit circuit (21241) is responsive to the input voltage detection signal (V _{IN_DIV} ) supplied from the input voltage detection circuit (21242) to provide a maximum current (I_limit) due to the current limitation of the power switch transistor (Path_SW). ) To control the value.

When the DC input voltage (V _IN ) supplied to the input terminal (T1) is at a high level, the current limiting circuit (21241) responds to the input voltage detection signal (V _{IN_DIV} ) in response to the power supply. The value of the maximum current (I_limit) due to the current limitation of the switch transistor (Path_SW) is controlled to a large current.

When the DC input voltage (V _IN ) supplied to the input terminal (T1) is at a low level lower than the high level, the current limiting circuit (21241) is configured to detect the input voltage detection signal (V _{IN_DIV} ). In response, the value of the maximum current (I_limit) due to the current limitation of the power switch transistor (Path_SW) is controlled to be smaller than the large current (see FIG. 5).

  According to the embodiment, it is possible to reduce the possibility that the DC-DC converter stops when the supplied power is small and the load current is large.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<Configuration of wireless power transmission system for multi-function mobile phone>
FIG. 1 is a diagram showing a configuration of a wireless power transmission system for a multi-function mobile phone on which a semiconductor integrated circuit 212 that executes a battery charging control operation according to the first embodiment is mounted.

  The wireless power transmission system for the multi-function mobile phone shown in FIG. 1 includes a power transmission circuit 1, a power reception circuit 2, and a power reception side system 3. In particular, in the wireless power transmission system for the multi-function mobile phone shown in FIG. 1, the RF signal from the power transmission side antenna coil 13 is received by the reception side antenna coil 25 to charge the secondary battery 26 and the power reception side system. 3 is executed.

<< Transmission circuit on the transmission side >>
As shown in FIG. 1, AC power is supplied to the power transmission circuit 1 on the transmission side of the wireless power transmission system via the AC adapter 10. The power transmission circuit 1 includes a microcontroller unit (MCU) 11 and a power transmission control circuit 12, and the microcontroller unit (MCU) 11 has an authentication processing function 111 and an encryption processing function 112. The power transmission control circuit 12 is rectified. A circuit 121 and an RF driver 122 are included, and the RF driver 122 is connected to the power transmission side antenna coil 13.

  A DC power supply voltage generated by rectifying and smoothing the AC power supplied via the AC adapter 10 by the rectifier circuit 121 is supplied to the microcontroller unit (MCU) 11 and the RF driver 122 of the power transmission circuit 1. Is done. The authentication processing function 111 and the encryption processing function 112 of the microcontroller unit (MCU) 11 of the power transmission circuit 1 determine whether or not the user of the multi-function mobile phone that is the power receiving circuit 2 has a right to use. Mutual authentication processing and encryption processing for preventing tampering of communication data are executed. That is, the microcontroller unit (MCU) 11 of the power transmission circuit 1 generates an encryption key related to a communication protocol between the authentication processing function 221 and the encryption processing function 222 of the microcontroller unit (MCU) 22 included in the power receiving circuit 2. Key management operations related to holding, updating, and deletion are executed.

  As a result, when it is determined by the microcontroller unit (MCU) 11 of the power transmission circuit 1 that the user of the multi-function mobile phone that is the power receiving circuit 2 is a valid user, the RF driver 122 performs an RF (not shown). An RF drive signal supplied to the power transmission side antenna coil 13 is generated in response to the RF oscillation output signal generated from the oscillator. Further, communication data of authentication processing and encryption processing from the microcontroller unit (MCU) 11 of the power transmission circuit 1 is supplied to the power reception circuit 2 via the RF driver 122, the power transmission side antenna coil 13, and the power reception side antenna coil 25. The

<< Receiving circuit on the receiving side >>
As shown in FIG. 1, the power reception circuit 2 on the reception side of the wireless power transmission system includes a power reception control circuit 21 and a microcontroller unit (MCU) 22, and the microcontroller unit (MCU) 22 includes an authentication processing function 221. The power reception control circuit 21 includes an encryption processing function 222, and includes a rectification circuit 211 and a semiconductor integrated circuit 212 for battery charge control.

  In the wireless power transmission system shown in FIG. 1, communication according to the communication protocol described above is first performed between the microcontroller unit (MCU) 11 of the power transmission circuit 1 and the microcontroller unit (MCU) 22 of the power reception circuit 2. This is executed via the power transmission side antenna coil 13 and the power reception side antenna coil 25. For this communication, the power receiving circuit 2 enables serial communication and power supply between the power receiving control circuit 21 and the microcontroller unit (MCU) 22. When it is determined by the microcontroller unit (MCU) 11 of the power transmission circuit 1 that the user of the multi-function mobile phone that is the power reception circuit 2 is a valid user, the RF drive signal generated from the RF driver 122 Is supplied to the power reception circuit 2 via the power transmission side antenna coil 13 and the power reception side antenna coil 25.

  A DC power supply voltage generated by rectifying and smoothing the RF drive signal supplied via the power transmission side antenna coil 13 and the power reception side antenna coil 25 by the rectification circuit 211 is converted into a semiconductor integrated circuit 212 and a microcontroller unit ( MCU) 22. The DC power supply voltage supplied from the rectifier circuit 211 to the semiconductor integrated circuit 212 is used for charging the secondary battery 26 and also for supplying power to the power receiving system 3.

  When the receiving side of the wireless power transmission system is a multi-function mobile phone, the power receiving side system 3 includes an application processor, baseband processor, liquid crystal display driver IC, RF signal processing semiconductor integrated circuit (RFIC), main memory, flash memory, etc. Non-volatile memory and the like.

  Further, when the receiving side of the wireless power transmission system is a portable personal computer such as a tablet PC, the power receiving side system 3 further includes a central processing unit (CPU) and a flash memory storage having a large-scale storage capacity replacing a hard disk. It is a waste.

  In addition to the DC power supply voltage generated by the rectifier circuit 211, the semiconductor integrated circuit 212 for battery charge control and system power supply includes the USB power supply voltage from the USB connection interface 23 and the AC power supply from the AC power supply interface 24. An AC-DC conversion power supply voltage generated by rectification and smoothing of the power supply voltage can be supplied. Accordingly, the semiconductor integrated circuit 212 for battery charging control and system power supply includes a plurality of DC power supply voltages of the rectifier circuit 211, USB power supply voltage of the USB connection interface 23, and AC-DC conversion power supply voltage of the AC power supply connection interface 24. It has a function of automatically selecting a power supply voltage for battery charge control and system power supply from the power supply voltage. USB is an abbreviation for Universal Serial Bus.

  Further, in the wireless power transmission system shown in FIG. 1, the power transmission circuit 1 on the power transmission side and the power reception circuit 2 on the reception side are configured to charge the secondary battery 26 and supply power to the power reception system 3. Power supply) and NFC communication between the power transmission circuit 1 on the power transmission side as the port device and the power reception circuit 2 on the reception side as the mobile device. Further, by executing NFC communication and wireless power feeding in a time-sharing manner, charging of the secondary battery 26 of the power receiving circuit 2 on the receiving side as the mobile device is performed, while the power transmitting circuit 1 on the power transmitting side as the port device and the mobile NFC communication with the receiving-side power receiving circuit 2 as a device can be executed. By this NFC communication, the power receiving circuit 2 on the reception side as the mobile device can use the wired or wireless Internet environment connected to the power transmission circuit 1 on the power transmission side as the port device.

<< Configuration of Semiconductor Integrated Circuit for Battery Charging Control >>
FIG. 2 is a diagram showing a configuration of semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG.

  As shown in FIG. 2, a semiconductor integrated circuit 212 for battery charge control and system power supply includes a step-down DC-DC converter 2121, a linear regulator 2122, a USB type detection circuit 2123, an input voltage selection circuit 2124, and an external interface 2125. And a built-in regulator 2126 and a gate drive control circuit 2127. Further, the semiconductor integrated circuit 212 for battery charge control and system power supply includes a P-channel MOS transistor MP3 and switches SW1, SW2, SW3, SW4.

  The supply terminal T1 of the first input voltage 1 has a power supply voltage for wireless power feeding of the power transmission circuit 1 via the first Schottky diode D1 and an AC-DC conversion power source of the AC power connection interface 24 via the second Schottky diode D2. The USB power supply voltage of the USB connection interface 23 is supplied to the supply terminal T2 for the second input voltage 2. The Schottky diodes D1 and D2 function as a backflow prevention element between the power supply voltage of the wireless power feeding of the power transmission circuit 1 and the AC-DC conversion power supply voltage of the AC power connection interface 24, but are lower than the PN junction diode. It functions as a voltage transmission element that transmits a power supply voltage with a forward voltage. The power supply voltage of the wireless power feeding of the power transmission circuit 1 is 5.5 to 20 volts, the AC-DC conversion power supply voltage of the AC power connection interface 24 is approximately 7 volts, and the USB connection interface 23 The USB power supply voltage is 5 volts.

  The step-down DC-DC converter 2121 is connected to an inductor L1 and a capacitor C1 via external terminals DDOUT1 (T5) and DDOUT2 (T6). Therefore, the step-down DC-DC converter 2121 starts up more slowly when the power is turned on than the linear regulator 2122, but operates as a switching regulator having higher power efficiency than the linear regulator 2122. On the other hand, the linear regulator 2122 operates as a series regulator that operates immediately after power-on.

  That is, the step-down DC-DC converter 2121 and the linear regulator 2122 are generated from the power supply voltage of the power transmission circuit 1 of 5.5 to 20 volts or the AC-DC conversion power supply voltage of the AC power connection interface 24 of approximately 7 volts. Generate a system supply voltage of 3.5 to 5 volts. Accordingly, the 5 volt system supply voltage from the step-down DC-DC converter 2121 and the linear regulator 2122 is supplied to the power receiving side system 3 via the switches SW2 and SW4 and the external terminal SYS (T4), while 5 volt. The USB power supply voltage of the USB connection interface 23 is supplied to the power receiving system 3 via the switch SW3 and the external terminal SYS (T4).

  The USB type detection circuit 2123 is configured such that the USB connection interface 23 is set to USB 1.1 or USB 1.0 from the bit rate of the differential data signals D + and D− of the USB connection interface 23 or the power supply capability of the supply terminal T2 of the second input voltage 2. It is detected whether the type is USB 2.0 or USB 3.0.

  The input voltage selection circuit 2124 executes the voltage detection of the supply terminal T1 of the first input voltage 1 and the voltage detection of the supply terminal of the supply terminal T2 of the second input voltage 2 in order to select the operation mode at the time of startup. On / off control of the switches SW1, SW2, SW3, and SW4 and control of the step-down DC-DC converter 2121, the built-in regulator 2126, and the gate drive control circuit 2127 are executed. Further, the input voltage selection circuit 2124 executes control of the USB type detection circuit 2123 and transmits the USB type detection data from the USB type detection circuit 2123 to the microcontroller unit (MCU) 22 and the power receiving side system 3 via the external interface 2125. It has a function to supply.

  Therefore, the external interface 2125 performs bidirectional communication of clock and serial data with the power receiving system 3 and the microcontroller unit (MCU) 22.

The built-in regulator 2126 is supplied with the power supply voltage for wireless power supply of the power transmission circuit 1 or the AC-DC conversion power supply voltage of the AC power connection interface 24 via the step-down DC-DC converter 2121 or the linear regulator 2122, or the USB The USB power supply voltage of the connection interface 23 is supplied. As a result, an operating voltage V _DD 18 of 1.8 volts and an operating voltage V _DD 30 of 3.0 volts are generated from the built-in regulator 2126 and supplied to the microcontroller unit (MCU) 22.

  The P-channel MOS transistor MP3 is controlled to be turned on by the input voltage selection circuit 2124 and the gate drive control circuit 2127, so that the system supply voltage of 3.5 V to 5 V of the external terminal SYS (T4) is supplied to the external terminal BAT. By supplying the secondary battery 26 via (T3), the secondary battery 26 is charged. For example, the secondary battery 26 is a lithium ion battery built in a multi-function mobile phone or the like, and its charging current is a relatively large current of approximately 0.5 A to 1.0 A.

  Further, the gate drive control circuit 2127 outputs an output signal for driving the gate of the P-channel MOS transistor MP3 so that the P-channel MOS transistor MP3 conducts bidirectionally between the external terminal SYS (T4) and the external terminal BAT (T3). Is generated. Accordingly, during the period in which the secondary battery 26 is charged, the charging current of the secondary battery 26 flows from the external terminal SYS (T4) to the external terminal BAT (T3). During the battery operation period, the discharge current of the secondary battery 26 flows from the external terminal BAT (T3) to the external terminal SYS (T4). Further, the gate drive control circuit 2127 has a function of preventing overcharge and overdischarge by executing current control of the charge current and the discharge current between the charging operation and the discharging operation of the secondary battery 26. It is.

  The semiconductor integrated circuit 212 for battery charging control according to the first embodiment shown in FIG. 2 is controlled such that the operation of the step-down DC-DC converter 2121 is stopped during the NFC communication period. However, since the linear regulator 2122 continues to operate even when the step-down DC-DC converter 2121 is stopped, the linear regulator 2122 mainly supplies power to the input voltage selection circuit 2124 and the microcontroller unit 22. . Therefore, as long as the power supply voltage is supplied to the input terminal T1, power is supplied from the linear regulator 2122 to the input voltage selection circuit 2124 and the microcontroller unit 22 even when the operation of the step-down DC-DC converter 2121 is stopped. Is supplied.

<External terminal function of semiconductor integrated circuit>
FIG. 3 is a diagram showing functions of external terminals of semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG.

  As shown in FIG. 3, the external supply terminal of the first input voltage 1 is connected to the power supply voltage of the wireless power feeding of the power transmission circuit 1 or the AC power connection interface 24 via the first Schottky diode D1 or the second Schottky diode D2. It has a function of supplying an AC-DC conversion power supply voltage.

  Further, the external supply terminal of the second input voltage 2 has a function of supplying the USB power supply voltage of the USB connection interface 23.

  The external supply terminal of the differential data signal D + has a function of supplying the non-inverted input signal D + of the differential data of the USB connection interface 23.

  Further, the external supply terminal of the differential data signal D− has a function of supplying the inverted input signal D− of the differential data of the USB connection interface 23.

  The external input / output terminal of the clock has a function of performing bidirectional communication of the clock of the external interface 2125.

  Further, the serial data external input / output terminal has a function of executing serial data bidirectional communication of the external interface 2125.

  The external terminal DDOUT1 has a function of outputting a switching output signal by a switching regulator operation in the step-down DC-DC converter 2121.

  Further, the external terminal DDOUT2 has a function of outputting the output voltage of the step-down DC-DC converter 2121 that has passed through a low-pass filter composed of an inductor L1 and a capacitor C1.

  The external terminal SYS has a function of outputting a power supply voltage to the power receiving side system 3.

  The external terminal BAT has a function of connecting the secondary battery 26.

The external terminal V _DD 18 has a function of outputting an operating voltage V _DD 18 of 1.8 volts to the microcontroller unit (MCU) 22.

The external terminal V _DD 30 has a function of outputting an operating voltage V _DD 30 of 3.0 volts to the microcontroller unit (MCU) 22.

《Basic configuration of power supply and charging》
FIG. 4 is a diagram showing a basic configuration for feeding power to the power receiving side system 3 of the semiconductor integrated circuit 212 and charging the secondary battery 26 for battery charging control according to the first embodiment shown in FIG. is there.

As shown in FIG. 4, the RF signal from the power transmission side antenna coil 13 is received by the reception side antenna coil 25, and the DC signal generated by the rectification circuit 211 rectifying and smoothing the RF signal of the power reception side antenna coil 25. The power supply voltage _VIN is supplied to the supply terminal T1 of the semiconductor integrated circuit 212 through the Schottky diode D1. A step-down DC-DC converter 2121 is connected to the supply terminal T1, and the step-down DC-DC converter 2121 includes a PWM control circuit 21211, a P-channel MOS transistor 21212 as a high-side switch, and an N-channel MOS transistor 21213 as a low-side switch. It is out. P to the source of channel MOS transistor 21212 is supplied with a DC supply voltage _{V IN,} drains of N-channel MOS transistor 21213 of the P-channel MOS transistor 21212 is connected to one end of the inductor L1 via the external terminal DDOUT1 (T5) The sources of the N-channel MOS transistors 21213 are connected to the ground potential via the external ground terminal DDGND.

  The PWM control circuit 21211 PWM drives the gate of the P-channel MOS transistor 21212 and the gate of the N-channel MOS transistor 21213 to generate a system supply voltage generated at a connection node where the other end of the inductor L1 and one end of the capacitor C1 are connected. Is supplied to the PWM control circuit 21211 via the external terminal DDOUT2 (T6) to the negative feedback terminal. The PWM control circuit 21211 performs PWM control on the ratio between the ON period of the P-channel MOS transistor 21212 and the ON period of the N-channel MOS transistor 21213 so that the system supply voltage at the negative feedback terminal becomes a predetermined voltage level.

  The system supply voltage from the step-down DC-DC converter 2121 generated at the external terminal DDOUT2 (T6) is supplied to the source of the P-channel MOS transistor Path_SW constituting the switch SW2, and the drain of the P-channel MOS transistor Path_SW is connected to the external terminal SYS. (T4) is connected to the drain of the P-channel MOS transistor MP3 and the gate drive control circuit 2127. Since the gate of the P-channel MOS transistor Path_SW of the switch SW2 is connected to the current limiting circuit 21241 included in the input voltage selection circuit 2124, the system power supply current and the battery charging current flowing through the source / drain path of the P-channel MOS transistor Path_SW Is adjusted by the current limiting circuit 21241.

The gate of the P-channel MOS transistor Mp3 for supplying the battery charging current to the secondary battery 26 via the external terminal BAT (T3) is connected to the gate drive control circuit 2127, and the gate drive control circuit 2127 is connected to the external terminal T11. One end of the resistor R _ICHG is connected to the other end, and the other end of the resistor R _ICHG is connected to the ground potential. As a result, by adjusting the resistance value of the resistor R _ICHG , it is possible to adjust the maximum value of the battery charging current flowing through the source / drain path of the P-channel MOS transistor Mp3.

《Detailed configuration of power supply and charging》
FIG. 5 is a diagram showing a detailed configuration for feeding power to the power receiving side system 3 of the semiconductor integrated circuit 212 and charging the secondary battery 26 for battery charging control according to the first embodiment shown in FIG. .

  As shown in FIG. 5, the current limiting circuit 21241 of the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 4 includes a differential amplifier 212411, an offset voltage circuit 2121241, P channel MOS transistors MP2, MP3, and a voltage control circuit 212413. And N-channel MOS transistors MN2 and MN3 and a resistor R_limit.

  The gate of the P-channel MOS transistor MP2 is connected to the gate of the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW constituting the switch SW2, and the element size of the P-channel MOS transistor MP1 and the element size of the P-channel MOS transistor MP2 are The ratio is set to M: 1. The source of the P-channel MOS transistor MP1, the source of the P-channel MOS transistor MP2, and one end of the resistor R3 are connected to the external terminal DDOUT2 (T6), the gate of the P-channel MOS transistor MP1, the gate of the P-channel MOS transistor MP2, and the resistor R3 The other end is connected to the source of P-channel MOS transistor MP3.

  Voltage control circuit 212413 includes a voltage comparison amplifier AMP and an N-channel MOS transistor MN4. The inverting input terminal − of the voltage comparison amplifier AMP is connected to the drain of the P channel MOS transistor MP1 as the P channel MOS transistor Path_SW of the switch SW2, and the non-inverting input terminal + of the voltage comparison amplifier AMP is connected to the drain of the N channel MOS transistor MN4. Connected to the drain of P-channel MOS transistor MP2.

One end of the resistor R_limit is connected to the source of the N-channel MOS transistor MN4 of the voltage control circuit 212413 and the other end of the first offset voltage Voffset of the offset voltage circuit 212412. The other end of the resistor R_limit is the drain / source of the N-channel MOS transistor MN3. It is connected to the ground potential through a path. The reference voltage V _{REF — U} is supplied to the other end of the second offset voltage Voffset of the offset voltage circuit 212412. One end of the first offset voltage Voffset and one end of the second offset voltage Voffset are connected to the non-inverting input terminal + of the differential amplifier 212411. Each is connected to the first inverting input terminal −. The input voltage detection output voltage V _{IN_DIV} generated from the input voltage selection circuit ₂₁₂₄₂ is supplied to the second inverting input terminal − of the differential amplifier 212411 via the low pass filter 21243. The output terminal of differential amplifier 212411 is connected to the gate of P channel MOS transistor MP3, and the drain of P channel MOS transistor MP3 is connected to the ground potential via the drain / source path of N channel MOS transistor MN2.

The input voltage detection circuit 21242 includes resistors R1 and R2, an N-channel MOS transistor MN1, and an offset current source Ioffset. One end of the resistor R1 is supplied with the DC power supply voltage _VIN of the supply terminal T1, and the other end of the resistor R1 is Connected to one end of the offset current source Ioffset and one end of the resistor R2. The other end of the offset current source Ioffset is connected to the ground potential, and the other end of the resistor R2 is connected to the ground potential via the drain / source path of the N-channel MOS transistor MN1. A detection voltage generated from a connection node between the other end of the resistor R1 and one end of the resistor R2 is supplied to an input terminal of the low-pass filter 21243.

The low-pass filter 21243 includes a resistor R _LPF and a capacitor C _LPF. One end of the resistor R _LPF is connected to the input terminal of the low-pass filter 21243, and the other end of the resistor R _LPF is the output terminal of the low-pass filter 21243 and the capacitor C _LPF . One end of the capacitor C _LPF is connected to the ground potential.

  An on / off control signal is supplied to the gate of the N-channel MOS transistor MN1 of the input voltage detection circuit 21242 and the gates of the N-channel MOS transistors MN2 and MN3 of the current limiting circuit 21241. When the input voltage detection circuit 21242 and the current limiting circuit 21241 are set in an active state, the N-channel MOS transistor MN1 of the input voltage detection circuit 21242 and the N-channel MOS of the current limiting circuit 21241 are turned on by a high level on / off control signal. The transistors MN2 and MN3 are controlled to be on, and the P-channel MOS transistors MP1 and MP2 are controlled to be active. When the input voltage detection circuit 21242 and the current limiting circuit 21241 are set in an inactive state, the N-channel MOS transistor MN1 of the input voltage detection circuit 21242 and the N-channel of the current limiting circuit 21241 are turned on by a low level on / off control signal. The MOS transistors MN2 and MN3 are controlled to be in an off state, and the P channel MOS transistors MP1 and MP2 are controlled to be in an inactive state.

  The current limiting circuit 21241 performs a current limiting operation for limiting the maximum value of the total current of the system power supply current and the battery charging current flowing in the source / drain path of the P channel MOS transistor MP1 as the P channel MOS transistor Path_SW constituting the switch SW2. Run as follows: That is, the current limiting circuit 21241 selects a low level voltage level between the first inverting input terminal − and the second inverting input terminal − of the differential amplifier 212411, and the differential amplifier is set to the selected low level voltage level. The drain current of the P-channel MOS transistor MP2 is controlled so that the voltage level of the non-inverting input terminal +212411 matches.

  The P-channel MOS transistor MP2 of the current limiting circuit 21241 and the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW constituting the switch SW2 function as an input transistor and an output transistor of the current mirror, respectively. The drain current of the P-channel MOS transistor MP1 functioning as the output transistor of the current mirror is set by controlling the drain current of the P-channel MOS transistor MP2 functioning as the input transistor of the current mirror by the current limiting circuit 21241. On the other hand, in the voltage control circuit 212413 of the current limiting circuit 21241, the drain voltage of the P-channel MOS transistor MP2 functioning as the input transistor of the current mirror matches the drain voltage of the P-channel MOS transistor MP1 functioning as the output transistor of the current mirror. Thus, negative feedback control is performed on the drain voltage of the P-channel MOS transistor MP2. As a result, the ratio of the drain current of the P channel MOS transistor MP1 and the drain current of the P channel MOS transistor MP2 is determined by the ratio M: 1 of the element size of the P channel MOS transistor MP1 and the element size of the P channel MOS transistor MP2. It will be set correctly.

<< Current limiting operation when DC power supply voltage is low >>
When the DC power supply voltage _VIN supplied to the supply terminal T1 is at a low level, the total voltage of the second offset voltage _Voffset supplied to the first inverting input terminal − of the differential amplifier 212411 and the reference voltage V _{REF_U} The voltage of the input voltage detection output voltage V _{IN_DIV} at the second inverting input terminal − of the differential amplifier 212411 becomes _lower than _Voffset + V _{REF_U} . As a result, the total voltage Voffset + V_limit of the current limit detection voltage V_limit of the resistor R_limit and the first offset voltage Voffset, which is the voltage level of the non-inverting input terminal + of the differential amplifier 212411, is applied to the second inverting input terminal − of the differential amplifier 212411. It is controlled to match the low level input voltage detection output voltage V _{IN — DIV} . That is, by controlling the drain current of the P-channel MOS transistor MP2 by the differential amplifier ₂₁₂₄₁ in response to the low-level input voltage detection output voltage V _{IN_DIV} , the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW constituting the switch SW2 is controlled. The maximum value of the total current flowing in the source / drain path is adjusted to a low level. The total current flowing through the source / drain path of the P-channel MOS transistor MP1 is the total current of the system power supply current and the battery charging current. As a result, the step-down DC-DC converter 2121 stops when the DC power supply voltage _VIN supplied to the supply terminal T1 is low, the power supplied by the wireless power supply is small, and the load current such as the charging current of the secondary battery 26 is large. It is possible to reduce the possibility of doing.

That is, as can be understood from FIG. 4, the total current of the system power supply current and the battery charging current is the source / drain path of the P-channel MOS transistor Path_SW constituting the switch SW2, the step-down DC-DC converter 2121 and the first input. The voltage is supplied from the rectifier circuit 211 and the reception-side antenna coil 25 via the supply terminal T1 for voltage 1. If the DC power supply voltage _VIN at the supply terminal T1 is at a low level and the power supply capability from the rectifier circuit 211 and the reception-side antenna coil 25 is at a low level, such as a communication operation period of NFC communication, FIG. When a large total current that is not controlled by the current limiting operation by the current limiting circuit 21241 shown in FIG. 5 flows, a large voltage drop is generated in the impedance between the rectifier circuit 211 and the receiving-side antenna coil 25. As a result, the DC power supply voltage _VIN supplied to the supply terminal T1 by this large voltage drop is lowered to a voltage level lower than the operation lower limit voltage of the step-down DC-DC converter 2121. Therefore, the converter by switching of the step-down DC-DC converter 2121 The operation stops.

However, due to the current limiting operation of the current limiting circuit 21241 according to the first embodiment shown in FIGS. 4 and 5, the current level of the total current of the system power supply current and the battery charging current is changed to the input voltage detection circuit 21242 and the low-pass filter 21243. _Is controlled to a low level in accordance with the low level of the input voltage detection output voltage V _{IN — DIV} generated from. Therefore, the voltage drop due to the impedance of the rectifier circuit 211 and the receiving antenna coil 25 is reduced, and the DC power supply voltage _VIN at the supply terminal T1 does not drop to a voltage level lower than the lower limit operating voltage of the step-down DC-DC converter 2121. Therefore, the possibility that the step-down DC-DC converter 2121 stops is reduced.

When the DC power supply voltage _VIN is at a low level, as described above, the current limit detection voltage V_limit of the resistor R_limit that is the voltage level of the non-inverting input terminal + of the differential amplifier 212411 and the first offset voltage Voffset The total voltage Voffset + V_limit matches the low level input voltage detection output voltage V _{IN_DIV} of the second inverting input terminal − of the differential amplifier 212411. Therefore, the following equation (1) is obtained.

  From the above equation (1), the following equation (2) is obtained.

<< Current limiting operation when DC power supply voltage is high >>
When the DC power supply voltage _VIN supplied to the supply terminal T1 is at a high level, the total voltage of the second offset voltage _Voffset supplied to the first inverting input terminal − of the differential amplifier 212411 and the reference voltage V _{REF_U} The voltage of the input voltage detection output voltage V _{IN_DIV} at the second inverting input terminal − of the differential amplifier 212411 becomes _higher than _Voffset + V _{REF_U} . As a result, the total voltage of the current limit detection voltage V_limit of the resistor R_limit and the first offset voltage Voffset, which is the voltage level of the non-inverting input terminal + of the differential amplifier 212411, is supplied to the first inverting input terminal − of the differential amplifier 212411. The second offset voltage _Voffset and the reference voltage V _{REF_U} are controlled so as to coincide with the total voltage. That is, by controlling the drain current of the P-channel MOS transistor MP2 by the differential amplifier ₂₂₁₂₄₁ in response to the total voltage _Voffset + V _{REF_U} that is the reference voltage, the source of the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW constituting the switch SW2 The maximum value of the total current flowing in the drain path is adjusted to an appropriate level. The total current flowing through the source / drain path of the P-channel MOS transistor MP1 is the total current of the system power supply current and the battery charging current. As a result, the consumption of the step-down DC-DC converter 2121 when the DC power supply voltage _VIN supplied to the supply terminal T1 is at a high level, the feeding power of the wireless power feeding is large, and the load current such as the charging current of the secondary battery 26 is large. It is possible to prevent the current from becoming excessive.

When the DC power supply voltage _VIN supplied to the supply terminal T1 is at a high level, as described above, the total voltage Voffset + V_limit of the current limit detection voltage V_limit of the resistor R_limit and the first offset voltage Voffset is the second offset voltage Voffset. And the reference voltage V _{REF_U} is _equal to the total voltage _Voffset + V _{REF_U} . Therefore, the following equation (3) is obtained.

<Characteristics of current limiting operation>
FIG. 6 is a diagram showing the characteristics of the current limiting operation of the current limiting circuit 21241 according to the first embodiment shown in FIG. 4 and FIG.

  The system power supply that flows in the source / drain path of the P channel MOS transistor MP1 as the P channel MOS transistor Path_SW of the switch SW2 determined by the current limiting operation of the current limiting circuit 21241 according to the first embodiment shown in FIGS. The current level of the sum of the current and the battery charging current is determined by the current limit detection voltage V_limit of the resistor R_limit.

When the DC power supply voltage _VIN supplied to the supply terminal T1 is at a low level, the current limit detection voltage V_limit of the resistor R_limit that determines the current level of the total current flowing through the source / drain path of the P-channel MOS transistor MP1 is , Calculated by the above equation (2). Accordingly, as shown on the left side of FIG. 6, the current limit detection voltage V_limit of the resistor R_limit decreases in response to the level decrease of the DC power supply voltage _VIN .

For example, when the DC power supply voltage _VIN supplied to the supply terminal T1 decreases to a predetermined value V _{IN —} min, the current limit detection voltage V_limit decreases to zero volts, and the P channel MOS transistor as the P channel MOS transistor Path_SW of the switch SW2 The current level of the total current flowing in the source / drain path of MP1 is reduced to zero amperes. Furthermore, as shown on the left side of FIG. 6, even if a DC supply voltage V _IN supplied to the supply terminal T1 is reduced to a low level than the predetermined value V _IN _min, current limit detection voltage V_limit is maintained at zero volts switch SW2 The current level of the total current flowing in the source / drain path of the P channel MOS transistor MP1 as the P channel MOS transistor Path_SW is maintained at zero amperes.

In FIG. 6, the operation lower limit voltage V _{DC-DC_LIMIT at} which the converter operation by switching of the step-down DC-DC converter 2121 stops when the impedance of the rectifier circuit 211 and the reception-side antenna coil 25 is assumed to be zero is the predetermined value described above. It is shown that the level is lower than V _{IN —} min. Accordingly, the source of the P-channel MOS transistor MP1 as the P-channel MOS transistor _{Path_SW} of the switch SW2 at the operation lower limit voltage V _{DC-DC_LIMIT} at which the converter operation of the step-down DC-DC converter 2121 stops when the above-described impedance is assumed to be zero. -The current level of the total current flowing in the drain path is reliably reduced to zero amperes.

Therefore, in the semiconductor integrated circuit 212 for battery charging control according to the first embodiment shown in FIGS. 4 and 5, when the impedances of the rectifier circuit 211 and the receiving-side antenna coil 25 are non-negligible resistance values, Can be realized. That is, the current level of the total current is reduced to a low level according to the low level of the input voltage detection output voltage V _{IN_DIV} generated from the input voltage detection circuit 21242 and the low-pass filter 21243 under the operation condition near the voltage of the operation lower limit voltage V _{DC-DC_LIMIT.} Be controlled. As a result, the voltage drop due to the impedance of the rectifier circuit 211 and the receiving antenna coil 25 is reduced, and the possibility that the step-down DC-DC converter 2121 stops is reduced.

When the DC power supply voltage _VIN supplied to the supply terminal T1 is at a high level, the current limit detection voltage V_limit of the resistor R_limit that determines the current level of the total current flowing in the source / drain path of the P-channel MOS transistor MP1 is , Calculated by the above equation (3). Accordingly, as shown on the right side of FIG. 6, the current limit detection voltage V_limit of the resistor R_limit is substantially supplied to the first inverting input terminal − of the differential amplifier 212411 because it is substantially irrelevant to the level change of the DC power supply voltage _VIN. The value of the reference voltage V _{REF — U} is maintained substantially constant. Therefore, the current level of the total current flowing through the source / drain path of the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW of the switch SW2 is set to an appropriate substantially constant current level. As a result, when the secondary battery 26 connected to the power receiving system 3 connected to the external terminal SYS (T4) or the external terminal BAT (T3) is overloaded, the current consumption of the step-down DC-DC converter 2121 Can be prevented from becoming excessive. Note that, as shown on the right side of FIG. 6, the maximum value V _{IN —} max of the DC power supply voltage _VIN supplied to the supply terminal T1 is 20 volts, which is the maximum power supply voltage for wireless power feeding, and the maximum DC power supply of 20 volts. At the voltage V _{IN —} max, the current limit detection voltage V_limit and the total current of the P-channel MOS transistor MP1 are each kept constant.

FIG. 6 shows the current limit detection voltage of the resistor R_limit when the battery charge control semiconductor integrated circuit 212 does not include the current limit circuit 21241 that executes the current limit operation in response to the level of the DC power supply voltage _{VIN at} the supply terminal T1. The characteristic of V′_limit is also shown. That is, in the characteristic of the current limit detection voltage V′_limit shown in FIG. 6, the current limit detection voltage V′_limit under the operating condition _{equal to} or higher than the operation lower limit voltage V _{DC-DC_LIMIT} where the operation of the step-down DC-DC converter 2121 stops is DC It becomes substantially irrelevant to the level change of the power supply voltage _VIN , and is maintained substantially constant at the value of the reference voltage V _{REF — U.} As a result, in this case, even if a DC supply voltage V _IN supplied to the supply terminal T1 is reduced to a predetermined value V _IN _min, current limit detection voltage V'_limit is maintained constant at the reference voltage V _{REF_U,} The current level of the total current flowing through the source / drain path of the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW of the switch SW2 is also maintained at a large current. Therefore, a large voltage drop is generated in the impedances of the rectifier circuit 211 and the reception-side antenna coil 25 by the large total current of the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW of the switch SW2. As a result, the DC power supply voltage _VIN supplied to the supply terminal T1 due to this large voltage drop falls to a voltage level lower than the operation lower limit voltage of the step-down DC-DC converter 2121. Therefore, the converter by switching of the step-down DC-DC converter 2121 The operation stops.

In the battery charge control semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 5, the second offset voltage Voffset supplied to the first inverting input terminal − of the differential amplifier 212411 is the same as that of the differential amplifier 212411. The input voltage detection output voltage V _{IN — DIV} supplied to the 2 inverting input terminal − is easily selected by the differential amplifier 212411 as a low level selection voltage. Further, the second offset voltage Voffset also has a function of reducing the influence of the internal error offset voltage related to the non-inverting input terminal +, the first inverting input terminal −, and the second inverting input terminal − of the differential amplifier 212411. Is. Further, the first offset voltage Voffset supplied to the non-inverting input terminal + of the differential amplifier ₂₁₂₄₁₁ has an influence on the reference voltage V _{REF_U} by the second offset voltage _Voffset supplied to the first inverting input terminal − of the differential amplifier 212411. It also has a function to reduce the above.

<Characteristics of total switch current>
FIG. 7 is a diagram showing the characteristic of the total current I_limit of the switch SW2 realized by the characteristic of the current limiting operation of the current limiting circuit 21241 according to the first embodiment shown in FIGS.

In FIG. 7, an operating point A indicates that the converter operation by switching of the step-down DC-DC converter 2121 starts in the initial state where the DC power supply voltage _VIN supplied to the supply terminal T1 is approximately 15 volts.

  As a result of the start of the converter operation by switching of the step-down DC-DC converter 2121, the total current I_limit flowing in the source / drain path of the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW of the switch SW2 is shown in FIGS. It is determined by the current limiting operation of the current limiting circuit 21241 according to the first embodiment shown.

Therefore, when the DC power supply voltage _VIN supplied to the supply terminal T1 is at a high level, it depends on the current limit detection voltage V_limit maintained substantially constant at the value of the reference voltage V _{REF_U} on the right side of FIG. As shown in the right side of FIG. 7, the total current I_limit of the switch SW2 is also a current value that is maintained substantially constant. As a result, the total current I_limit of the switch SW2 shown on the right side of FIG. 7 is calculated by the following equation (4).

Thereafter, as the DC power supply voltage _VIN supplied to the supply terminal T1 changes from a high level to a low level, the DC power supply voltage _VIN decreases in response to a decrease in the level of the DC power supply voltage _VIN as shown on the left side of FIG. Depending on the current limit detection voltage V_limit, as shown on the left side of FIG. 7, the total current I_limit of the switch SW2 also decreases in response to the level decrease of the DC power supply voltage _VIN . As a result, the total current I_limit of the switch SW2 shown on the left side of FIG. 7 is calculated by the following equation (5).

The operating point B shown in FIG. 7 shows a state where the DC power supply voltage _VIN of the supply terminal T1 starts from the operating point A in the initial state of approximately 15 volts and decreases to approximately 8 volts. As described above, at the operating point B where the DC power supply voltage _VIN of the supply terminal T1 is lowered to about 8 volts, the total current of the low-level wireless power supply current, the system power-supply current due to the low-level current limit, and the battery charging current. And balance.

FIG. 7 shows the total current I ′ of the switch SW2 when the semiconductor integrated circuit 212 for battery charging control does not include the current limiting circuit 21241 that executes the current limiting operation in response to the level of the DC power supply voltage _{VIN at} the supply terminal T1. The _limit property is also shown. That is, in the characteristic of the total current I′_limit of the switch SW2 shown in FIG. 7, the total current I′_limit under the operating condition _{equal to} or higher than the operation lower limit voltage V _{DC-DC_LIMIT} where the operation of the step-down DC-DC converter 2121 stops is DC The power supply voltage _{VIN remains} substantially constant regardless of the level change. Therefore, in this case, even if a DC supply voltage _{V IN} supplied to the supply terminal T1 is reduced to a predetermined value _V IN _min, the source and drain of P-channel MOS transistor MP1 as P-channel MOS transistor Path_SW switch SW2 The current level of the total current I′_limit flowing through the path is also maintained at a constant current. Therefore, a large voltage drop is generated in the impedances of the rectifier circuit 211 and the reception-side antenna coil 25 by the large total current of the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW of the switch SW2. As a result, the DC power supply voltage _VIN supplied to the supply terminal T1 due to this large voltage drop falls to a voltage level lower than the operation lower limit voltage of the step-down DC-DC converter 2121. Therefore, the converter by switching of the step-down DC-DC converter 2121 The operation stops.

<< Operation of Semiconductor Integrated Circuit without Current Limiting Circuit for Performing Current Limiting Operation Responding to DC Power Supply Voltage Level >>
FIG. 8 shows the operation of the semiconductor integrated circuit 212 in the case where the battery charge control semiconductor integrated circuit 212 does not include the current limiting circuit 21241 that executes the current limiting operation in response to the level of the DC power supply voltage _{VIN at} the supply terminal T1. FIG.

  The time change of the voltage waveform of each part of the semiconductor integrated circuit 212 is shown in the upper part of FIG. 8, and the time change of the current waveform of each part of the semiconductor integrated circuit 212 is shown in the lower part of FIG.

As shown in the current waveform at the bottom of FIG. 8, the maximum value of the battery current adjusted by the resistance value of the resistor R _ICHG connected to the external terminal T11 is substantially constant controlled by the current limiting circuit 21241. This is set to a level lower than the current limiting current I′_limit.

In the first period T1 in FIG. 8, the supply to the supply terminal T1 of the low-level DC power supply voltage _{V IN} is started, the level of the DC power supply voltage _{V IN} of the supply terminal T1 and the rectifier circuit 211 receiving antenna coil 25 Ascending according to the time constant. On the other hand, the system supply voltage (SYS voltage) supplied to the power receiving system 3 via the external terminal SYS (T4) is set to the battery voltage from the secondary battery 26 in the first period T1.

Since the DC power supply voltage _VIN of the supply terminal T1 exceeds the DC-DC start-up voltage of the step-down DC-DC converter 2121 during the elapse of the first period T1, the start-up delay time elapses and the second period T2 in FIG. Then, the converter operation by switching of the step-down DC-DC converter 2121 is started. Therefore, in the second period T2, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 generated from the external terminal DDOUT2 (T6) starts to rise. Since the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 exceeds a predetermined voltage during the elapse of the second period T2, in response to this voltage excess, the input voltage selection circuit 2124 displays the P-channel MOS transistor of the switch SW2. The P-channel MOS transistor MP1 as Path_SW is controlled from the off state to the on state.

  As a result, in the third period T3, the system supply voltage (SYS voltage) of the external terminal SYS (T4) is stepped down from the external terminal DDOUT2 (T6) due to the ON state of the P-channel MOS transistor MP1 of the switch SW2. It is set by the output voltage (DDOUT2 voltage) of the DC-DC converter 2121.

  Further, in response to the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 exceeding a predetermined voltage during the elapse of the second period T2, the timer circuit in the input voltage selection circuit 2124 receives a clock (not shown). While executing the signal counting operation, the P channel MOS transistor MP3 between the external terminal SYS (T4) and the external terminal BAT (T3) is controlled to be in an ON state.

That is, since the P-channel MOS transistor MP3 between the external terminal SYS (T4) and the external terminal BAT (T3) is controlled to be in the ON state in the fourth period T4, the battery charging current is supplied to the secondary battery 26. Be started. When the amount of battery charging current is large and the battery supply power is larger than the transmission power from the rectifier circuit 211, the output voltage of the rectifier circuit 211, that is, the DC power supply voltage _VIN of the supply terminal T1 decreases. Therefore, since the DC power supply voltage _VIN of the supply terminal T1 falls to a voltage level lower than the DC-DC stop voltage of the step-down DC-DC converter 2121 at the end of the fourth period T4, the converter by switching of the step-down DC-DC converter 2121 The operation stops. Note that the DC-DC stop voltage shown in FIG. 4 means the operation lower limit voltage of the step-down DC-DC converter 2121 described above.

In the fifth period T5, in response to the operation stop of the step-down DC-DC converter 2121 and the OFF state of the P-channel MOS transistor MP1 of the switch SW2, the battery charging current is set to zero ampere. As a result, the output voltage of the rectifier circuit 211, that is, the DC power supply voltage _VIN of the supply terminal T1 increases. Accordingly, in the subsequent sixth period T6 and seventh period T7, the operations in the second period T2 and the third period T3 and the operation in the fourth period T4 are repeated.

As described above, when the battery supply power is larger than the transmission power from the rectifier circuit 211, the DC power supply voltage _{VIN at} the supply terminal T1 decreases and the step-down DC-DC converter 2121 stops. Therefore, the battery cannot be charged.

<< Operation of Semiconductor Integrated Circuit with Current Limiting Circuit for Performing Current Limiting Operation Responding to DC Power Supply Voltage Level >>
FIG. 9 shows a battery integrated circuit for controlling the current limiting circuit 21241 that performs a current limiting operation in response to the level of the DC power supply voltage _{VIN at} the supply terminal T1 according to the first embodiment shown in FIGS. FIG. 6 is a diagram illustrating an operation of the semiconductor integrated circuit 212 when the reference numeral 212 is provided.

  The time variation of the voltage waveform of each part of the semiconductor integrated circuit 212 according to the first embodiment is shown in the upper part of FIG. 9, and the time waveform of the current waveform of each part of the semiconductor integrated circuit 212 according to the first embodiment is shown in the lower part of FIG. Changes are shown.

Note that, as shown in the current waveform at the bottom of FIG. 9, the maximum value of the battery current adjusted by the resistance value of the resistor R _ICHG connected to the external terminal T11 is the supply terminal T1 controlled by the current limiting circuit 21241. Is set at a level lower than the maximum value of the current limiting current I_limit in response to the level of the DC power supply voltage _VIN .

In the first period T1 in FIG. 9, the supply to the supply terminal T1 of the low-level DC power supply voltage _{V IN} is started, the level of the DC power supply voltage _{V IN} of the supply terminal T1 and the rectifier circuit 211 receiving antenna coil 25 Ascending according to the time constant. On the other hand, the system supply voltage (SYS voltage) supplied to the power receiving system 3 via the external terminal SYS (T4) is set to the battery voltage from the secondary battery 26 in the first period T1.

Since the DC power supply voltage _VIN of the supply terminal T1 exceeds the DC-DC start-up voltage of the step-down DC-DC converter 2121 during the elapse of the first period T1, the start-up delay time elapses and the second period T2 in FIG. , The converter operation by switching of the step-down DC-DC converter 2121 is started. Accordingly, in the second period T2, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 generated from the external terminal DDOUT2 (T6) starts to rise. Since the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 exceeds a predetermined voltage during the elapse of the second period T2, in response to this voltage excess, the input voltage selection circuit 2124 displays the P-channel MOS transistor of the switch SW2. The P-channel MOS transistor MP1 as Path_SW is controlled from the off state to the on state.

  As a result, in the third period T3, the system supply voltage (SYS voltage) of the external terminal SYS (T4) is step-down DC-DC generated from the external terminal DDOUT2 (T6) due to the ON state of the P-channel MOS transistor MP1 of the switch SW2. It is set by the output voltage (DDOUT2 voltage) of converter 2121.

  Further, in response to the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 exceeding a predetermined voltage during the elapse of the second period T2, the timer circuit in the input voltage selection circuit 2124 receives a clock (not shown). While executing the signal counting operation, the P-channel MOS transistor Mp3 between the external terminal SYS (T4) and the external terminal BAT (T3) is controlled to be in an ON state.

In the fourth period T4, since the P-channel MOS transistor Mp3 between the external terminal SYS (T4) and the external terminal BAT (T3) is controlled to be on, supply of the battery charge current of the secondary battery 26 is started. The However, when the battery charging current amount is large and the battery supply power is larger than the transmission power from the rectifier circuit 211, the output voltage of the rectifier circuit 211, that is, the DC power supply voltage _VIN of the supply terminal T1 is the fourth period. It decreases at T4.

According to the first embodiment shown in FIGS. 4 and 5, the P-channel MOS transistor as the P-channel MOS transistor Path_SW of the switch SW2 in response to the decrease in the level of the DC power supply voltage _VIN supplied to the supply terminal T1. The current limit level of the total current flowing through the source / drain path of MP1 also decreases.

In the fifth period T5, the current limit level of the total current I_limit flowing in the source / drain path of the P-channel MOS transistor MP1 as the P-channel MOS transistor Path_SW of the switch SW2 is the DC power supply voltage _VIN supplied to the supply terminal T1. It decreases in response to a decrease in level.

  In the sixth period T6, the battery charging current to the secondary battery 26 is set to a low level according to the current limit level of the total current I_limit of the switch SW2 that is decreasing.

As a result, the battery charging current is suppressed by the current limiting function by the switch SW2 in response to the DC supply voltage _{V IN} of the seventh period T7 in the supply terminal T1, a DC supply voltage _{V IN} of the supply terminal T1 buck DC-DC It is maintained at a voltage level higher than the DC-DC stop voltage of converter 2121. Therefore, by using the current limiting circuit 21241 that performs a current limiting operation in response to the level of the DC power supply voltage _VIN of the supply terminal T1 according to the first embodiment shown in FIGS. 4 and 5, a step-down DC-DC converter is used. The problem that the operation of 2121 stops and the battery charging current cannot be supplied can be solved.

<Operation when the current limit current is set higher than the maximum battery current during wireless power supply>
FIG. 10 shows a maximum battery in which the current limiting current of the P-channel MOS transistor MP1 of the switch SW2 is adjusted by the resistor R _ICHG in a state where the intermediate level or high level DC power supply voltage _VIN is supplied to the supply terminal T1 by wireless power feeding. It is a figure which shows operation | movement of the semiconductor integrated circuit 212 at the time of setting higher than an electric current.

  The upper part of FIG. 10 shows the temporal change of the voltage waveform of each part of the semiconductor integrated circuit 212 according to the first embodiment, and the lower part of FIG. 10 shows the time of the current waveform of each part of the semiconductor integrated circuit 212 according to the first embodiment. Changes are shown.

As shown in the current waveform at the bottom of FIG. 10, the supply terminal controlled by the current limiting circuit 21241 rather than the maximum battery current value adjusted by the resistance value of the resistor R _ICHG connected to the external terminal T11. The maximum value of the current limiting current (I_limit) in response to a substantially constant intermediate level or high level of the DC power supply voltage _VIN of T1 is set high.

  In the period T11 of FIG. 10, as shown in the current waveform at the bottom of FIG. 10, the system power supply current supplied to the power receiving system 3 increases as the time of wireless power supply elapses, and the battery charge of the secondary battery 26 increases. Therefore, a maximum battery current having a substantially constant value flows, and the total current of the system power supply current and the battery charging current increases. In the period T11 of FIG. 10, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is maintained substantially constant as shown in the upper voltage waveform of FIG. 10, and the system supply voltage of the external terminal SYS (T4) is maintained. (SYS voltage) decreases, and the battery voltage (BAT voltage) of the external terminal BAT (T3) increases.

  In the period T12 of FIG. 10, as shown in the current waveform at the bottom of FIG. 10, the increase in the total current of the system power supply current and the battery charging current is the current limit current (I_limit) in the P-channel MOS transistor MP1 of the switch SW2. Clamped by a constant value. Therefore, in the period T12 of FIG. 10, the system power supply current increases with time, while the battery charging current decreases. Further, in the period T12 of FIG. 10, as shown in the voltage waveform at the top of FIG. 10, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is kept constant, and the system supply of the external terminal SYS (T4) is performed. The voltage (SYS voltage) is also maintained constant, and the battery voltage (BAT voltage) at the external terminal BAT (T3) increases.

  In the period T13 of FIG. 10, as shown in the current waveform at the bottom of FIG. 10, the increase in the total current of the system power supply current and the battery charging current is the current limit current (I_limit) in the P-channel MOS transistor MP1 of the switch SW2. Clamped by a constant value. On the other hand, in the period T13 of FIG. 10, the system power supply current exceeds the current limiting current (I_limit) in the P-channel MOS transistor MP1 of the clamp level switch SW2, so the battery charging current for the secondary battery 26 is A negative current value of zero ampere or less is obtained, and the battery discharge current is supplied from the secondary battery 26 to the power receiving system 3. Furthermore, in the period T13 of FIG. 10, as shown in the voltage waveform at the top of FIG. 10, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is maintained constant, and the system supply of the external terminal SYS (T4) is performed. The voltage (SYS voltage) slightly decreases, and the battery voltage (BAT voltage) of the external terminal BAT (T3) also decreases slightly.

  In the period T14 in FIG. 10, the system power supply current decreases to a level smaller than the current limiting current (I_limit) in the P-channel MOS transistor MP1 of the clamp level switch SW2 as shown in the current waveform in the lower part of FIG. Therefore, in the period T14, the total current of the system power supply current and the battery charging current is clamped by a constant value of the current limiting current (I_limit) of the P-channel MOS transistor MP1 of the switch SW2, and the battery charging current increases. Furthermore, in the period T14 of FIG. 10, as shown in the voltage waveform at the top of FIG. 10, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is maintained constant, and the system of the external terminal SYS (T4) is maintained. The supply voltage (SYS voltage) is also maintained constant, and the battery voltage (BAT voltage) at the external terminal BAT (T3) increases.

  In the period T15 in FIG. 10, as shown in the current waveform at the bottom of FIG. 10, the battery charging current is maintained at the maximum battery current at a substantially constant value, while the system feeding current is decreased. The total current of the battery charging current is reduced to a level lower than the current limiting current (I_limit) of the P-channel MOS transistor MP1 of the switch SW2. Further, in the period T15 in FIG. 10, as shown in the upper voltage waveform in FIG. 10, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is kept constant, and the system supply of the external terminal SYS (T4) is performed. The voltage (SYS voltage) increases, and the battery voltage (BAT voltage) of the external terminal BAT (T3) also increases.

  By the operation of the semiconductor integrated circuit 212 shown in FIG. 10, system power feeding to the power receiving side system 3 by wireless power feeding and charging to the secondary battery 26 are executed.

<Operation when the maximum battery current is set higher than the current limit current during wireless power supply>
FIG. 11 shows the current limit of the P-channel MOS transistor MP1 of the switch SW2 with the maximum battery current adjusted by the resistor R _ICHG in a state where the intermediate or high level DC power supply voltage _VIN is supplied to the supply terminal T1 by wireless power feeding. It is a figure which shows operation | movement of the semiconductor integrated circuit 212 at the time of setting higher than an electric current.

  11 shows the time variation of the voltage waveform of each part of the semiconductor integrated circuit 212 according to the first embodiment, and the lower part of FIG. 11 shows the time of the current waveform of each part of the semiconductor integrated circuit 212 according to the first embodiment. Changes are shown.

As shown in the current waveform at the bottom of FIG. 11, the current limit current (I_limit) in response to a substantially constant intermediate level or high level of the DC power supply voltage _VIN of the supply terminal T1 controlled by the current limit circuit 21241. The maximum battery current value adjusted by the resistance value of the resistor R _ICHG connected to the external terminal T11 is set higher than the maximum value of.

  In the period T11 of FIG. 11, as shown in the current waveform at the bottom of FIG. 11, the system power supply current supplied to the power receiving system 3 is maintained at substantially zero ampere as the wireless power supply time elapses, and the secondary battery 26 The battery charging current for charging the battery is clamped by a constant value of the current limiting current (I_limit) in the P-channel MOS transistor MP1 of the switch SW2. Therefore, in the period T11 in FIG. 11, the total current of the system power supply current and the battery charging current is also clamped by a constant value of the current limiting current (I_limit) in the P-channel MOS transistor MP1 of the switch SW2. In the period T11 in FIG. 11, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is maintained substantially constant as shown in the upper voltage waveform in FIG. 11, and the system supply voltage of the external terminal SYS (T4) (SYS voltage) is also maintained substantially constant, and the battery voltage (BAT voltage) of the external terminal BAT (T3) increases.

  In the period T12 in FIG. 11, the total current of the system power supply current and the battery charging current is a constant value of the current limiting current (I_limit) in the P-channel MOS transistor MP1 of the switch SW2, as shown in the current waveform at the bottom of FIG. Is clamped by. On the other hand, in the period T12 of FIG. 11, the system power supply current increases with time, whereas the battery charging current decreases. Further, in the period T12 of FIG. 11, as shown in the voltage waveform at the top of FIG. 11, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is maintained constant, and the system supply of the external terminal SYS (T4) is performed. The voltage (SYS voltage) is also kept constant, and the battery voltage (BAT voltage) at the external terminal BAT (T3) increases.

  In the period T13 of FIG. 11, as shown in the current waveform at the bottom of FIG. 11, the increase in the total current of the system power supply current and the battery charging current is the current limit current (I_limit) in the P-channel MOS transistor MP1 of the switch SW2. Clamped by a constant value. On the other hand, in the period T13 in FIG. 11, the system power supply current exceeds the current limiting current (I_limit) in the P-channel MOS transistor MP1 of the clamp level switch SW2, so the battery charging current for the secondary battery 26 is A negative current value of zero ampere or less is obtained, and the battery discharge current is supplied from the secondary battery 26 to the power receiving system 3. Further, in the period T13 in FIG. 11, as shown in the upper voltage waveform in FIG. 11, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is maintained constant, and the system supply of the external terminal SYS (T4) is performed. The voltage (SYS voltage) slightly decreases, and the battery voltage (BAT voltage) of the external terminal BAT (T3) also decreases slightly.

  In the period T14 in FIG. 11, the system power supply current decreases to a level smaller than the current limiting current (I_limit) in the P-channel MOS transistor MP1 of the clamp level switch SW2 as shown in the current waveform in the lower part of FIG. Therefore, in the period T14, the total current of the system power supply current and the battery charging current is clamped by a constant value of the current limiting current (I_limit) of the P-channel MOS transistor MP1 of the switch SW2, and the battery charging current increases. Further, in the period T14 of FIG. 11, as shown in the voltage waveform at the top of FIG. 11, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is maintained constant, and the system of the external terminal SYS (T4) is maintained. The supply voltage (SYS voltage) is also maintained constant, and the battery voltage (BAT voltage) at the external terminal BAT (T3) increases.

  In the period T15 of FIG. 11, as shown in the current waveform at the bottom of FIG. 11, the system power supply current is maintained at substantially zero amperes, while the battery charging current and the total current of the system power supply current and the battery charging current are Clamped by a constant value of the current limiting current (I_limit) in the P-channel MOS transistor MP1 of SW2. Further, in the period T15 in FIG. 11, as shown in the voltage waveform at the top in FIG. 11, the output voltage (DDOUT2 voltage) of the step-down DC-DC converter 2121 is maintained constant, and the system supply of the external terminal SYS (T4) is performed. The voltage (SYS voltage) is also kept constant, and the battery voltage (BAT voltage) of the external terminal BAT (T3) also increases.

  By the operation of the semiconductor integrated circuit 212 shown in FIG. 11, system power feeding to the power receiving system 3 by wireless power feeding and charging to the secondary battery 26 are executed.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, an electronic device in which the semiconductor integrated circuit is mounted is not limited to a portable personal computer such as a multi-function mobile phone or a tablet PC, but a digital video camera, a digital still camera, a portable music player, a portable music player, or the like. It can be applied to a DVD player or the like.

DESCRIPTION OF SYMBOLS 1 ... Power transmission circuit 2 ... Power reception circuit 3 ... Power receiving side system 10 ... AC adapter 11 ... Microcontroller unit (MCU)
DESCRIPTION OF SYMBOLS 111 ... Authentication processing function 112 ... Encryption processing function 12 ... Power transmission control circuit 121 ... Rectification circuit 122 ... RF driver 13 ... Power transmission side antenna coil 21 ... Power reception control circuit 211 ... Rectification circuit 22 ... Microcontroller unit (MCU)
221 ... Authentication processing function 222 ... Cryptographic processing function 23 ... USB connection interface 24 ... AC power supply connection interface 25 ... Power receiving side antenna coil 26 ... Secondary battery 212 ... Semiconductor integrated circuit T1 to T10 ... Terminals D1, D2 ... Schottky diode 2121 ... Step-down DC-DC converter 2122 ... Linear regulator 2123 ... USB type detection circuit 2124 ... Input voltage selection circuit 2125 ... External interface 2126 ... Built-in regulator 2127 ... Gate drive control circuit SW1, SW2, SW3, SW4 ... Switch Mp1, Mp2, Mp3: P-channel MOS transistor Mn1, Mn2, Mn3 ... N-channel MOS transistor L1: Inductor C1: Capacitance 21211 ... PWM control circuit 21212 ... High-side switch 1213 ... side switch 21241 ... current limiting circuit 21242 ... input voltage detection circuit 21243 ... low-pass filter 212 411 ... differential amplifier 212412 ... offset voltage circuit 212413 ... voltage control circuit

Claims (14)

The semiconductor integrated circuit includes an input terminal, a DC-DC converter, an output terminal, a power switch transistor, a current limiting circuit, and an input voltage detection circuit.
The input terminal can be supplied with a DC input voltage generated by rectification and smoothing of an RF reception signal,
The DC-DC converter can generate a DC output voltage having a desired voltage level from the converter output terminal from the DC input voltage supplied to the input terminal.
The output terminal is capable of charging an external battery or feeding an external power receiving system using the DC output voltage,
The power switch transistor enables electrical conduction between the output terminal and the converter output terminal of the DC-DC converter,
The current limiting circuit executes current limitation of a load current of the power switch transistor flowing from the converter output terminal to the output terminal,
The input voltage detection circuit generates an input voltage detection signal by detecting a level of the DC input voltage supplied to the input terminal, and supplies the input voltage detection signal to the current limiting circuit.
In response to the input voltage detection signal supplied from the input voltage detection circuit, the current limit circuit controls the maximum current value due to the current limit of the power switch transistor,
When the DC input voltage supplied to the input terminal is at a high level, the current limiting circuit increases the value of the maximum current due to the current limitation of the power switch transistor in response to the input voltage detection signal. Control to current,
When the DC input voltage supplied to the input terminal is at a low level lower than the high level, the current limit circuit is responsive to the input voltage detection signal to maximize the current limit of the power switch transistor. Controlling the value of the current to a smaller current than the larger current ;
The power switch transistor is a P-channel MOS transistor whose source and drain are connected to the converter output terminal and the output terminal, respectively.
The gate of the P-channel MOS transistor of the power switch transistor is controlled by the current limiting circuit;
The current limiting circuit includes a control P-channel MOS transistor, a detection resistor, and a differential amplifier,
The source and drain of the control P-channel MOS transistor are connected to the converter output terminal and one end of the detection resistor, respectively, and the other end of the detection resistor is connected to the ground potential.
A reference voltage, the input voltage detection signal, and a detection voltage at the one end of the detection resistor are respectively supplied to the first inverting input terminal, the second inverting input terminal, and the non-inverting input terminal of the differential amplifier.
The gate of the P channel MOS transistor and the gate of the control P channel MOS transistor are controlled by an output signal of the differential amplifier,
The differential amplifier selects a low voltage level among the reference voltage of the first inverting input terminal and the input voltage detection signal of the second inverting input terminal, and the selected low voltage level The semiconductor integrated circuit , wherein the output signal of the differential amplifier controls the drain current of the control P-channel MOS transistor so that the detected voltage at the non-inverting input terminal coincides with the control voltage. In claim 1,
When the reference voltage at the first inverting input terminal is at a lower level than the input voltage detection signal at the second inverting input terminal, the control P-channel MOS transistor so that the detection voltage matches the reference voltage. The drain current of the
When the input voltage detection signal of the second inverting input terminal is at a level lower than the reference voltage of the first inverting input terminal, the control P channel is set so that the detection voltage matches the input voltage detection signal. A semiconductor integrated circuit in which the drain current of the MOS transistor is controlled . In claim 2,
The current limiting circuit further includes an offset voltage circuit that generates a first offset voltage and a second offset voltage;
A first total voltage of the first offset voltage and the detection voltage is supplied to the non-inverting input terminal of the differential amplifier, and a second total voltage of the second offset voltage and the reference voltage is the first voltage of the differential amplifier. A semiconductor integrated circuit supplied to the first inverting input terminal . In claim 3,
The current limiting circuit further includes a voltage control circuit having a voltage comparison amplifier and a comparison control transistor,
A first input terminal and a second input terminal of the voltage comparison amplifier are respectively connected to the drain of the P-channel MOS transistor of the power switch transistor and the drain of the control P-channel MOS transistor;
The output terminal of the voltage comparison amplifier is connected to the control input terminal of the comparison control transistor, and the output current path of the comparison control transistor is connected between the drain of the control P-channel MOS transistor and the one end of the detection resistor. A semiconductor integrated circuit. In claim 4,
The input voltage detection circuit includes a first voltage dividing resistor and a second voltage dividing resistor,
The DC input voltage supplied to the input terminal is supplied to one end of the first voltage dividing resistor, the other end of the first voltage dividing resistor is connected to one end of the second voltage dividing resistor, The other end of the voltage dividing resistor is connected to the ground potential,
The semiconductor integrated circuit , wherein the input voltage detection signal is generated from a connection node between the other end of the first voltage dividing resistor and the one end of the second voltage dividing resistor of the input voltage detecting circuit. In claim 5,
The semiconductor integrated circuit further includes a low pass filter including a resistance element and a capacitance element,
The input voltage detection signal generated from the input voltage detection circuit is supplied to the input terminal of the low-pass filter, and the input voltage detection signal transmitted to the output terminal of the low-pass filter is the second inversion of the current limiting circuit. A semiconductor integrated circuit supplied to the input terminal . In claim 6,
An RF signal by NFC communication and an RF signal by wireless power feeding can be supplied to the input terminal in a time division manner . Semiconductor integrated circuit. In claim 7,
The semiconductor integrated circuit further comprises a linear regulator connected in parallel with the DC-DC converter connected between the input terminal and the output terminal,
The linear regulator operates immediately in response to the supply of the DC input voltage at the input terminal,
The DC-DC converter operates as a switching regulator having higher power efficiency than the linear regulator . In claim 8,
The input terminal is configured so that the DC input voltage can be supplied to the input terminal via the first Schottky diode and the AC-DC conversion voltage of the AC power connection interface via the second Schottky diode. <br/> Semiconductor integrated circuit. In claim 9,
The semiconductor integrated circuit further includes another input terminal and a switch,
The other input terminal is configured so that the USB power supply voltage of the USB connection interface can be supplied to the other input terminal.
The semiconductor integrated circuit , wherein one end and the other end of the switch are connected to the other input terminal and the output terminal, respectively .   An operation method of a semiconductor integrated circuit comprising an input terminal, a DC-DC converter, an output terminal, a power switch transistor, a current limiting circuit, and an input voltage detection circuit,
  The input terminal can be supplied with a DC input voltage generated by rectification and smoothing of an RF reception signal,
  The DC-DC converter can generate a DC output voltage having a desired voltage level from the converter output terminal from the DC input voltage supplied to the input terminal.
  The output terminal is capable of charging an external battery or feeding an external power receiving system using the DC output voltage,
  The power switch transistor enables electrical conduction between the output terminal and the converter output terminal of the DC-DC converter,
  The current limiting circuit executes current limitation of a load current of the power switch transistor flowing from the converter output terminal to the output terminal,
  The input voltage detection circuit generates an input voltage detection signal by detecting a level of the DC input voltage supplied to the input terminal, and supplies the input voltage detection signal to the current limiting circuit.
  In response to the input voltage detection signal supplied from the input voltage detection circuit, the current limit circuit controls the maximum current value due to the current limit of the power switch transistor,
  When the DC input voltage supplied to the input terminal is at a high level, the current limiting circuit increases the value of the maximum current due to the current limitation of the power switch transistor in response to the input voltage detection signal. Control to current,
  When the DC input voltage supplied to the input terminal is at a low level lower than the high level, the current limit circuit is responsive to the input voltage detection signal to maximize the current limit of the power switch transistor. Controlling the value of the current to a smaller current than the larger current;
  The power switch transistor is a P-channel MOS transistor whose source and drain are connected to the converter output terminal and the output terminal, respectively.
  The gate of the P-channel MOS transistor of the power switch transistor is controlled by the current limiting circuit;
  The current limiting circuit includes a control P-channel MOS transistor, a detection resistor, and a differential amplifier,
  The source and drain of the control P-channel MOS transistor are connected to the converter output terminal and one end of the detection resistor, respectively, and the other end of the detection resistor is connected to the ground potential.
  A reference voltage, the input voltage detection signal, and a detection voltage at the one end of the detection resistor are respectively supplied to the first inverting input terminal, the second inverting input terminal, and the non-inverting input terminal of the differential amplifier.
  The gate of the P channel MOS transistor and the gate of the control P channel MOS transistor are controlled by an output signal of the differential amplifier,
  The differential amplifier selects a low voltage level among the reference voltage of the first inverting input terminal and the input voltage detection signal of the second inverting input terminal, and the selected low voltage level The output signal of the differential amplifier controls the drain current of the control P-channel MOS transistor so that the detected voltage at the non-inverting input terminal coincides with
A method of operating a semiconductor integrated circuit.   In claim 11,
  When the reference voltage at the first inverting input terminal is at a lower level than the input voltage detection signal at the second inverting input terminal, the control P-channel MOS transistor so that the detection voltage matches the reference voltage. The drain current of the
  When the input voltage detection signal of the second inverting input terminal is at a level lower than the reference voltage of the first inverting input terminal, the control P channel is set so that the detection voltage matches the input voltage detection signal. The drain current of the MOS transistor is controlled
A method of operating a semiconductor integrated circuit.   In claim 12,
  The current limiting circuit further includes an offset voltage circuit that generates a first offset voltage and a second offset voltage;
  A first total voltage of the first offset voltage and the detection voltage is supplied to the non-inverting input terminal of the differential amplifier, and a second total voltage of the second offset voltage and the reference voltage is the first voltage of the differential amplifier. Supplied to the first inverting input terminal
A method of operating a semiconductor integrated circuit. In claim 13,
The current limiting circuit further includes a voltage control circuit having a voltage comparison amplifier and a comparison control transistor,
A first input terminal and a second input terminal of the voltage comparison amplifier are respectively connected to the drain of the P-channel MOS transistor of the power switch transistor and the drain of the control P-channel MOS transistor;
The output terminal of the voltage comparison amplifier is connected to the control input terminal of the comparison control transistor, and the output current path of the comparison control transistor is connected between the drain of the control P-channel MOS transistor and the one end of the detection resistor. A method of operating a semiconductor integrated circuit.

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