JP2014041406A - Semiconductor integrated circuit and operation method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent loss of control information of a control circuit, which is caused by re-executing a power-on reset operation in executing automatic selection for re-selecting a working power supply from a plurality of power supplies in response to a power failure.SOLUTION: A semiconductor integrated circuit 212 includes: a first power supply terminal T1; a second power supply terminal T2; an input voltage selection circuit 2124 that is connected to the terminals T1 and T2; first power switches SW1 and SW2; and a second power switch SW3. The input voltage selection circuit includes: a power-on reset circuit 21244; an input voltage detection circuit 21248; a first variable transmission circuit 2124Y1; a second variable transmission circuit 2124Y2; a voltage comparison/selection circuit 21243; and control circuits 21245 and 21246. In response to a power failure detection result, the control circuit sets the signal transmission amount of a variable transmission circuit, which corresponds to a power switch that has a lower priority out of first and second power switches, out of the first and second variable transmission circuits, so as to make it larger than the signal transmission amount of the other variable transmission circuit.

Description

  The present invention relates to a semiconductor integrated circuit and an operation method thereof, and more particularly, to control information of a control circuit by re-execution of a power-on reset operation when performing automatic selection for re-selecting a power source to be used from a plurality of power sources in response to a power failure. The present invention relates to a technique effective in eliminating the disappearance.

  For example, as described in Patent Document 1 and Patent Document 2 below, a semiconductor integrated circuit and an antenna coil are mounted on an IC card, and the power supply of this IC card is read / read called a card reader / card writer. The RF signal from the writing device is received by an antenna coil and rectified by a rectifier circuit. Thus, IC cards that do not have a power source on the card side are becoming widespread in automatic ticket gate systems, electronic money, logistics management, and the like. Thus, while this IC card is RF-fed, unique identification information (ID information) is stored in the built-in nonvolatile memory, so it is called an RFID card.

  On the other hand, a wireless power feeding system called “just-on-placement charging” that allows charging of a mobile device by simply placing the mobile device on a dedicated charging table without connecting a power cable to the mobile device such as a smartphone has become widespread. This wireless power supply system corresponds to the fact that the battery of a mobile phone called a smartphone is consumed greatly. In other words, smartphones are multifunctional mobile phones that have high compatibility with the Internet and are based on the functions of a personal computer, or multi-function mobile phones that have a PDA function added to phone / mail. Sometimes abbreviated. The wireless power supply system is based on an international standard called Qi (Qi) established by the industry group Wireless Power Consortium (WPC). According to the method, power can be supplied from the transmitting device to the receiving device. The advantage of this wireless power supply system is that it is not necessary to connect and disconnect the power connector for charging, and in particular, the work of opening and closing the connector cover of the power connector of the portable device can be omitted.

  Further, in Patent Document 3 below, in an electronic device that charges a battery by being selectively connected to two or more types of power sources, the connection with the power source receiving the power supply is immediately released. And use a controller to start charging the battery. That is, in the control by the controller, while the current is supplied from the AC power source to the AC connection unit, the battery is charged by the AC power source, and the current is not supplied from the AC power source to the AC connection unit. While current is being supplied to the battery, the battery is charged by the power supply of the external device. In particular, the controller is necessary to charge the battery via the external device by performing initial communication with the external device when the external device connection unit is connected to the external device while the battery is being charged by the AC power source. To set the correct charge. Specifically, the external device connection unit is a USB connection unit, and an interface of another standard such as IEEE1394 can be used. When the electronic device is connected to both the AC power source and the external device, the current from the AC power source is larger than the current from the external device, so the controller charges the battery with the AC power source.

  In Patent Document 4 below, the source / drain path of the first N-channel power MOS transistor is connected between the first input / output terminals, and the source / drain path of the second N-channel power MOS transistor is connected between the second input / output terminals. Thus, there is described a power switch IC in which a source / drain path of a third N-channel power MOS transistor is connected between third input / output terminals. The drain / source path of the third MOS transistor is connected between the gate of the third N-channel power MOS transistor and the ground potential, and the drain / source path of the fourth MOS transistor is connected between the gate of the second N-channel power MOS transistor and the ground potential. The drain / source path of the fifth MOS transistor is connected between the gate of the first N-channel power MOS transistor and the ground potential. The first input terminal is connected to the input terminal of the first inverter circuit and the input terminal of the second inverter circuit. The second input terminal and the third input terminal are the power supply terminal of the first inverter circuit and the power supply terminal of the second inverter circuit. And connected respectively. The output terminal of the first inverter circuit is connected to the gate of the third MOS transistor, the output terminal of the second inverter circuit is connected to the gate of the fourth MOS transistor, and the output terminal of the first inverter circuit and the output terminal of the second inverter circuit Is connected to the two input terminals of the two-input NOR gate circuit. Further, the output terminal of the 2-input NOR gate circuit is connected to the input terminal of the third inverter circuit, and the output terminal of the third inverter circuit is connected to the gate of the fifth MOS transistor. When the potential of the first input terminal decreases due to the occurrence of an abnormality, the output terminal of the first inverter circuit, the output terminal of the second inverter circuit, and the output terminal of the third inverter circuit become high level, and the third MOS transistor and the fourth MOS transistor And the fifth MOS transistor are turned on. Accordingly, the first N-channel power MOS transistor connected between the first input / output terminals, the second N-channel power MOS transistor connected between the second input / output terminals, and the third N-channel power connected between the third input / output terminals. All the power MOS transistors of the MOS transistor are controlled to be in an off state.

JP 2009-4949 A JP 2010-9353 A JP 2011-155830 A JP 2006-180226 A

  Prior to the present invention, the present inventor has determined the AC-DC power supply voltage generated by rectification and smoothing of the AC power supply voltage from the AC power supply, the USB power supply voltage from the USB connection, and the power supply voltage by the wireless power supply of the wireless power supply system described above. Engaged in the development of semiconductor integrated circuits for battery charge control that can be operated with multiple power supply voltages.

  In the course of this development, the present inventor examined the method of charging a battery with a plurality of power sources described in Patent Document 3, but an implementation for automatically selecting a power source to be used according to whether or not a plurality of power sources are powered. The problem that the method is not described in Patent Document 3 has been clarified by the study by the present inventor. That is, in the above-described semiconductor integrated circuit for battery charge control that can be operated by a plurality of power supply voltages, it is necessary to implement an electronic circuit that automatically selects a power supply to be used from a plurality of power supplies. .

  Furthermore, as a result of the study of the present inventor in the course of this development, it has been clarified that the method described in Patent Document 4 cannot automatically select a power source to be used from a plurality of power sources.

  Prior to the present invention, the present inventor studied a method of implementing an electronic circuit that automatically selects a power supply to be used from a plurality of power supplies by using a power-on reset circuit, an input voltage detection circuit, and a control circuit. Selection of the first power supply switch and the second power supply voltage for selecting the first power supply voltage by the power-on reset operation of the power-on reset circuit that responds to supply of at least one of the first power supply voltage and the second power supply voltage The control circuit for controlling the second power switch for resetting is reset.

  The input voltage detection circuit detects whether the first power supply voltage is supplied and whether the second power supply voltage is supplied in response to the end of the power-on reset operation. When the input voltage detection circuit detects the supply of the first power supply voltage but detects the non-supply of the second power supply voltage, the control circuit sets the first power switch and the second power switch to the on state and the off state, respectively. Control. On the other hand, when the input voltage detection circuit detects the supply of the second power supply voltage but detects the non-supply of the first power supply voltage, the control circuit sets the first power switch and the second power switch to the off state and the on state. To control each. Further, when the input voltage detection circuit detects both the supply of the first power supply voltage and the supply of the second power supply voltage, the control circuit sets the first power switch and the second power switch according to a preset priority order. One and the other are controlled to an on state and an off state, respectively.

  Prior to the present invention, the inventor examined the above-described method in more detail. After the input voltage detection circuit detects both the supply of the first power supply voltage and the supply of the second power supply voltage, for example, the higher one is used. When a power failure occurs in the first power supply voltage set in the priority order, it is necessary to execute automatic selection in which a power source to be used is selected again from a plurality of power sources in response to the power failure.

  However, for that purpose, it is necessary to execute the power-on reset operation of the power-on reset circuit again in response to the power failure. As a result, it has been clarified that the initial setting information set in the control circuit and the control information stored in the control circuit are cleared and lost by re-execution of the power-on reset operation.

  Therefore, the initial setting information lost in the control circuit must be reloaded from the boot program stored in the non-volatile memory such as the flash memory, while the control information lost in the control circuit is not backed up in the non-volatile memory or the like. Therefore, the problem that it is impossible to recover the lost control information was revealed.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  The outline of the typical embodiment disclosed in the present application will be briefly described as follows.

  That is, the semiconductor integrated circuit (212) according to the representative embodiment includes a first supply terminal (T1) capable of supplying a first power supply voltage and a second supply terminal capable of supplying a second power supply voltage. (T2), an input voltage selection circuit (2124) connected to the first supply terminal and the second supply terminal, a first power switch (SW1, SW2), and a second power switch (SW3). (See FIG. 2).

  The input voltage selection circuit (2124) includes a power-on reset circuit (21244), an input voltage detection circuit (21248), a first variable transmission circuit (2124Y1), a second variable transmission circuit (2124Y2), and a voltage comparison / selection circuit (21243). ) And a control circuit (21245, 21246).

  The voltage comparison / selection circuit (21243) compares the voltage of the first input terminal (T1) and the voltage of the second input terminal (T2) and selects a high voltage, so that the high voltage is power-on reset from the output terminal. The operation voltage supplied to the circuit (21244) and the input voltage detection circuit (21248) is output (see FIG. 7).

  At the end of the power-on reset operation of the power-on reset circuit (21244), the input voltage detection circuit (21248) detects the supply of the first or second power supply voltage to either the first or second supply terminal. In the first case, the control circuit path (21245, 21246) responding to the detection controls the power switch corresponding to the supply terminal from which the supply is detected among the first and second power switches to be turned on. .

  In the first case, the control circuit sets the signal transmission amount of the variable transmission circuit corresponding to the supply terminal detected to be supplied from among the first variable transmission circuit and the second variable transmission circuit to the supply terminal where supply is not detected. Set larger than the signal transmission amount of the corresponding variable transmission circuit.

  When the power-on reset circuit (21244) ends the power-on reset operation, the input voltage detection circuit (21248) detects the supply of both the first and second power supply voltages to both the first and second supply terminals. In the case of 2, the control circuit responding to the detection controls the power switch having the higher priority order set in advance among the first and second power switches to the ON state.

  In the second case, the control circuit corresponds to a power switch having a high priority order among the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. Is set larger than the signal transmission amount of the variable transmission circuit that does not correspond to the power switch having a high priority order.

  After the power switch having a high priority order is controlled to be in the ON state, the input voltage detection circuit (21248) supplies the power supply voltage supplied to the power switch having the high priority order among the first and second power switches. This is to detect a power outage.

  In response to the detection result of the power failure by the input voltage detection circuit, the control circuit controls the power switch having a low priority order set in advance among the first and second power switches to an ON state. .

  In response to the detection result of the power failure by the input voltage detection circuit, the control circuit has a power supply having a low priority order among the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. The signal transmission amount of the variable transmission circuit corresponding to the switch is set larger than the signal transmission amount of the variable transmission circuit corresponding to the power switch having a high priority order (see FIGS. 9 and 10).

  The following is a brief description of an effect obtained by the typical embodiment of the embodiments disclosed in the present application.

  That is, according to this semiconductor integrated circuit (212), the control information of the control circuit is lost due to the re-execution of the power-on reset operation when the automatic selection for re-selecting the power source to be used is selected from a plurality of power sources in response to a power failure. Can be eliminated.

FIG. 1 is a diagram showing a configuration of a multi-function mobile phone equipped with a semiconductor integrated circuit 212 for battery charge control according to the first embodiment. FIG. 2 is a diagram showing a configuration of the semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG. FIG. 3 is a diagram showing functions of external terminals of the semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG. FIG. 4 is a diagram showing a configuration of an input voltage selection circuit 2124 for selecting an operation mode at the start-up of the semiconductor integrated circuit 212 examined by the inventor prior to the present invention as a comparative reference example of the present invention. FIG. 5 is a diagram showing waveforms of respective parts of the input voltage selection circuit 2124 for explaining the operation of the input voltage selection circuit 2124 according to the comparative reference example of the present invention shown in FIG. FIG. 6 is a diagram showing waveforms of respective parts of the input voltage selection circuit 2124 for explaining another operation of the input voltage selection circuit 2124 according to the comparative reference example of the present invention shown in FIG. FIG. 7 is a diagram showing a configuration of an input voltage selection circuit 2124 for selecting an operation mode at the time of activation of the semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG. FIG. 8 is a diagram showing a configuration of first variable transmission circuit 2124Y1 and second variable transmission circuit 2124Y2 of variable transmission circuit 2124Y included in input voltage selection circuit 2124 according to the first embodiment shown in FIG. FIG. 9 is a diagram showing waveforms of respective parts of the input voltage selection circuit 2124 for explaining the operation of the input voltage selection circuit 2124 according to the first embodiment shown in FIG. FIG. 10 is a diagram showing waveforms of respective parts of the input voltage selection circuit 2124 for explaining another operation of the input voltage selection circuit 2124 according to the first embodiment shown in FIG.

1. First, an outline of a typical embodiment disclosed in the present application will be described. The reference numerals of the drawings referred to in parentheses in the outline description of the representative embodiment merely exemplify what is included in the concept of the component to which the reference numeral is attached.

  [1] A semiconductor integrated circuit (212) according to a typical embodiment includes a first supply terminal (T1) capable of supplying a first power supply voltage and a second supply capable of supplying a second power supply voltage. A terminal (T2), an input voltage selection circuit (2124) connected to the first supply terminal and the second supply terminal, a first power switch (SW1, SW2), a second power switch (SW3), (See FIG. 2).

  The input voltage selection circuit (2124) includes a power-on reset circuit (21244), an input voltage detection circuit (21248), a first variable transmission circuit (2124Y1), a second variable transmission circuit (2124Y2), and a voltage comparison / selection circuit ( 21243) and control circuits (21245, 21246).

  The input terminal of the first variable transmission circuit (2124Y1) and the input terminal of the second variable transmission circuit (2124Y2) are respectively connected to the first supply terminal (T1) and the second supply terminal (T2). Connected.

  The voltage comparison / selection circuit (21243) has a first input terminal (Node1), a second input terminal (Node2), and an output terminal, and the first input terminal (Node1) is the first variable transmission circuit ( 2124Y1) and the second input terminal (Node2) is connected to the output terminal of the second variable transmission circuit (2124Y2).

Operating voltages (Vcc, AV _DD , DV _DD ) supplied to the power-on reset circuit and the input voltage detection circuit are generated from the output terminal of the voltage comparison / selection circuit (21243).

  The voltage comparison / selection circuit compares the voltage of the first input terminal and the voltage of the second input terminal to select a high voltage, and thereby selects the high voltage from the output terminal to the power-on reset circuit and the input. The operation voltage supplied to the voltage detection circuit is output (see FIG. 7).

  The first input voltage detection circuit detects the supply of either the first or second power supply voltage to the first or second supply terminal at the end of the power-on reset operation of the power-on reset circuit. In this case, the control circuit responding to the detection controls to turn on the power switch corresponding to the supply terminal from which the supply is detected among the first and second power switches.

  In the first case, the control circuit detects the signal transmission amount of the variable transmission circuit corresponding to the supply terminal from which the supply is detected among the first variable transmission circuit and the second variable transmission circuit. It is set to be larger than the signal transmission amount of the variable transmission circuit corresponding to the supply terminal that is not set.

  The input voltage detection circuit detects the supply of both the first and second power supply voltages to both the first and second supply terminals at the end of the power-on reset operation of the power-on reset circuit. In this case, the control circuit responding to the detection controls the power switch having a higher priority order set in advance among the first and second power switches to the ON state.

  In the second case, the control circuit includes the power supply having the higher priority order among the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. The signal transmission amount of the variable transmission circuit corresponding to the switch is set to be larger than the signal transmission amount of the variable transmission circuit not corresponding to the power switch having the high priority order.

  After the power switch having the higher priority order is controlled to be in the ON state, the input voltage detection circuit (21248) is configured to supply the power source having the higher priority order among the first and second power switches. It detects a power failure in the power supply voltage supplied to the switch.

  In response to the detection result of the power failure by the input voltage detection circuit, the control circuit has a power switch having a low priority order set in advance among the first power switch and the second power switch. To turn on.

  In response to the detection result of the power failure by the input voltage detection circuit, the control circuit includes the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. The signal transmission amount of the variable transmission circuit corresponding to the power switch having the low priority order is set larger than the signal transmission amount of the variable transmission circuit corresponding to the power switch having the high priority order (FIGS. 9 and 9). 10).

  According to the semiconductor integrated circuit (212) of the above-described embodiment, control information of the control circuit by re-execution of the power-on reset operation when performing automatic selection for re-selecting the power source to be used from a plurality of power sources in response to a power failure Can be eliminated.

  The semiconductor integrated circuit (212) according to a preferred embodiment supplies the first power supply voltage or the second power supply voltage to the first external load (3) and the second external load (26) as loads, respectively. A first external output terminal (T4) and a second external output terminal (T3).

  The semiconductor integrated circuit (212) further includes an output P-channel MOS transistor (Mp0) connected between the first external output terminal and the second external output terminal.

  When one of the first power switch and the second power switch is controlled to be in an ON state after the power-on reset operation is completed and in response to the detection result of the power failure, the control circuit (21245, 21246) controls the output P-channel MOS transistor (Mp0) to the on state.

  When the output P-channel MOS transistor is controlled to be in the ON state, the first power supply voltage or the second power supply voltage is applied to the second external load from the output P-channel MOS transistor and the second external output terminal. (T3) and can be supplied (see FIGS. 2 and 7).

  In another preferred embodiment, the first external output terminal (T4) is connected to the first power supply voltage or the second voltage to the first external load (3) which is another semiconductor integrated circuit as an active device. The power supply voltage can be supplied.

  The output P-channel MOS transistor and the second external output terminal can supply the first power supply voltage or the second power supply voltage to the second external load (26) which is a battery. It is characterized by being configured (see FIG. 2).

  In still another preferred embodiment, the first variable transmission circuit (2124Y1) and the second variable transmission circuit (2124Y2) are configured by a first variable gain amplifier and a second variable gain amplifier, respectively. (See FIG. 8).

  In a more preferred embodiment, the first variable transmission circuit (2124Y1) and the second variable transmission circuit (2124Y2) are configured by a first variable attenuator and a second variable attenuator, respectively. It is what.

  In another more preferred embodiment, the voltage comparison / selection circuit (21243) includes a first P-channel MOS transistor (Mp3), a second P-channel MOS transistor (Mp4), and a differential amplifier (DA1).

  The source and drain of the first P-channel MOS transistor (Mp3) are connected to the first input terminal (Node1) and the output terminal of the voltage comparison / selection circuit (21243), respectively.

  The source and drain of the second P-channel MOS transistor (Mp4) are connected to the second input terminal (Node2) and the output terminal of the voltage comparison / selection circuit (21243), respectively.

  The other differential input terminal of one differential input terminal of the differential amplifier (DA1) is the first input terminal (Node1) and the second input terminal (Node2) of the voltage comparison / selection circuit (21243). ) And connected.

  The other differential output terminal of the differential amplifier (DA1) is connected to the gate of the first P-channel MOS transistor (Mp3) and the gate of the second P-channel MOS transistor (Mp4), respectively. It is characterized by being connected (see FIG. 7).

  The semiconductor integrated circuit (212) according to still another more preferred embodiment further includes an external interface (2125) for executing serial data communication with an external microcontroller unit (22).

  The control circuit (21245, 21246) of the input voltage selection circuit (2124) controls the operation of the external interface (2125) (see FIGS. 2 and 7).

  In another more preferred embodiment, the control circuit (21245, 21246) is reset by a power-on reset operation of the power-on reset circuit (see FIGS. 2 and 7). .

  A semiconductor integrated circuit (212) according to a specific embodiment includes a step-down DC-DC converter (2121) connected in parallel between the first supply terminal (T1) and the first power switch (SW1, SW2). And a linear regulator (2122).

  The linear regulator operates as a series regulator that operates immediately after power is turned on by the supply of the first power supply voltage to the first supply terminal.

  The step-down DC-DC converter 2121 operates as a switching regulator having higher power efficiency than the linear regulator (see FIG. 2).

  In the most specific embodiment, the first power supply terminal T1 is connected to the power supply voltage of wireless power supply via the first Schottky diode D1 and the AC power supply connection interface via the second Schottky diode D2. The first supply terminal (T1) is configured so that the AC-DC conversion power supply voltage (24) can be supplied.

  The second supply terminal (T2) is configured so that the USB power supply voltage of the USB connection interface (23) can be supplied to the second supply terminal (T2) (see FIG. 2). ).

  [2] A typical embodiment of another aspect is that a first supply terminal (T1) capable of supplying a first power supply voltage and a second supply terminal (T2) capable of supplying a second power supply voltage. ), An input voltage selection circuit (2124) connected to the first supply terminal and the second supply terminal, a first power switch (SW1, SW2), and a second power switch (SW3). This is an operation method of the semiconductor integrated circuit (212) (see FIG. 2).

  The input voltage selection circuit (2124) includes a power-on reset circuit (21244), an input voltage detection circuit (21248), a first variable transmission circuit (2124Y1), a second variable transmission circuit (2124Y2), and a voltage comparison / selection circuit ( 21243) and control circuits (21245, 21246).

  The input terminal of the first variable transmission circuit (2124Y1) and the input terminal of the second variable transmission circuit (2124Y2) are respectively connected to the first supply terminal (T1) and the second supply terminal (T2). Connected.

  The voltage comparison / selection circuit (21243) has a first input terminal (Node1), a second input terminal (Node2), and an output terminal, and the first input terminal (Node1) is the first variable transmission circuit ( 2124Y1) and the second input terminal (Node2) is connected to the output terminal of the second variable transmission circuit (2124Y2).

Operating voltages (Vcc, AV _DD , DV _DD ) supplied to the power-on reset circuit and the input voltage detection circuit are generated from the output terminal of the voltage comparison / selection circuit (21243).

  The voltage comparison / selection circuit compares the voltage of the first input terminal and the voltage of the second input terminal to select a high voltage, and thereby selects the high voltage from the output terminal to the power-on reset circuit and the input. The operation voltage supplied to the voltage detection circuit is output (see FIG. 7).

  The first input voltage detection circuit detects the supply of either the first or second power supply voltage to the first or second supply terminal at the end of the power-on reset operation of the power-on reset circuit. In this case, the control circuit responding to the detection controls to turn on the power switch corresponding to the supply terminal from which the supply is detected among the first and second power switches.

  In the first case, the control circuit detects the signal transmission amount of the variable transmission circuit corresponding to the supply terminal from which the supply is detected among the first variable transmission circuit and the second variable transmission circuit. It is set to be larger than the signal transmission amount of the variable transmission circuit corresponding to the supply terminal that is not set.

  The input voltage detection circuit detects the supply of both the first and second power supply voltages to both the first and second supply terminals at the end of the power-on reset operation of the power-on reset circuit. In this case, the control circuit responding to the detection controls the power switch having a higher priority order set in advance among the first and second power switches to the ON state.

  In the second case, the control circuit includes the power supply having the higher priority order among the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. The signal transmission amount of the variable transmission circuit corresponding to the switch is set to be larger than the signal transmission amount of the variable transmission circuit not corresponding to the power switch having the high priority order.

  After the power switch having the higher priority order is controlled to be in the ON state, the input voltage detection circuit (21248) is configured to supply the power source having the higher priority order among the first and second power switches. It detects a power failure in the power supply voltage supplied to the switch.

  In response to the detection result of the power failure by the input voltage detection circuit, the control circuit has a power switch having a low priority order set in advance among the first power switch and the second power switch. To turn on.

  In response to the detection result of the power failure by the input voltage detection circuit, the control circuit includes the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. The signal transmission amount of the variable transmission circuit corresponding to the power switch having the low priority order is set larger than the signal transmission amount of the variable transmission circuit corresponding to the power switch having the high priority order (FIGS. 9 and 9). 10).

  According to the semiconductor integrated circuit (212) of the above-described embodiment, control information of the control circuit by re-execution of the power-on reset operation when performing automatic selection for re-selecting the power source to be used from a plurality of power sources in response to a power failure Can be eliminated.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<Configuration of multi-function mobile phone>
FIG. 1 is a diagram showing a configuration of a multi-function mobile phone equipped with a semiconductor integrated circuit 212 for battery charge control according to the first embodiment.

  The multi-function mobile phone shown in FIG. 1 includes a power transmission circuit 1, a power reception circuit 2, and a power reception side system 3. In particular, in the multi-function mobile phone shown in FIG. 1, the RF signal from the power transmission side antenna coil 13 is received by the reception side antenna coil 25, thereby charging the secondary battery 26 and supplying power to the power receiving side system 3. Executed.

<< Transmission circuit on the transmission side >>
As shown in FIG. 1, AC power is supplied to the power transmission circuit 1 on the transmission side of the wireless power transmission system via the AC adapter 10. The power transmission circuit 1 includes a microcontroller unit (MCU) 11 and a power transmission control circuit 12, and the microcontroller unit (MCU) 11 has an authentication processing function 111 and an encryption processing function 112. The power transmission control circuit 12 is rectified. A circuit 121 and an RF driver 122 are included, and the RF driver 122 is connected to the power transmission side antenna coil 13.

  A DC power supply voltage generated by rectifying and smoothing the AC power supplied via the AC adapter 10 by the rectifier circuit 121 is supplied to the microcontroller unit (MCU) 11 and the RF driver 122 of the power transmission circuit 1. Is done. The authentication processing function 111 and the encryption processing function 112 of the microcontroller unit (MCU) 11 of the power transmission circuit 1 determine whether or not the user of the multi-function mobile phone that is the power receiving circuit 2 has a right to use. Mutual authentication processing and encryption processing for preventing tampering of communication data are executed. That is, the microcontroller unit (MCU) 11 of the power transmission circuit 1 generates an encryption key related to a communication protocol between the authentication processing function 221 and the encryption processing function 222 of the microcontroller unit (MCU) 22 included in the power receiving circuit 2. Key management operations related to holding, updating, and deletion are executed.

  As a result, when it is determined by the microcontroller unit (MCU) 11 of the power transmission circuit 1 that the user of the multi-function mobile phone that is the power receiving circuit 2 is a valid user, the RF driver 122 performs an RF (not shown). An RF drive signal supplied to the power transmission side antenna coil 13 is generated in response to the RF oscillation output signal generated from the oscillator. Further, communication data of authentication processing and encryption processing from the microcontroller unit (MCU) 11 of the power transmission circuit 1 is supplied to the power reception circuit 2 via the RF driver 122, the power transmission side antenna coil 13, and the power reception side antenna coil 25. The

<< Receiving circuit on the receiving side >>
As shown in FIG. 1, the power reception circuit 2 on the reception side of the wireless power transmission system includes a power reception control circuit 21 and a microcontroller unit (MCU) 22, and the microcontroller unit (MCU) 22 includes an authentication processing function 221. The power reception control circuit 21 includes an encryption processing function 222, and includes a rectification circuit 211 and a semiconductor integrated circuit 212 for battery charge control.

  In the wireless power transmission system shown in FIG. 1, communication according to the communication protocol described above is first performed between the microcontroller unit (MCU) 11 of the power transmission circuit 1 and the microcontroller unit (MCU) 22 of the power reception circuit 2. This is executed via the power transmission side antenna coil 13 and the power reception side antenna coil 25. For this communication, the power receiving circuit 2 enables serial communication and power supply between the power receiving control circuit 21 and the microcontroller unit (MCU) 22. When it is determined by the microcontroller unit (MCU) 11 of the power transmission circuit 1 that the user of the multi-function mobile phone that is the power reception circuit 2 is a valid user, the RF drive signal generated from the RF driver 122 Is supplied to the power reception circuit 2 via the power transmission side antenna coil 13 and the power reception side antenna coil 25.

  A DC power supply voltage generated by rectifying and smoothing the RF drive signal supplied via the power transmission side antenna coil 13 and the power reception side antenna coil 25 by the rectification circuit 211 is converted into a semiconductor integrated circuit 212 and a microcontroller unit ( MCU) 22. The DC power supply voltage supplied from the rectifier circuit 211 to the semiconductor integrated circuit 212 is used for charging the secondary battery 26 and also for supplying power to the power receiving side system 3.

  When the receiving side of the wireless power transmission system is a multi-function mobile phone, the power receiving side system 3 includes an application processor, baseband processor, liquid crystal display driver IC, RF signal processing semiconductor integrated circuit (RFIC), main memory, flash memory, etc. Non-volatile memory and the like.

  Further, when the receiving side of the wireless power transmission system is a portable personal computer such as a tablet PC, the power receiving side system 3 further includes a central processing unit (CPU) and a flash memory storage having a large-scale storage capacity replacing a hard disk. It is a waste.

  In addition to the DC power supply voltage generated by the rectifier circuit 211, the semiconductor integrated circuit 212 for battery charge control and system power supply includes the USB power supply voltage from the USB connection interface 23 and the AC power supply from the AC power supply connection interface 24. An AC-DC conversion power supply voltage generated by rectification and smoothing of the power supply voltage can be supplied. Accordingly, the semiconductor integrated circuit 212 for battery charge control and system power supply includes a plurality of DC power supply voltages of the rectifier circuit 211, USB power supply voltage of the USB connection interface 23, and AC-DC conversion power supply voltage of the AC power supply connection interface 24. It has a function of automatically selecting a power supply voltage for battery charge control and system power supply from the power supply voltage. USB is an abbreviation for Universal Serial Bus.

<Structure of semiconductor integrated circuit for battery charge control>
FIG. 2 is a diagram showing a configuration of the semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG.

  As shown in FIG. 2, a semiconductor integrated circuit 212 for battery charge control and system power supply includes a step-down DC-DC converter 2121, a linear regulator 2122, a USB type detection circuit 2123, an input voltage selection circuit 2124, and an external interface 2125. And a built-in regulator 2126 and a gate drive control circuit 2127. Further, the semiconductor integrated circuit 212 for battery charge control and system power supply includes a P-channel MOS transistor Mp0 and switches SW1, SW2, SW3, SW4.

  The supply terminal T1 of the first input voltage 1 has a power supply voltage for wireless power feeding of the power transmission circuit 1 via the first Schottky diode D1 and an AC-DC conversion power source of the AC power connection interface 24 via the second Schottky diode D2. The USB power supply voltage of the USB connection interface 23 is supplied to the supply terminal T2 for the second input voltage 2. The Schottky diodes D1 and D2 function as a backflow prevention element between the power supply voltage of the wireless power feeding of the power transmission circuit 1 and the AC-DC conversion power supply voltage of the AC power connection interface 24, but are lower than the PN junction diode. It functions as a voltage transmission element that transmits a power supply voltage with a forward voltage. The power supply voltage of the wireless power feeding of the power transmission circuit 1 is 5.5 to 20 volts, the AC-DC conversion power supply voltage of the AC power connection interface 24 is approximately 7 volts, and the USB connection interface 23 The USB power supply voltage is 5 volts.

  The step-down DC-DC converter 2121 is connected to an inductor L1 and a capacitor C1 via external terminals DDOUT1 (T5) and DDOUT2 (T6). Therefore, the step-down DC-DC converter 2121 starts up more slowly when the power is turned on than the linear regulator 2122, but operates as a switching regulator having higher power efficiency than the linear regulator 2122. On the other hand, the linear regulator 2122 operates as a series regulator that operates immediately after power-on.

  That is, the step-down DC-DC converter 2121 and the linear regulator 2122 are generated from the power supply voltage of the power transmission circuit 1 of 5.5 to 20 volts or the AC-DC conversion power supply voltage of the AC power connection interface 24 of approximately 7 volts. Generate a system supply voltage of 3.5 to 5 volts. Accordingly, the 5 volt system supply voltage from the step-down DC-DC converter 2121 and the linear regulator 2122 is supplied to the power receiving side system 3 via the switches SW2 and SW4 and the external terminal SYS (T4), while 5 volt. The USB power supply voltage of the USB connection interface 23 is supplied to the power receiving system 3 via the switch SW3 and the external terminal SYS (T4).

  The current supply capability of the USB interface 23 varies depending on the type of the USB host that performs data communication, the USB hub, or the USB charger that does not perform data communication. Therefore, the current supply capability of these USB devices can be detected by a method described in, for example, the Battery Charging Specification provided by USB Implementers Forum, Inc., specifically, differential data signal terminals D + and D−. It is possible to detect by detecting.

  When the USB interface 23 is connected, the USB type detection circuit 2123 detects the bus voltage and the differential data signal terminals D + and D− to detect the current capability that can be supplied. That is, the USB type detection circuit 2123 executes current limiting so that the current exceeding the supply current capability is not supplied to the external terminal SYS (T4), and the switch SW3 has this current limiting function.

  The input voltage selection circuit 2124 executes the voltage detection of the supply terminal T1 of the first input voltage 1 and the voltage detection of the supply terminal of the supply terminal T2 of the second input voltage 2 in order to select the operation mode at the time of startup. On / off control of the switches SW1, SW2, SW3, and SW4 and control of the step-down DC-DC converter 2121, the built-in regulator 2126, and the gate drive control circuit 2127 are executed. Further, the input voltage selection circuit 2124 executes control of the USB type detection circuit 2123 and transmits the USB type detection data from the USB type detection circuit 2123 to the microcontroller unit (MCU) 22 and the power receiving side system 3 via the external interface 2125. It has a function to supply.

  Therefore, the external interface 2125 performs bidirectional communication of clock and serial data with the power receiving system 3 and the microcontroller unit (MCU) 22.

The built-in regulator 2126 is supplied with the power supply voltage for wireless power supply of the power transmission circuit 1 or the AC-DC conversion power supply voltage of the AC power connection interface 24 via the step-down DC-DC converter 2121 or the linear regulator 2122, or the USB The USB power supply voltage of the connection interface 23 is supplied. As a result, an operating voltage V _DD 18 of 1.8 volts and an operating voltage V _DD 30 of 3.0 volts are generated from the built-in regulator 2126 and supplied to the microcontroller unit (MCU) 22.

  The P-channel MOS transistor Mp0 is controlled to be turned on by the input voltage selection circuit 2124 and the gate drive control circuit 2127, so that the system supply voltage of 3.5 to 5 volts of the external terminal SYS (T4) is supplied to the external terminal BAT. By supplying the secondary battery 26 via (T3), the secondary battery 26 is charged. For example, the secondary battery 26 is a lithium ion battery built in a multifunctional mobile phone or the like, and its charging current is a relatively large current of about 0.5 A to 1.0.

  Further, the gate drive control circuit 2127 outputs an output signal for driving the gate of the P-channel MOS transistor Mp0 so that the P-channel MOS transistor Mp0 conducts bidirectionally between the external terminal SYS (T4) and the external terminal BAT (T3). Is generated. Accordingly, during the period in which the secondary battery 26 is charged, the charging current of the secondary battery 26 flows from the external terminal SYS (T4) to the external terminal BAT (T3). During the battery operation period, the discharge current of the secondary battery 26 flows from the external terminal BAT (T3) to the external terminal SYS (T4). Further, the gate drive control circuit 2127 has a function of preventing overcharge and overdischarge by executing current control of the charge current and the discharge current between the charging operation and the discharging operation of the secondary battery 26. It is.

<External terminal function of semiconductor integrated circuit>
FIG. 3 is a diagram showing functions of external terminals of the semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG.

  As shown in FIG. 3, the external supply terminal of the first input voltage 1 is connected to the power supply voltage of the wireless power feeding of the power transmission circuit 1 or the AC power connection interface 24 via the first Schottky diode D1 or the second Schottky diode D2. It has a function of supplying an AC-DC conversion power supply voltage.

  Further, the external supply terminal of the second input voltage 2 has a function of supplying the USB power supply voltage of the USB connection interface 23.

  The external supply terminal of the differential data signal D + has a function of supplying the non-inverted input signal D + of the differential data of the USB connection interface 23.

  Further, the external supply terminal of the differential data signal D− has a function of supplying the inverted input signal D− of the differential data of the USB connection interface 23.

  The external input / output terminal of the clock has a function of performing bidirectional communication of the clock of the external interface 2125.

  Further, the serial data external input / output terminal has a function of executing serial data bidirectional communication of the external interface 2125.

  The external terminal DDOUT1 has a function of outputting a switching output signal by a switching regulator operation in the step-down DC-DC converter 2121.

  Further, the external terminal DDOUT2 has a function of outputting the output voltage of the step-down DC-DC converter 2121 that has passed through a low-pass filter composed of an inductor L1 and a capacitor C1.

  The external terminal SYS has a function of outputting a power supply voltage to the power receiving side system 3.

  The external terminal BAT has a function of connecting the secondary battery 26.

The external terminal V _DD 18 has a function of outputting an operating voltage V _DD 18 of 1.8 volts to the microcontroller unit (MCU) 22.

The external terminal V _DD 30 has a function of outputting an operating voltage V _DD 30 of 3.0 volts to the microcontroller unit (MCU) 22.

<< Configuration of Input Voltage Detection Circuit According to Comparative Reference Example of the Present Invention >>
FIG. 4 is a diagram showing a configuration of an input voltage selection circuit 2124 for selecting an operation mode at the start-up of the semiconductor integrated circuit 212 examined by the inventor prior to the present invention as a comparative reference example of the present invention.

  As shown in FIG. 4, the input voltage selection circuit 2124 of the comparative reference example of the present invention includes a linear regulator 21241, an input voltage selection switch 21242, a first reference voltage generation circuit Ref_Gen1, a first buffer circuit BA1, and a second buffer circuit. A BA2, a power-on reset circuit 21244, and a power-on reset auxiliary circuit 2124 are included. Further, the input voltage selection circuit 2124 includes a control logic circuit 21245, an input voltage selection switch control logic circuit 21246, a clock generation circuit 21247, an input voltage detection circuit 21248, and a gate drive circuit 21249.

  As shown in the upper left part of FIG. 4, the power supply voltage of the wireless power feeding of the power transmission circuit 1 and the AC-DC conversion power supply voltage of the AC power connection interface 24 are supplied to the supply terminal T1 of the first input voltage 1, and the second The USB power supply voltage of the USB connection interface 23 is supplied to the supply terminal T2 for the input voltage 2.

  The power supply voltage or the AC-DC conversion power supply voltage of the wireless power supply having the voltage of 5.5 to 20 volts at the supply terminal T1 of the first input voltage 1 is converted into the output power supply voltage Vout of about 5 volts by the linear regulator 21241. The output power supply voltage Vout of about 5 volts is supplied to the source of the P-channel MOS transistor Mp1 of the input voltage selection switch 21242 and the gate drive circuit 21249. The source and back gate of the P channel MOS transistor Mp1 are short-circuited, the cathode of the body diode d1 is connected to the back gate of the P channel MOS transistor Mp1, and the anode of the body diode d1 is connected to the drain of the P channel MOS transistor Mp1. Is connected.

  The USB power supply voltage of the USB connection interface 23 having a voltage of 5 volts supplied to the supply terminal T2 of the second input voltage 2 is supplied to the source of the P-channel MOS transistor Mp2 of the input voltage selection switch 21242. The source and back gate of the P channel MOS transistor Mp2 are short-circuited, the cathode of the body diode d2 is connected to the back gate of the P channel MOS transistor Mp2, and the body diode d2 is connected to the drain of the P channel MOS transistor Mp2. The anode is connected.

  The gate of the P-channel MOS transistor Mp1 of the input voltage selection switch 21242 is driven by the first gate drive output signal Mp1_G of the gate drive circuit 21249, and the gate of the P-channel MOS transistor Mp2 of the input voltage selection switch 21242 is the first gate drive circuit 21249. It is driven by a two-gate drive output signal Mp2_G. Since both the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G of the gate drive circuit 21249 are set to the low level in the power-on reset period described in detail below when the power is turned on, the input voltage selection switch 21242 is set. Both P channel MOS transistor Mp1 and P channel MOS transistor Mp2 are controlled to be in an on state.

  The voltage comparison / selection circuit 21243 includes the P-channel MOS transistor Mp3, the P-channel MOS transistor Mp4, and the differential amplifier DA1, thereby comparing the voltage of the first node Node1 with the voltage of the second node Node2. A voltage higher than the voltage of the first node Node1 and the voltage of the second node Node2 is selected and generated as the output voltage Vcc. The current passing direction of the body diode d3 of the P-channel MOS transistor Mp3 and the current passing direction of the body diode d4 of the P-channel MOS transistor Mp4 are between the supply terminal T1 for the first input voltage 1 and the supply terminal T2 for the second input voltage 2. The reverse current is set so as not to pass through.

  That is, when the supply terminal T1 of the first input voltage 1 is set to a high voltage level of 5.5 to 20 volts and the supply terminal T2 of the second input voltage 2 is set to a low voltage of zero volts, 2 There is a possibility that a reverse current flows from the common connection node of the P channel MOS transistors Mp3 and Mp4 in the direction of the supply terminal T2 of the second input voltage 2. However, the current passage direction of the body diode d4 connected to the P-channel MOS transistor Mp4 shown in the voltage comparison / selection circuit 21243 in FIG. 4 prevents the passage of the reverse current.

  Further, when the supply terminal T1 of the first input voltage 1 is set to a low voltage level of zero volts and the supply terminal T2 of the second input voltage 2 is set to a high voltage of approximately 5 volts, two P-channel MOSs There is a possibility that a reverse current flows from the common connection node of the transistors Mp3 and Mp4 to the supply terminal T1 of the first input voltage 1. However, the current passage direction of the body diode d3 connected to the P-channel MOS transistor Mp3 shown in the voltage comparison / selection circuit 21243 in FIG. 4 prevents the passage of the reverse current.

  Note that the two types of backflow currents described above do not flow through the sources and drains of the P-channel MOS transistors Mp3 and Mp4 in the following description, and the supply terminal T1 for the first input voltage 1 and the supply terminal T2 for the second input voltage 2 This is a definition in a state in which only one of these is set to a high voltage and the other is set to a low voltage.

  That is, the first node Node1 is connected to the source of the P channel MOS transistor Mp3, the inverting input terminal of the differential amplifier DA1, and the anode of the body diode d3, and the drain and back gate of the P channel MOS transistor Mp3 are short-circuited. The cathode of body diode d3 is connected to the short-circuited drain and back gate of P-channel MOS transistor Mp3. The second node Node2 is connected to the source of the P channel MOS transistor Mp4, the non-inverting input terminal + of the differential amplifier DA1, and the anode of the body diode d4, so that the drain and back gate of the P channel MOS transistor Mp3 are short-circuited. The cathode of body diode d4 is connected to the shorted drain and back gate of P-channel MOS transistor Mp4. The non-inverting output terminal + and the inverting output terminal − of the differential amplifier DA1 are connected to the gate of the P channel MOS transistor Mp3 and the gate of the P channel MOS transistor Mp4, respectively, and the drain of the P channel MOS transistor Mp3 and the P channel MOS transistor. The drain of Mp4 is commonly connected to generate an output voltage Vcc.

  The output voltage Vcc of the voltage comparison / selection circuit 21243 is supplied as an operation power supply voltage to the differential amplifier DA1, the first reference voltage generation circuit Ref_Gen1, the first buffer circuit BA1, and the second buffer circuit BA2.

The first reference voltage generating circuit Ref_Gen1, by operating the output voltage Vcc from the voltage comparison and selection circuit 21243 as an operating power supply voltage, generates a reference voltage _{V REF.}

The first buffer circuit BA1 and the second buffer circuit BA2 are responsive to the reference voltage V _REF generated from the first reference voltage generation circuit Ref_Gen1, and the analog circuit power supply voltage AV _DD proportional to the voltage level of the reference voltage V _REF A digital circuit power supply voltage DV _DD is generated.

The power-on reset circuit 21244 includes a second reference voltage generation circuit Ref_Gen2, a differential amplifier DA2, a resistor Rp, a capacitor Cp, and a third buffer circuit BA3. The second reference voltage generation circuit Ref_Gen2 of the power-on reset circuit 21244 and the differential amplifier DA2 are supplied with the digital circuit power supply voltage DV _DD generated by the second buffer circuit BA2, and the non-inverting input terminal + of the differential amplifier DA2 The digital circuit power supply voltage DV _DD and the reference voltage V _BB generated from the second reference voltage generation circuit Ref_Gen 2 are supplied to the inverting input terminal −.

  The output voltage of the differential amplifier DA2 of the power-on reset circuit 21244 is supplied to one end of the resistor Rp, and the other end of the resistor Rp is connected to one end of the capacitor Cp and the input terminal of the third buffer circuit BA3. Is connected to the ground potential. The low-level power-on reset signal POR generated from the third buffer circuit BA3 during the power-on reset period is the inverted reset input terminal / Reset of the control logic circuit 21245 and the inverted reset input terminal / of the input voltage selection switch control logic circuit 21246. Supplied to Reset.

The clock signal generated from the clock generation circuit 21247 to which the output voltage Vcc from the voltage comparison / selection circuit 21243 and the digital circuit power supply voltage DV _DD from the second buffer circuit BA2 are supplied is the clock input terminal of the control logic circuit 21245. CLK and the input voltage selection switch control logic circuit 21246 are supplied to the clock input terminal CLK.

A control logic circuit 21245 of the input voltage selection circuit 2124 controls the overall operation of the semiconductor integrated circuit 212 shown in FIG. That is, the analog circuit 2128 connected to the input voltage selection circuit 2124 shown in FIG. 4 includes the step-down DC-DC converter 2121, the linear regulator 2122, the USB type detection circuit 2123, and the built-in regulator of the semiconductor integrated circuit 212 shown in FIG. An analog circuit of 2126 and a gate drive control circuit 2127 is included. Therefore, the operations of these analog circuits are all controlled by the control logic circuit 21245 of the input voltage selection circuit 2124 shown in FIG. The analog circuit 2128 is supplied with the output voltage Vcc from the voltage comparison / selection circuit 21243 and the analog circuit power supply voltage AV _DD from the first buffer circuit BA1.

  Further, the operation of the input voltage selection switch control logic circuit 21246 is similarly controlled by the control logic circuit 21245 of the input voltage selection circuit 2124 shown in FIG.

  Furthermore, the operations of the switches SW1, SW2, SW3, SW4, the built-in regulator 2126, and the gate drive control circuit 2127 shown in FIG. 2 are similarly controlled by the control logic circuit 21245 of the input voltage selection circuit 2124 shown in FIG. The

The input voltage detection circuit 21248 is supplied with the output voltage Vcc from the voltage comparison / selection circuit 21243 and the analog circuit power supply voltage AV _DD from the first buffer circuit BA1. After the elapse of the power-on reset period, the input voltage detection circuit 21248 has the power level of the power supply voltage of the supply terminal T1 of the first input voltage 1 or the power supply voltage of the AC-DC conversion and the USB of the supply terminal T2 of the second input voltage 2. The voltage level of the power supply voltage is detected. As a result, the 2-bit voltage detection output signals Vdet1 and Vdet2 from the input voltage detection circuit 21248 are supplied to the control logic circuit 21245 and the input voltage selection switch control logic circuit 21246. That is, the voltage detection output signal Vdet1 is obtained by detecting whether or not the power supply voltage for wireless power feeding or AC-DC conversion is supplied to the supply terminal T1 of the first input voltage 1, and the voltage detection output signal Vdet2 is the second input voltage. In this case, it is detected whether or not the USB power supply voltage is supplied to the second supply terminal T2.

  After the power-on reset period, the first gate drive output signal Mp1_G and the second gate drive of the gate drive circuit 21249 are output by the output signal of the input voltage selection switch control logic circuit 21246 in response to the 2-bit voltage detection output signals Vdet1 and Vdet2. One and the other of the output signal Mp2_G are set to a low level and a high level, respectively, and automatic selection of the power source to be used is executed.

  The supply of the power supply voltage to the supply terminal T1 of the first input voltage 1 is detected by the high level voltage detection output signal Vdet1, and the power supply voltage to the supply terminal T2 of the second input voltage 2 is detected by the low level voltage detection output signal Vdet2. Assume that a non-supply of is detected. In this case, in response to the voltage detection output signals Vdet1 and Vdet2 having different levels, the control logic circuit 21245 controls the switch SW2 in the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. On the other hand, the switch SW3 is controlled to be turned off. As a result, the supply voltage from the supply terminal T1 of the first input voltage 1 is used for charging the secondary battery 26 via the step-down DC-DC converter 2121, the switch SW2, and the P-channel MOS transistor Mp0, and also on the power receiving side. Used to supply power to the system 3. Furthermore, in this case, the gate drive circuit 21249 sets the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G to a low level and a high level, respectively. Further, the voltage comparison / selection circuit 21243 detects that the voltage of the first node Node1 is higher than the second node Node2, and the supply voltage of the supply terminal T1 of the first input voltage 1 of the first node Node1 is voltage comparison / selection. It is generated as the output voltage Vcc of the circuit 21243.

  The low-level voltage detection output signal Vdet1 detects the non-supply of the power supply voltage to the supply terminal T1 of the first input voltage 1, and the high-level voltage detection output signal Vdet2 detects the power supply to the supply terminal T2 of the second input voltage 2 Assume that a voltage supply is detected. In this case, in response to the voltage detection output signals Vdet1 and Vdet2 having different levels, the control logic circuit 21245 controls the switch SW2 inside the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. On the other hand, the switch SW3 is controlled to be on. As a result, the supply voltage from the supply terminal T2 of the second input voltage 2 is used for charging the secondary battery 26 via the switch SW3 and the P-channel MOS transistor Mp0, and for supplying power to the power receiving system 3. used. Furthermore, in this case, the gate drive circuit 21249 sets the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G to a high level and a low level, respectively. Further, the voltage comparison / selection circuit 21243 detects that the voltage of the second node Node2 is higher than the first node Node1, and the supply voltage of the supply terminal T2 of the second input voltage 2 of the second node Node2 is voltage comparison / selection. It is generated as the output voltage Vcc of the circuit 21243.

  The power supply voltage for the wireless power feeding or AC-DC conversion to the supply terminal T1 of the first input voltage 1 and the supply terminal T2 of the second input voltage 2 by the 2-bit voltage detection output signals Vdet1 and Vdet2 of the input voltage detection circuit 21248 Assume that the USB power supply voltage is simultaneously detected. In this case, the control logic circuit 21245 adjusts the voltage level of the output power supply voltage Vout of approximately 5 volts of the linear regulator 21241 in response to the voltage detection output signals Vdet1 and Vdet2 which are both at the high level.

  That is, when the supply voltage of the supply terminal T1 of the first input voltage 1 detected simultaneously has priority over the supply voltage of the supply terminal T2 of the second input voltage 2, the output power supply of about 5 volts of the linear regulator 21241. The voltage Vout is set to, for example, 5.2 volts, which is higher than the USB power supply voltage of the USB connection interface 23 having a voltage of 5 volts supplied to the supply terminal T2 of the second input voltage 2. Further, the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G of the gate drive circuit 21249 controlled by the control logic circuit 21245 are set to a low level and a high level, respectively. As a result, the voltage comparison / selection circuit 21243 detects that the voltage of the first node Node1 is higher than the second node Node2, and the supply voltage of the supply terminal T1 of the first input voltage 1 of the first node Node1 is compared with the voltage. Generated as the output voltage Vcc of the selection circuit 21243 Further, the control logic circuit 21245 controls the switch SW2 in the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 2 to be in an on state, and controls the switch SW3 to be in an off state. As a result, the supply voltage from the supply terminal T1 of the first input voltage 1 is used for charging the secondary battery 26 via the step-down DC-DC converter 2121, the switch SW2, and the P-channel MOS transistor Mp0, and also on the power receiving side. Used to supply power to the system 3.

  On the other hand, when the supply voltage of the supply terminal T2 of the second input voltage 2 is prioritized over the supply voltage of the supply terminal T1 of the first input voltage 1 detected simultaneously, the linear regulator 21241 has approximately 5 volts. The output power supply voltage Vout is set to, for example, 4.8 volts, which is lower than the USB power supply voltage of the USB connection interface 23 having a voltage of 5 volts supplied to the supply terminal T2 of the second input voltage 2. Further, the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G of the gate drive circuit 21249 controlled by the control logic circuit 21245 are set to a high level and a low level, respectively. As a result, the voltage comparison / selection circuit 21243 detects that the voltage of the second node Node2 is higher than the first node Node1, and the supply voltage of the supply terminal T2 of the second input voltage 2 of the second node Node2 is compared with the voltage. Generated as the output voltage Vcc of the selection circuit 21243 Further, the control logic circuit 21245 controls the switch SW2 inside the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 2 to the off state, and controls the switch SW3 to the on state. As a result, the supply voltage from the supply terminal T2 of the second input voltage 2 is used for charging the secondary battery 26 via the switch SW3 and the P-channel MOS transistor Mp0, and for supplying power to the power receiving system 3. used.

  On the other hand, before the elapse of the power-on reset period, the first gate drive output signal Mp1_G of the gate drive circuit 21249 and the second output signal of the input voltage selection switch control logic circuit 21246 in response to the low-level power-on reset signal POR. Both the gate drive output signal Mp2_G are set to a low level. As a result, both P channel MOS transistor Mp1 and P channel MOS transistor Mp2 included in input voltage selection switch 21242 are controlled to be in an on state.

  The power-on reset auxiliary circuit 2124X of the input voltage selection circuit 2124 shown in FIG. 4 includes a third reference voltage generation circuit Ref_Gen3, a fourth reference voltage generation circuit Ref_Gen4, two differential amplifiers DA3 and DA4, and two N channels. MOS transistors Mn1 and Mn2 are used.

The power supply voltage at the supply terminal T1 of the first input voltage 1 is supplied to the fourth reference voltage generation circuit Ref_Gen4 of the power-on reset auxiliary circuit 2124X via the linear regulator 21241 and the P-channel MOS transistor Mp1 of the input voltage selection switch 21242. An operating power supply voltage is supplied to the differential amplifier DA4. The power supply voltage at the supply terminal T1 of the first input voltage 1 is a power supply voltage for wireless power feeding from the power transmission circuit 1 or a power supply voltage for AC-DC conversion from the AC power connection interface 24. The fourth reference voltage generation circuit Ref_Gen4 generates the reference voltage by operating with the power supply voltage of the supply terminal T1 of the first input voltage 1 as the operation power supply voltage. The digital circuit power supply voltage DV _DD and the reference voltage generated from the fourth reference voltage generation circuit Ref_Gen4 are respectively supplied to the inverting input terminal − and the non-inverting input terminal + of the differential amplifier DA4, and the output terminal of the differential amplifier DA4. Is supplied to the gate of the N-channel MOS transistor Mn2. The source and drain of the N-channel MOS transistor Mn2 are connected to the ground potential and a common connection node of the resistor Rp and the capacitor Cp of the power-on reset circuit 21244, respectively.

The power supply voltage at the supply terminal T2 for the second input voltage 2 is supplied as the operation power supply voltage to the third reference voltage generation circuit Ref_Gen3 and the differential amplifier DA3 of the power-on reset auxiliary circuit 2124X. The power supply voltage of the supply terminal T2 for the second input voltage 2 is the power supply voltage from the USB connection interface 23. The third reference voltage generation circuit Ref_Gen3 generates the reference voltage by operating with the power supply voltage of the supply terminal T2 of the second input voltage 2 as the operation power supply voltage. The digital circuit power supply voltage DV _DD and the reference voltage generated from the third reference voltage generation circuit Ref_Gen3 are respectively supplied to the inverting input terminal − and the non-inverting input terminal + of the differential amplifier DA3, and the output terminal of the differential amplifier DA4. Is supplied to the gate of the N-channel MOS transistor Mn1. The source and drain of the N-channel MOS transistor Mn1 are connected to the ground potential and the common connection node of the resistor Rp and the capacitor Cp of the power-on reset circuit 21244, respectively.

  In the power-on reset auxiliary circuit 2124X of the input voltage selection circuit 2124 shown in FIG. 4, the third reference voltage generation circuit Ref_Gen3, the differential amplifier DA3, and the N-channel MOS transistor Mn1 are wirelessly fed in accordance with the priority of USB feeding. Detects a wireless power failure when the priority is set high. In the control logic circuit 21245, the priority of wireless power feeding is set higher than the priority of USB power feeding.

  In the power-on reset auxiliary circuit 2124X of the input voltage selection circuit 2124 shown in FIG. 4, the fourth reference voltage generation circuit Ref_Gen4, the differential amplifier DA4, and the N-channel MOS transistor Mn2 are powered by USB in accordance with the priority of wireless power feeding. The power failure of the USB power supply is detected when the priority order of is set high. In the control logic circuit 21245, the USB power feeding priority is set higher than the wireless power feeding priority.

<< Explanation of operation waveforms according to comparative example of the present invention >>
FIG. 5 is a diagram showing waveforms of respective parts of the input voltage selection circuit 2124 for explaining the operation of the input voltage selection circuit 2124 according to the comparative reference example of the present invention shown in FIG.

  As shown in FIG. 5, in the period T1, the power supply voltage of the wireless power feeding of the supply terminal T1 of the first input voltage 1 is first started by the supply of the power supply voltage to the supply terminal T1 of the first input voltage 1. . When the power supply voltage of the wireless power supply reaches the detection threshold voltage, the voltage detection output signal Vdet1 of the input voltage selection circuit 21248 changes from the low level to the high level.

In response to the increase of the wireless power supply voltage, the output voltage Vcc of the voltage comparison / selection circuit 21243 starts to increase. Further, in response to the increase in the output voltage Vcc of the voltage comparison / selection circuit 21243, the increase in the digital circuit power supply voltage DV _DD generated from the second buffer circuit BA2 is started. When the digital circuit power supply voltage _{DV DD} reaches the detection threshold voltage corresponding to the reference voltage _{V BB} of the second reference voltage generating circuit Ref_Gen2, power on the output is at a high level from the low level of the differential amplifier DA2 of the reset circuit 21244 Then, a power-on reset period is started by charging the resistor Rp and the capacitor Cp of the time constant circuit. When the terminal voltage Vc of the capacitor Cp of the time constant circuit reaches the detection threshold voltage corresponding to the threshold voltage of the third buffer circuit BA3, the power-on reset signal POR changes from the low level to the high level, and the control is performed. The power-on reset operation of the logic circuit 21245 and the input voltage selection switch control logic circuit 21246 is finished.

  The input voltage selection circuit 21248 responds to the high level voltage detection output signal Vdet1 and the low level voltage detection output signal Vdet2 of the input voltage selection circuit 21248 in the period T2 by the end of the power-on reset operation. Accordingly, the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G are set to a low level and a high level, respectively, under the control of the input voltage selection switch control logic circuit 21246 and the gate drive circuit 21249. Accordingly, the P-channel MOS transistor Mp1 and the P-channel MOS transistor Mp2 of the input voltage selection switch 21242 are controlled to be in an on state and an off state, respectively, so that USB power feeding is controlled to an off state and wireless power feeding is controlled to an on state. And automatic selection of the power source to be used is executed.

  In this state, by the supply of the power supply voltage at the supply terminal T2 of the second input voltage 2 at the end of the period T2, the increase of the power supply voltage for USB power supply at the supply terminal T2 of the second input voltage 2 is started. As a result, when the increase in the power supply voltage for USB power supply reaches the detection threshold voltage, the voltage detection output signal Vdet2 of the input voltage selection circuit 21248 changes from the low level to the high level.

  At the last timing of the period T2, the input voltage selection circuit 21248 generates both high-level voltage detection output signals Vdet1 and Vdet2. However, since the priority of the wireless power supply is set higher than the priority of the USB power supply in the control logic circuit 21245, the low-level first gate drive output signal Mp1_G is output from the gate drive circuit 21249 at the final timing of the period T2. And a high-level second gate drive output signal Mp2_G is generated. As a result, in the input voltage selection switch 21242, the P-channel MOS transistor Mp1 is maintained in the on state, while the P-channel MOS transistor Mp2 is maintained in the off state. The power supply voltage for power supply is selected as the output voltage Vcc from the voltage comparison / selection circuit 21243.

  However, as shown in FIG. 5, at the switching timing between the period T2 and the period T3, a power failure occurs in the power supply voltage of the wireless power supply of the supply terminal T1 of the first input voltage 1 set in the higher priority order. At the timing immediately after the power failure, the P-channel MOS transistor Mp1 and the P-channel MOS transistor Mp2 of the input voltage selection switch 21242 are set to an on state and an off state, respectively. Therefore, a drop in the power supply voltage of the wireless power supply at the supply terminal T1 of the first input voltage 1 due to the power failure is transmitted to the first node Node1 of the voltage comparison / selection circuit 21243 via the P-channel MOS transistor Mp1 in the on state. It will be a thing. On the other hand, since the second node Node2 of the voltage comparison / selection circuit 21243 is at the ground potential, the voltage comparison / selection circuit 21243 receives the first input transmitted to the first node Node1 which is at a higher level than the second node Node2. A drop in the power supply voltage of the wireless power feeding at the supply terminal T1 of the voltage 1 is output as the output voltage Vcc.

Accordingly, the digital circuit power supply voltage DV _DD of the second buffer circuit BA2 decreases in response to the decrease of the output voltage Vcc of the voltage comparison / selection circuit 21243, so that the terminal of the capacitor Cp of the time constant circuit of the power-on reset circuit 21244 The voltage Vc and the power-on reset signal POR of the third buffer circuit are slightly reduced. As a result, the digital circuit power supply voltage DV _{DD at} the inverting input terminal − of the differential amplifier DA3 of the power-on reset auxiliary circuit 2124X is lower than the reference voltage of the third reference voltage generating circuit Ref_Gen3 supplied to the non-inverting input terminal +. Therefore, the output signal of the differential amplifier DA3 changes from low level to high level.

  Accordingly, since the N-channel MOS transistor Mn1 of the power-on reset auxiliary circuit 2124X changes from the off state to the on-state, the capacitor Cp of the time constant circuit of the power-on reset circuit 21244 is grounded via the N-channel MOS transistor Mn1 in the on state. Discharged. As a result, since the terminal voltage Vc of the capacitor Cp of the time constant circuit of the power-on reset circuit 21244 and the power-on reset signal POR of the third buffer circuit change to the low level which is the ground potential, the low-level power-on reset signal POR Is supplied to the inverting reset input terminal / Reset, the control logic circuit 21245 and the input voltage selection switch control logic circuit 21246 are reset. Accordingly, the power-on reset period is resumed, and both the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G of the gate drive circuit 21249 are low in response to the output signal of the input voltage selection switch control logic circuit 21246. Set to level. As a result, both P-channel MOS transistor Mp1 and P-channel MOS transistor Mp2 included in input voltage selection switch 21242 are controlled to be in an on state.

  As a result, during the power failure period T3 of the wireless power supply, the P-channel MOS transistor Mp2 in which the USB power supply high-level power supply voltage at the supply terminal T2 of the second input voltage 2 is controlled to be turned on by the input voltage selection switch 21242. Is transmitted to the second node Node2 of the voltage comparison / selection circuit 21243. On the other hand, since the first node Node1 of the voltage comparison / selection circuit 21243 is at the ground potential, the voltage comparison / selection circuit 21243 receives the second input transmitted to the second node Node2 that is at a higher level than the first node Node1. The USB power supply high level power supply voltage at the voltage 2 supply terminal T2 is output as the output voltage Vcc.

Accordingly, in response to the high level output voltage Vcc of the voltage comparison / selection circuit 21243, the digital circuit power supply voltage DV _DD of the second buffer circuit BA2 also rises, so that the capacitance Cp of the time constant circuit of the power-on reset circuit 21244 is increased. The terminal voltage Vc increases.

  A power-on reset period is started by charging the resistor Rp and the capacitor Cp of the time constant circuit. When the terminal voltage Vc of the capacitor Cp of the time constant circuit reaches the detection threshold voltage corresponding to the threshold voltage of the third buffer circuit BA3, the power-on reset signal POR changes from the low level to the high level, and the control logic The power-on reset operation of the circuit 21245 and the input voltage selection switch control logic circuit 21246 is terminated.

  The input voltage selection circuit 21248 generates the low-level voltage detection output signal Vdet1 and the high-level voltage detection output signal Vdet2 in the period T4 due to the end of the restarted power-on reset operation. Accordingly, the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G are set to a high level and a low level, respectively, under the control of the input voltage selection switch control logic circuit 21246 and the gate drive circuit 21249. Accordingly, since the P-channel MOS transistor Mp1 and the P-channel MOS transistor Mp2 of the input voltage selection switch 21242 are controlled to be in an off state and an on state, respectively, wireless power feeding is controlled to an off state and USB power feeding is controlled to an on state. Thus, automatic selection is performed in which a power source to be used is selected again from a plurality of power sources in response to a power failure.

  However, in the operation of the input voltage selection circuit 2124 shown in FIG. 5, the control logic circuit 21245 of the input voltage selection circuit 2124 by the low-level power-on reset signal POR due to the restart of the power-on reset period in the power failure period T3 of the wireless power feeding. The input voltage selection switch control logic circuit 21246 is reset. In particular, the control logic circuit 21245 includes the analog circuit 2128 of FIG. 4 (step-down DC-DC converter 2121, linear regulator 2122, USB type detection circuit 2123, built-in regulator 2126, and gate drive control of the semiconductor integrated circuit 212 shown in FIG. The circuit 2127) is controlled. The control logic circuit 21245 also controls the operations of the switches SW1, SW2, SW3, and SW4, the built-in regulator 2126, and the gate drive control circuit 2127 in FIG. 2, while serially communicating with the microcontroller unit (MCU) 22 and the power receiving system 3. It also controls the operation of the external interface 2125 that executes.

  Therefore, resetting the control logic circuit 21245 of the input voltage selection circuit 2124 resets the control information of the various controlled circuits described above, but the initial setting information is restored from a boot program stored in a nonvolatile memory such as a flash memory. Need to load. On the other hand, since the control information that is not backed up in the nonvolatile memory or the like cannot be recovered, the control information can finally be obtained by restarting the operation of various controlled circuits.

<< Other operation waveforms according to comparative example of the present invention >>
FIG. 6 is a diagram showing waveforms of respective parts of the input voltage selection circuit 2124 for explaining another operation of the input voltage selection circuit 2124 according to the comparative reference example of the present invention shown in FIG.

  That is, FIG. 6 shows that the USB power supply priority is set higher than the wireless power supply priority in the control logic circuit 21245 of the input voltage selection circuit 2124 of the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. The waveform of each part of the input voltage selection circuit 2124 at the time of USB power failure is shown.

  As shown in FIG. 6, in the period T1, the supply of the power supply voltage of the USB power supply to the supply terminal T2 of the second input voltage 2 is first started by the supply of the power supply voltage to the supply terminal T2 of the second input voltage 2. . When the USB power supply voltage reaches the detection threshold voltage, the voltage detection output signal Vdet2 of the input voltage selection circuit 21248 changes from the low level to the high level.

In response to the rise of the USB power supply voltage, the output voltage Vcc of the voltage comparison / selection circuit 21243 starts to rise. Further, in response to the increase of the output voltage Vcc of the voltage comparison / selection circuit 21243, the increase of the digital circuit power supply voltage DV _DD generated from the second buffer circuit BA2 is started. When the digital circuit power supply voltage _{DV DD} reaches the detection threshold voltage corresponding to the reference voltage _{V BB} of the second reference voltage generating circuit Ref_Gen2, power on the output is at a high level from the low level of the differential amplifier DA2 of the reset circuit 21244 Then, a power-on reset period is started by charging the resistor Rp and the capacitor Cp of the time constant circuit. When the terminal voltage Vc of the capacitor Cp of the time constant circuit reaches the detection threshold voltage corresponding to the threshold voltage of the third buffer circuit BA3, the power-on reset signal POR changes from the low level to the high level, and the control is performed. The power-on reset operation of the logic circuit 21245 and the input voltage selection switch control logic circuit 21246 is finished.

  The input voltage selection circuit 21248 responds to the low level voltage detection output signal Vdet1 and the high level voltage detection output signal Vdet2 of the input voltage selection circuit 21248 in the period T2 by the end of the power-on reset operation. Accordingly, the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G are set to a high level and a low level, respectively, under the control of the input voltage selection switch control logic circuit 21246 and the gate drive circuit 21249. Accordingly, since the P-channel MOS transistor Mp1 and the P-channel MOS transistor Mp2 of the input voltage selection switch 21242 are controlled to be in an off state and an on state, respectively, wireless power feeding is controlled to an off state and USB power feeding is controlled to an on state. And automatic selection of the power source to be used is executed.

  In this state, by the supply of the power supply voltage of the supply terminal T1 of the first input voltage 1 at the end of the period T2, the increase of the power supply voltage of the wireless power feeding of the supply terminal T1 of the first input voltage 1 is started. As a result, when the increase in the power supply voltage for wireless power feeding reaches the detection threshold voltage, the voltage detection output signal Vdet1 of the input voltage selection circuit 21248 changes from the low level to the high level.

  At the last timing of the period T2, the input voltage selection circuit 21248 generates both high-level voltage detection output signals Vdet1 and Vdet2. However, since the priority of the USB power supply is set higher than the priority of the wireless power supply in the control logic circuit 21245, the first gate drive output signal Mp1_G at the high level from the gate drive circuit 21249 is set at the final timing of the period T2. And a low-level second gate drive output signal Mp2_G is generated. As a result, in the input voltage selection switch 21242, the P-channel MOS transistor Mp2 is maintained in the on state while the P-channel MOS transistor Mp1 is maintained in the off state, so that the USB of the supply terminal T2 for the second input voltage 2 is supplied. The power supply voltage for power supply is selected as the output voltage Vcc from the voltage comparison / selection circuit 21243.

  However, as shown in FIG. 6, at the switching timing between the period T2 and the period T3, a power failure occurs in the power supply voltage of the USB power supply at the supply terminal T1 of the first input voltage 1 set in the higher priority order. At the timing immediately after the power failure, the P-channel MOS transistor Mp1 and the P-channel MOS transistor Mp2 of the input voltage selection switch 21242 are set to an off state and an on state, respectively. Accordingly, a decrease in the USB power supply voltage at the supply terminal T2 of the second input voltage 2 due to a power failure is transmitted to the second node Node2 of the voltage comparison / selection circuit 21243 via the P-channel MOS transistor Mp2 in the on state. It will be a thing. On the other hand, since the first node Node1 of the voltage comparison / selection circuit 21243 is at the ground potential, the voltage comparison / selection circuit 21243 receives the second input transmitted to the second node Node2 that is at a higher level than the first node Node1. A decrease in the USB power supply voltage at the supply terminal T2 of the voltage 2 is output as the output voltage Vcc.

Accordingly, the digital circuit power supply voltage DV _DD of the second buffer circuit BA2 decreases in response to the decrease of the output voltage Vcc of the voltage comparison / selection circuit 21243, so that the terminal of the capacitor Cp of the time constant circuit of the power-on reset circuit 21244 The voltage Vc and the power-on reset signal POR of the third buffer circuit are slightly reduced. As a result, the digital circuit power supply voltage DV _{DD at} the inverting input terminal − of the differential amplifier DA4 of the power-on reset auxiliary circuit 2124X is lower than the reference voltage of the fourth reference voltage generating circuit Ref_Gen4 supplied to the non-inverting input terminal +. Therefore, the output signal of the differential amplifier DA4 changes from low level to high level.

  Accordingly, since the N-channel MOS transistor Mn2 of the power-on reset auxiliary circuit 2124X is changed from the OFF state to the ON state, the capacitance Cp of the time constant circuit of the power-on reset circuit 21244 is grounded via the N-channel MOS transistor Mn2. Discharged. As a result, since the terminal voltage Vc of the capacitor Cp of the time constant circuit of the power-on reset circuit 21244 and the power-on reset signal POR of the third buffer circuit change to the low level which is the ground potential, the low-level power-on reset signal POR Is supplied to the inverting reset input terminal / Reset, the control logic circuit 21245 and the input voltage selection switch control logic circuit 21246 are reset. Accordingly, the power-on reset period is resumed, and both the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G of the gate drive circuit 21249 are low in response to the output signal of the input voltage selection switch control logic circuit 21246. Set to level. As a result, both P-channel MOS transistor Mp1 and P-channel MOS transistor Mp2 included in input voltage selection switch 21242 are controlled to be in an on state.

  Therefore, during the power failure period T3 of the wireless power supply, the high-level power supply voltage of the wireless power supply at the supply terminal T1 of the first input voltage 1 is applied to the P-channel MOS transistor Mp1 controlled by the input voltage selection switch 21242. Then, it is transmitted to the first node Node1 of the voltage comparison / selection circuit 21243. On the other hand, since the second node Node2 of the voltage comparison / selection circuit 21243 is at the ground potential, the voltage comparison / selection circuit 21243 receives the first input transmitted to the first node Node1 which is at a higher level than the second node Node2. A high-level power supply voltage for wireless power feeding at the supply terminal T1 of voltage 1 is output as the output voltage Vcc.

Accordingly, in response to the high level output voltage Vcc of the voltage comparison / selection circuit 21243, the digital circuit power supply voltage DV _DD of the second buffer circuit BA2 also rises, so that the capacitance Cp of the time constant circuit of the power-on reset circuit 21244 is increased. The terminal voltage Vc increases.

  A power-on reset period is started by charging the resistor Rp and the capacitor Cp of the time constant circuit. When the terminal voltage Vc of the capacitor Cp of the time constant circuit reaches the detection threshold voltage corresponding to the threshold voltage of the third buffer circuit BA3, the power-on reset signal POR changes from the low level to the high level, and the control logic The power-on reset operation of the circuit 21245 and the input voltage selection switch control logic circuit 21246 is terminated.

  The input voltage selection circuit 21248 generates a high-level voltage detection output signal Vdet1 and a low-level voltage detection output signal Vdet2 during the period T4 due to the end of the restarted power-on reset operation. Accordingly, the first gate drive output signal Mp1_G and the second gate drive output signal Mp2_G are set to a low level and a high level, respectively, under the control of the input voltage selection switch control logic circuit 21246 and the gate drive circuit 21249. Accordingly, the P-channel MOS transistor Mp1 and the P-channel MOS transistor Mp2 of the input voltage selection switch 21242 are controlled to be in an on state and an off state, respectively, so that USB power feeding is controlled to an off state and wireless power feeding is controlled to an on state. Thus, automatic selection is performed in which a power source to be used is selected again from a plurality of power sources in response to a power failure.

  Further, in the operation of the input voltage selection circuit 2124 shown in FIG. 6, the control logic circuit 21245 of the input voltage selection circuit 2124 and the low-level power-on reset signal POR by the restart of the power-on reset period in the power failure period T3 of the wireless power supply The input voltage selection switch control logic circuit 21246 is reset. In particular, the control logic circuit 21245 includes the analog circuit 2128 of FIG. 4 (step-down DC-DC converter 2121, linear regulator 2122, USB type detection circuit 2123, built-in regulator 2126, and gate drive control of the semiconductor integrated circuit 212 shown in FIG. The circuit 2127) is controlled. The control logic circuit 21245 also controls the operations of the switches SW1, SW2, SW3, and SW4, the built-in regulator 2126, and the gate drive control circuit 2127 in FIG. 2, while serially communicating with the microcontroller unit (MCU) 22 and the power receiving system 3. It also controls the operation of the external interface 2125 that executes.

  Therefore, resetting the control logic circuit 21245 of the input voltage selection circuit 2124 resets the control information of the various controlled circuits described above, but the initial setting information is restored from a boot program stored in a nonvolatile memory such as a flash memory. Need to load. On the other hand, since the control information that is not backed up in the nonvolatile memory or the like cannot be recovered, the control information can finally be obtained by restarting the operation of various controlled circuits.

<< Configuration of Input Voltage Detection Circuit According to Embodiment 1 >>
FIG. 7 is a diagram showing a configuration of an input voltage selection circuit 2124 for selecting an operation mode at the time of activation of the semiconductor integrated circuit 212 for battery charge control according to the first embodiment shown in FIG.

  The input voltage selection circuit 2124 of the first embodiment shown in FIG. 7 is different from the input voltage selection circuit 2124 of the comparative reference example of the present invention shown in FIG. 4 in the following points.

  That is, in the input voltage detection circuit 2124 of the first embodiment shown in FIG. 7, the power-on reset auxiliary circuit 2124X included in the input voltage detection circuit 2124 of the comparative reference example of the present invention shown in FIG. The circuit 21249 is deleted. Further, in the input voltage detection circuit 2124 of the first embodiment shown in FIG. 7, the input voltage selection switch 21242 included in the input voltage detection circuit 2124 of the comparative reference example of the present invention shown in FIG. The circuit 2124Y is replaced.

  As shown in FIG. 7, the variable transmission circuit 2124Y includes a first variable transmission circuit 2124Y1 and a second variable transmission circuit 2124Y2. The input terminal of the first variable transmission circuit 2124Y1 is connected to the output terminal of the linear regulator 21241, and the input terminal of the second variable transmission circuit 2124Y2 is connected to the supply terminal T2 of the second input voltage 2 to which the USB power supply voltage is supplied. The The output terminal of the first variable transmission circuit 2124Y1 and the output terminal of the second variable transmission circuit 2124Y2 are connected to the first node Node1 and the second node Node2 of the voltage comparison / selection circuit 21243, respectively. The first gain Gain1 of the first variable transfer circuit 2124Y1 and the second gain Gain2 of the second variable transfer circuit 2124Y2 are the first gain control signal CNT1 generated from the input voltage selection switch control logic circuit 21246 and the second gain control. It is set by the signal CNT2.

  As shown in the upper left part of FIG. 7, the power supply voltage of the wireless power feeding of the power transmission circuit 1 and the AC-DC conversion power supply voltage of the AC power connection interface 24 are supplied to the supply terminal T1 of the first input voltage 1, and the second The USB power supply voltage of the USB connection interface 23 is supplied to the supply terminal T2 for the input voltage 2.

  The power supply voltage or the AC-DC conversion power supply voltage of the wireless power supply having the voltage of 5.5 volts to 20 volts at the supply terminal T1 of the first input voltage 1 is converted into the output power supply voltage of about 5 volts by the linear regulator 21241; The output power supply voltage of about 5 volts is supplied to the input terminal of the first variable transmission circuit 2124Y1 of the variable transmission circuit 2124Y.

  The USB power supply voltage of the USB connection interface 23 having a voltage of 5 volts supplied to the supply terminal T2 of the second input voltage 2 is supplied to the input terminal of the second variable transmission circuit 2124Y2 of the variable transmission circuit 2124Y.

  The voltage comparison / selection circuit 21243 includes the P-channel MOS transistor Mp3, the P-channel MOS transistor Mp4, and the differential amplifier DA1, thereby comparing the voltage of the first node Node1 with the voltage of the second node Node2. A voltage higher than the voltage of the first node Node1 and the voltage of the second node Node2 is selected and generated as the output voltage Vcc. The current passing direction of the body diode d3 of the P-channel MOS transistor Mp3 and the current passing direction of the body diode d4 of the P-channel MOS transistor Mp4 are between the supply terminal T1 for the first input voltage 1 and the supply terminal T2 for the second input voltage 2. The reverse current is set so as not to pass through.

  That is, when the supply terminal T1 of the first input voltage 1 is set to a high voltage level of 5.5 to 20 volts and the supply terminal T2 of the second input voltage 2 is set to a low voltage of zero volts, 2 There is a possibility that a reverse current flows from the common connection node of the P channel MOS transistors Mp3 and Mp4 in the direction of the supply terminal T2 of the second input voltage 2. However, the current passage direction of the body diode d4 connected to the P-channel MOS transistor Mp4 shown in the voltage comparison / selection circuit 21243 in FIG. 7 prevents the passage of the reverse current.

  Further, when the supply terminal T1 of the first input voltage 1 is set to a low voltage level of zero volts and the supply terminal T2 of the second input voltage 2 is set to a high voltage of approximately 5 volts, two P-channel MOSs There is a possibility that a reverse current flows from the common connection node of the transistors Mp3 and Mp4 to the supply terminal T1 of the first input voltage 1. However, the current passage direction of the body diode d3 connected to the P-channel MOS transistor Mp3 shown in the voltage comparison / selection circuit 21243 in FIG. 7 prevents the passage of the reverse current.

  Note that the two types of backflow currents described above do not flow through the sources and drains of the P-channel MOS transistors Mp3 and Mp4 in the following description, and the supply terminal T1 for the first input voltage 1 and the supply terminal T2 for the second input voltage 2 This is a definition in a state in which only one of these is set to a high voltage and the other is set to a low voltage.

  That is, the first node Node1 is connected to the source of the P channel MOS transistor Mp3, the inverting input terminal of the differential amplifier DA1, and the anode of the body diode d3, and the drain and back gate of the P channel MOS transistor Mp3 are short-circuited. The cathode of body diode d3 is connected to the short-circuited drain and back gate of P-channel MOS transistor Mp3. The second node Node2 is connected to the source of the P channel MOS transistor Mp4, the non-inverting input terminal + of the differential amplifier DA1, and the anode of the body diode d4, so that the drain and back gate of the P channel MOS transistor Mp3 are short-circuited. The cathode of body diode d4 is connected to the shorted drain and back gate of P-channel MOS transistor Mp4. The non-inverting output terminal + and the inverting output terminal − of the differential amplifier DA1 are connected to the gate of the P channel MOS transistor Mp3 and the gate of the P channel MOS transistor Mp4, respectively, and the drain of the P channel MOS transistor Mp3 and the P channel MOS transistor. The drain of Mp4 is commonly connected to generate an output voltage Vcc.

  The output voltage Vcc of the voltage comparison / selection circuit 21243 is supplied as an operation power supply voltage to the differential amplifier DA1, the first reference voltage generation circuit Ref_Gen1, the first buffer circuit BA1, and the second buffer circuit BA2.

The first reference voltage generating circuit Ref_Gen1, by operating the output voltage Vcc from the voltage comparison and selection circuit 21243 as an operating power supply voltage, generates a reference voltage _{V REF.}

The first buffer circuit BA1 and the second buffer circuit BA2 are responsive to the reference voltage V _REF generated from the first reference voltage generation circuit Ref_Gen1, and the analog circuit power supply voltage AV _DD proportional to the voltage level of the reference voltage V _REF A digital circuit power supply voltage DV _DD is generated.

The power-on reset circuit 21244 includes a second reference voltage generation circuit Ref_Gen2, a differential amplifier DA2, a resistor Rp, a capacitor Cp, and a third buffer circuit BA3. The second reference voltage generation circuit Ref_Gen2 of the power-on reset circuit 21244 and the differential amplifier DA2 are supplied with the digital circuit power supply voltage DV _DD generated by the second buffer circuit BA2, and the non-inverting input terminal + of the differential amplifier DA2 The digital circuit power supply voltage DV _DD and the reference voltage V _BB generated from the second reference voltage generation circuit Ref_Gen 2 are supplied to the inverting input terminal −.

  The output voltage of the differential amplifier DA2 of the power-on reset circuit 21244 is supplied to one end of the resistor Rp, and the other end of the resistor Rp is connected to one end of the capacitor Cp and the input terminal of the third buffer circuit BA3. Is connected to the ground potential. The low-level power-on reset signal POR generated from the third buffer circuit BA3 during the power-on reset period is the inverted reset input terminal / Reset of the control logic circuit 21245 and the inverted reset input terminal / of the input voltage selection switch control logic circuit 21246. Supplied to Reset.

The clock signal generated from the clock generation circuit 21247 to which the output voltage Vcc from the voltage comparison / selection circuit 21243 and the digital circuit power supply voltage DV _DD from the second buffer circuit BA2 are supplied is the clock input terminal of the control logic circuit 21245. CLK and the input voltage selection switch control logic circuit 21246 are supplied to the clock input terminal CLK.

A control logic circuit 21245 of the input voltage selection circuit 2124 controls the overall operation of the semiconductor integrated circuit 212 shown in FIG. That is, the analog circuit 2128 connected to the input voltage selection circuit 2124 shown in FIG. 7 includes the step-down DC-DC converter 2121, the linear regulator 2122, the USB type detection circuit 2123, and the built-in regulator of the semiconductor integrated circuit 212 shown in FIG. An analog circuit of 2126 and a gate drive control circuit 2127 is included. Therefore, the operations of these analog circuits are all controlled by the control logic circuit 21245 of the input voltage selection circuit 2124 shown in FIG. The analog circuit 2128 is supplied with the output voltage Vcc from the voltage comparison / selection circuit 21243 and the analog circuit power supply voltage AV _DD from the first buffer circuit BA1.

  Further, the operation of the input voltage selection switch control logic circuit 21246 is similarly controlled by the control logic circuit 21245 of the input voltage selection circuit 2124 shown in FIG.

  Furthermore, the operations of the switches SW1, SW2, SW3, SW4, the built-in regulator 2126, and the gate drive control circuit 2127 shown in FIG. 2 are similarly controlled by the control logic circuit 21245 of the input voltage selection circuit 2124 shown in FIG. The Furthermore, the control logic circuit 21245 also controls the operation of the external interface 2125 that executes serial communication with the microcontroller unit (MCU) 22 and the power receiving system 3.

The input voltage detection circuit 21248 is supplied with the output voltage Vcc from the voltage comparison / selection circuit 21243 and the analog circuit power supply voltage AV _DD from the first buffer circuit BA1. After the elapse of the power-on reset period and when the power source to be used is selected again, the input voltage detection circuit 21248 has the second input and the voltage level of the power supply voltage for the wireless power feeding or AC-DC conversion of the supply terminal T1 of the first input voltage 1 The voltage level of the USB power supply voltage at the supply terminal T2 for the voltage 2 is detected. As a result, the 2-bit voltage detection output signals Vdet1 and Vdet2 from the input voltage detection circuit 21248 are supplied to the control logic circuit 21245 and the input voltage selection switch control logic circuit 21246. That is, the voltage detection output signal Vdet1 is obtained by detecting whether or not the power supply voltage for wireless power feeding or AC-DC conversion is supplied to the supply terminal T1 of the first input voltage 1, and the voltage detection output signal Vdet2 is the second input voltage. In this case, it is detected whether or not the USB power supply voltage is supplied to the second supply terminal T2.

  When the power-on reset period has elapsed and when the power supply to be used is selected again, the input voltage selection switch control logic circuit 21246 responds to the 2-bit voltage detection output signals Vdet1 and Vdet2 of the output signal from the input voltage detection circuit 21248. One and the other of the first gain control signal CNT1 and the second gain control signal CNT2 are set to a high level and a low level, respectively. Accordingly, one of the first gain Gain1 of the first variable transmission circuit 2124Y1 and the second gain Gain2 of the second variable transmission circuit 2124Y2 is set to a high gain and a low gain, respectively, and automatic selection of the power source to be used is executed. The

  The supply of the power supply voltage to the supply terminal T1 of the first input voltage 1 is detected by the high level voltage detection output signal Vdet1, and the power supply voltage to the supply terminal T2 of the second input voltage 2 is detected by the low level voltage detection output signal Vdet2. Assume that a non-supply of is detected. In this case, in response to the voltage detection output signals Vdet1 and Vdet2 having different levels, the control logic circuit 21245 controls the switch SW2 in the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. On the other hand, the switch SW3 is controlled to be turned off. As a result, the supply voltage from the supply terminal T1 of the first input voltage 1 is used for charging the secondary battery 26 via the step-down DC-DC converter 2121, the switch SW2, and the P-channel MOS transistor Mp0, and also on the power receiving side. Used to supply power to the system 3. Further, in this case, the input voltage selection switch control logic circuit 21246 sets the first gain Gain1 of the first variable transmission circuit 2124Y1 and the second gain Gain2 of the second variable transmission circuit 2124Y2 to high gain and low gain, respectively. . Further, the voltage comparison / selection circuit 21243 detects that the voltage of the first node Node1 is higher than the second node Node2, and the supply voltage of the supply terminal T1 of the first input voltage 1 of the first node Node1 is voltage comparison / selection. It is generated as the output voltage Vcc of the circuit 21243.

  The low-level voltage detection output signal Vdet1 detects the non-supply of the power supply voltage to the supply terminal T1 of the first input voltage 1, and the high-level voltage detection output signal Vdet2 detects the power supply to the supply terminal T2 of the second input voltage 2 Assume that a voltage supply is detected. In this case, in response to the voltage detection output signals Vdet1 and Vdet2 having different levels, the control logic circuit 21245 controls the switch SW2 inside the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. On the other hand, the switch SW3 is controlled to be on. As a result, the supply voltage from the supply terminal T2 of the second input voltage 2 is used for charging the secondary battery 26 via the switch SW3 and the P-channel MOS transistor Mp0, and for supplying power to the power receiving system 3. used. Further, in this case, the input voltage selection switch control logic circuit 21246 sets the first gain Gain1 of the first variable transmission circuit 2124Y1 and the second gain Gain2 of the second variable transmission circuit 2124Y2 to low gain and high gain, respectively. Further, the voltage comparison / selection circuit 21243 detects that the voltage of the second node Node2 is higher than the first node Node1, and the supply voltage of the supply terminal T2 of the second input voltage 2 of the second node Node2 is voltage comparison / selection. It is generated as the output voltage Vcc of the circuit 21243.

  The power supply voltage for the wireless power feeding or AC-DC conversion to the supply terminal T1 of the first input voltage 1 and the supply terminal T2 of the second input voltage 2 by the 2-bit voltage detection output signals Vdet1 and Vdet2 of the input voltage detection circuit 21248 Assume that the USB power supply voltage is simultaneously detected. In this case, the control logic circuit 21245 adjusts the voltage level of the output power supply voltage Vout of approximately 5 volts of the linear regulator 21241 in response to the voltage detection output signals Vdet1 and Vdet2 which are both at the high level.

  That is, when the supply voltage of the supply terminal T1 of the first input voltage 1 detected simultaneously has priority over the supply voltage of the supply terminal T2 of the second input voltage 2, the output power supply of about 5 volts of the linear regulator 21241. The voltage Vout is set to, for example, 5.2 volts, which is higher than the USB power supply voltage of the USB connection interface 23 having a voltage of 5 volts supplied to the supply terminal T2 of the second input voltage 2. Further, the input voltage selection switch control logic circuit 21246 sets the first gain Gain1 of the first variable transmission circuit 2124Y1 and the second gain Gain2 of the second variable transmission circuit 2124Y2 to high gain and low gain, respectively. As a result, the voltage comparison / selection circuit 21243 detects that the voltage of the first node Node1 is higher than the second node Node2, and the supply voltage of the supply terminal T1 of the first input voltage 1 of the first node Node1 is compared with the voltage. Generated as the output voltage Vcc of the selection circuit 21243 Further, the control logic circuit 21245 controls the switch SW2 in the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 2 to be in an on state, and controls the switch SW3 to be in an off state. As a result, the supply voltage from the supply terminal T1 of the first input voltage 1 is used for charging the secondary battery 26 via the step-down DC-DC converter 2121, the switch SW2, and the P-channel MOS transistor Mp0, and also on the power receiving side. Used to supply power to the system 3.

  On the other hand, when the supply voltage of the supply terminal T2 of the second input voltage 2 is prioritized over the supply voltage of the supply terminal T1 of the first input voltage 1 detected simultaneously, the linear regulator 21241 has approximately 5 volts. The output power supply voltage Vout is set to, for example, 4.8 volts, which is lower than the USB power supply voltage of the USB connection interface 23 having a voltage of 5 volts supplied to the supply terminal T2 of the second input voltage 2. Further, the input voltage selection switch control logic circuit 21246 sets the first gain Gain1 of the first variable transmission circuit 2124Y1 and the second gain Gain2 of the second variable transmission circuit 2124Y2 to low gain and high gain, respectively. As a result, the voltage comparison / selection circuit 21243 detects that the voltage of the second node Node2 is higher than the first node Node1, and the supply voltage of the supply terminal T2 of the second input voltage 2 of the second node Node2 is compared with the voltage. Generated as the output voltage Vcc of the selection circuit 21243 Further, the control logic circuit 21245 controls the switch SW2 inside the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 2 to the off state, and controls the switch SW3 to the on state. As a result, the supply voltage from the supply terminal T2 of the second input voltage 2 is used for charging the secondary battery 26 via the switch SW3 and the P-channel MOS transistor Mp0, and for supplying power to the power receiving system 3. used.

  On the other hand, before the elapse of the power-on reset period, the first gain control signal CNT1 and the second gain control signal CNT2 generated from the input voltage selection switch control logic circuit 21246 in response to the low-level power-on reset signal POR are both Set to high level. Therefore, the first gain Gain1 of the first variable transmission circuit 2124Y1 of the variable transmission circuit 2124Y and the second gain Gain2 of the second variable transmission circuit 2124Y2 are both set to a high gain.

<Configuration of variable transmission circuit>
FIG. 8 is a diagram showing a configuration of first variable transmission circuit 2124Y1 and second variable transmission circuit 2124Y2 of variable transmission circuit 2124Y included in input voltage selection circuit 2124 according to the first embodiment shown in FIG.

  As shown in FIG. 8, the first variable transmission circuit 2124Y1 includes a first differential amplifier 2124Y11, a first P-channel MOS transistor 2124Y12, a first reference voltage generation circuit 2124Y13, a first resistor 2124Y14, a second resistor 2124Y15, and a third resistor. 2124Y16 and a second P-channel MOS transistor 2124Y17. The output power supply voltage of the linear regulator 21241 is supplied as the first input signal Vin1 of the input voltage selection circuit 2124 to the sources of the first differential amplifier 2124Y11, the first reference voltage generation circuit 2124Y13, and the first P-channel MOS transistor 2124Y12. The first reference voltage generated from the first reference voltage generation circuit 2124Y13 is supplied to the inverting input terminal − of the first differential amplifier 2124Y11, and the output signal of the first differential amplifier 2124Y11 is supplied to the gate of the first P-channel MOS transistor 2124Y12. Supplied. A first output signal Vout1 is generated from the drain of the first P-channel MOS transistor 2124Y12, and the first output signal Vout1 is supplied to one end of the first resistor 2124Y14 and the source of the second P-channel MOS transistor 2124Y17. The other end of the first resistor 2124Y14, the drain of the second P-channel MOS transistor 2124Y17, and one end of the third resistor 2124Y16 are connected to the non-inverting input terminal + of the first differential amplifier 2124Y11, and the other end of the third resistor 2124Y16 is grounded. Connected to potential. When the first gain control signal CNT1 supplied from the input voltage selection switch control logic circuit 21246 is at a high level, the second P-channel MOS transistor 2124Y17 is turned off, the negative feedback amount of the first differential amplifier 2124Y11 is reduced, and the first The 1st gain Gain1 of 1 variable transmission circuit 2124Y1 becomes a high gain. When the first gain control signal CNT1 supplied from the input voltage selection switch control logic circuit 21246 is at a low level, the second P-channel MOS transistor 2124Y17 is turned on, the negative feedback amount of the first differential amplifier 2124Y11 becomes large, The 1st gain Gain1 of 1 variable transmission circuit 2124Y1 becomes a low gain.

  As shown in FIG. 8, the second variable transmission circuit 2124Y2 includes a second differential amplifier 2124Y21, a third P-channel MOS transistor 2124Y22, a second reference voltage generation circuit 2124Y23, a fourth resistor 2124Y24, a fifth resistor 2124Y25, and a sixth resistor. 2124Y26 and a fourth P-channel MOS transistor 2124Y27. The USB power supply voltage of the USB connection interface 23 of the supply terminal T2 is used as the second input signal Vin2 of the input voltage selection circuit 2124 as the source of the second differential amplifier 2124Y21, the second reference voltage generation circuit 2124Y23, and the third P-channel MOS transistor 2124Y22. Supplied. The second reference voltage generated from the second reference voltage generation circuit 2124Y23 is supplied to the inverting input terminal − of the second differential amplifier 2124Y21, and the output signal of the second differential amplifier 2124Y21 is supplied to the gate of the third P-channel MOS transistor 2124Y22. Supplied. The first output signal Vout1 is generated from the drain of the third P-channel MOS transistor 2124Y22, and the second output signal Vout2 is supplied to one end of the fourth resistor 2124Y24 and the source of the fourth P-channel MOS transistor 2124Y27. The other end of the fourth resistor 2124Y24, the drain of the fourth P-channel MOS transistor 2124Y27, and one end of the sixth resistor 2124Y26 are connected to the non-inverting input terminal + of the second differential amplifier 2124Y21, and the other end of the sixth resistor 2124Y26 is grounded. Connected to potential. When the second gain control signal CNT2 supplied from the input voltage selection switch control logic circuit 21246 is at a high level, the fourth P-channel MOS transistor 2124Y27 is turned off, and the negative feedback amount of the second differential amplifier 2124Y21 is reduced. The second gain Gain2 of the two variable transmission circuit 2124Y2 is a high gain. When the second gain control signal CNT2 supplied from the input voltage selection switch control logic circuit 21246 is at a low level, the fourth P-channel MOS transistor 2124Y27 is turned on, the negative feedback amount of the second differential amplifier 2124Y21 becomes large, The second gain Gain2 of the two variable transmission circuit 2124Y2 is a low gain.

<< Waveforms of Each Part of Input Voltage Selection Circuit According to Embodiment 1 >>
FIG. 9 is a diagram showing waveforms of respective parts of the input voltage selection circuit 2124 for explaining the operation of the input voltage selection circuit 2124 according to the first embodiment shown in FIG.

  As shown in FIG. 9, in the period T <b> 1, the power supply voltage for the wireless power feeding at the supply terminal T <b> 1 of the first input voltage 1 is first started by supplying the power supply voltage to the supply terminal T <b> 1 of the first input voltage 1. . When the power supply voltage for wireless power feeding reaches the detection threshold voltage, the voltage detection output signal Vdet1 of the input voltage detection circuit 21248 changes from low level to high level.

In response to the increase of the wireless power supply voltage, the output voltage Vcc of the voltage comparison / selection circuit 21243 starts to increase. Further, in response to the increase in the output voltage Vcc of the voltage comparison / selection circuit 21243, the increase in the digital circuit power supply voltage DV _DD generated from the second buffer circuit BA2 is started. When the digital circuit power supply voltage _{DV DD} reaches the detection threshold voltage corresponding to the reference voltage _{V BB} of the second reference voltage generating circuit Ref_Gen2, power on the output is at a high level from the low level of the differential amplifier DA2 of the reset circuit 21244 Then, a power-on reset period is started by charging the resistor Rp and the capacitor Cp of the time constant circuit. When the terminal voltage Vc of the capacitor Cp of the time constant circuit reaches the detection threshold voltage corresponding to the threshold voltage of the third buffer circuit BA3, the power-on reset signal POR changes from the low level to the high level, and the control is performed. The power-on reset operation of the logic circuit 21245 and the input voltage selection switch control logic circuit 21246 is finished.

  By the end of the power-on reset operation, in the period T2, the control logic circuit 21245 and the input voltage selection switch control logic circuit 21246 are switched to the high level voltage detection output signal Vdet1 and the low level voltage detection output signal Vdet2 of the input voltage detection circuit 21248. It is a response. Therefore, the control by the input voltage detection circuit 21248 and the control logic circuit 21245 controls the switch SW2 inside the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 2 to the on state, while setting the switch SW3 to the off state. Control. As a result, the supply voltage from the supply terminal T1 of the first input voltage 1 is used for charging the secondary battery 26 via the step-down DC-DC converter 2121, the switch SW2, and the P-channel MOS transistor Mp0, and also on the power receiving side. Used to supply power to the system 3. Further, by the control by the input voltage selection switch control logic circuit 21246, the first gain control signal CNT1 and the second gain control signal CNT2 are set to the high level and the low level, respectively, and the first gain Gain1 of the first variable transmission circuit 2124Y1 and The second gain Gain2 of the second variable transmission circuit 2124Y2 is set to a high gain and a low gain, respectively. As a result, the voltage comparison / selection circuit 21243 detects that the voltage of the first node Node1 is higher than the second node Node2, and the supply voltage of the supply terminal T1 of the first input voltage 1 of the first node Node1 is compared with the voltage. Generated as the output voltage Vcc of the selection circuit 21243 Accordingly, the wireless power feeding is controlled to be in the on state, the USB power feeding is controlled to be in the off state, and automatic selection of the power source to be used is executed.

  In this state, by the supply of the power supply voltage at the supply terminal T2 of the second input voltage 2 at the end of the period T2, the increase of the power supply voltage for USB power supply at the supply terminal T2 of the second input voltage 2 is started. As a result, when the rise of the USB power supply voltage reaches the detection threshold voltage, the voltage detection output signal Vdet2 of the input voltage detection circuit 21248 changes from the low level to the high level.

  At the last timing of the period T2, the input voltage detection circuit 21248 generates both high-level voltage detection output signals Vdet1 and Vdet2. However, since the priority of the wireless power feeding is set higher than the priority of the USB power feeding inside the control logic circuit 21245, the high-level first gain control is performed from the input voltage selection switch control logic circuit 21246 at the final timing of the period T2. A signal CNT1 and a low-level second gain control signal CNT2 are generated. Accordingly, the first gain Gain1 of the first variable transmission circuit 2124Y1 and the second gain Gain2 of the second variable transmission circuit 2124Y2 are set to a high gain and a low gain, respectively. As a result, the voltage comparison / selection circuit 21243 detects that the voltage of the first node Node1 is higher than the second node Node2, and the supply voltage of the supply terminal T1 of the first input voltage 1 of the first node Node1 is compared with the voltage comparison / selection circuit 21243. It is generated as the output voltage Vcc of the selection circuit 21243. Accordingly, the wireless power feeding is controlled to be in the on state, the USB power feeding is controlled to be in the off state, and automatic selection of the power source to be used is executed.

  However, as shown in FIG. 9, at the switching timing between the period T2 and the period T3, a power failure occurs in the power supply voltage of the wireless power supply of the supply terminal T1 of the first input voltage 1 set in the higher priority order. Therefore, after this switching timing, the voltage of the second node Node2, which is the result of amplification of the USB power supply voltage of the second supply terminal T2 by the low gain second gain Gain2 of the second variable transmission circuit 2124Y2, is the first supply. The level of the wireless power supply voltage at the terminal T1 is higher than the result of amplification by the first gain Gain1 of the high gain of the first variable transmission circuit 2124Y1.

  Therefore, as shown in FIG. 9, at the switching timing between the period T3 and the period T4, the first gain control signal CNT1 generated from the input voltage selection switch control logic circuit 21246 changes from the high level to the low level to change the input voltage. The second gain control signal CNT2 generated from the selection switch control logic circuit 21246 changes from low level to high level. Accordingly, at the switching timing between the period T3 and the period T4, the first gain Gain1 of the first variable transmission circuit 2124Y1 changes from high gain to low gain, and the second gain Gain2 of the second variable transmission circuit 2124Y2 changes from low gain. Change to high gain.

  As a result, as shown in FIG. 9, from the period T4, the voltage comparison / selection circuit 21243 detects that the voltage of the second node Node2 is higher than the first node Node1, and the second input voltage 2 of the second node Node2 The supply voltage of the supply terminal T2 is generated as the output voltage Vcc of the voltage comparison / selection circuit 21243. Further, the control by the input voltage detection circuit 21248 and the control logic circuit 21245 controls the switch SW2 inside the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 2 to the off state, while controlling the switch SW3 to the on state. To do. As a result, the supply voltage from the supply terminal T2 of the second input voltage 2 is used for charging the secondary battery 26 via the switch SW3 and the P-channel MOS transistor Mp0, and for supplying power to the power receiving system 3. used. Therefore, the wireless power supply is controlled to be in an off state, the USB power supply is controlled to be in an on state, and automatic selection is performed in which a power supply to be used is selected again from a plurality of power supplies in response to a power failure.

<< Waveforms of Each Part of Input Voltage Selection Circuit According to Embodiment 1 >>
FIG. 10 is a diagram showing waveforms of respective parts of the input voltage selection circuit 2124 for explaining another operation of the input voltage selection circuit 2124 according to the first embodiment shown in FIG.

  As shown in FIG. 10, in the period T1, the USB power supply voltage at the supply terminal T2 for the second input voltage 2 starts to rise due to the supply of the power supply voltage to the supply terminal T2 for the second input voltage 2 first. When the USB power supply voltage reaches the detection threshold voltage, the voltage detection output signal Vdet2 of the input voltage detection circuit 21248 changes from low level to high level.

In response to the rise of the USB power supply voltage, the output voltage Vcc of the voltage comparison / selection circuit 21243 starts to rise. Further, in response to the increase of the output voltage Vcc of the voltage comparison / selection circuit 21243, the increase of the digital circuit power supply voltage DV _DD generated from the second buffer circuit BA2 is started. When the digital circuit power supply voltage _{DV DD} reaches the detection threshold voltage corresponding to the reference voltage _{V BB} of the second reference voltage generating circuit Ref_Gen2, power on the output is at a high level from the low level of the differential amplifier DA2 of the reset circuit 21244 Then, a power-on reset period is started by charging the resistor Rp and the capacitor Cp of the time constant circuit. When the terminal voltage Vc of the capacitor Cp of the time constant circuit reaches the detection threshold voltage corresponding to the threshold voltage of the third buffer circuit BA3, the power-on reset signal POR changes from the low level to the high level, and the control is performed. The power-on reset operation of the logic circuit 21245 and the input voltage selection switch control logic circuit 21246 is finished.

  The input voltage selection switch control logic circuit 21246 responds to the low level voltage detection output signal Vdet1 and the high level voltage detection output signal Vdet2 of the input voltage detection circuit 21248 in the period T2 due to the end of the power-on reset operation. . Therefore, the control logic circuit 21245 and the input voltage selection switch control logic circuit 21246 are responsive to the low level voltage detection output signal Vdet1 and the high level voltage detection output signal Vdet2 of the input voltage detection circuit 21248. Therefore, the control by the input voltage detection circuit 21248 and the control logic circuit 21245 controls the switch SW2 inside the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 2 to the off state, while turning the switch SW3 to the on state. Control. As a result, the supply voltage from the supply terminal T2 of the first input voltage 2 is used for charging the secondary battery 26 via the switch SW3 and the P-channel MOS transistor Mp0, and for supplying power to the power receiving side system 3. used. Further, under the control of the input voltage selection switch control logic circuit 21246, the first gain control signal CNT1 and the second gain control signal CNT2 are set to a low level and a high level, respectively, and the first gain Gain1 of the first variable transmission circuit 2124Y1 and The second gain Gain2 of the second variable transmission circuit 2124Y2 is set to a low gain and a high gain, respectively. As a result, the voltage comparison / selection circuit 21243 detects that the voltage of the second node Node2 is higher than the first node Node1, and the supply voltage of the supply terminal T2 of the second input voltage 2 of the second node Node2 is compared with the voltage. Generated as the output voltage Vcc of the selection circuit 21243 Accordingly, the wireless power feeding is controlled to be in the off state, the USB power feeding is controlled to be in the on state, and automatic selection of the power source to be used is executed.

  In this state, by the supply of the power supply voltage of the supply terminal T1 of the first input voltage 1 at the end of the period T2, the increase of the power supply voltage of the wireless power feeding of the supply terminal T1 of the first input voltage 1 is started. As a result, when the increase of the power supply voltage for wireless power feeding reaches the detection threshold voltage, the voltage detection output signal Vdet1 of the input voltage detection circuit 21248 changes from the low level to the high level.

  At the last timing of the period T2, the input voltage detection circuit 21248 generates both high-level voltage detection output signals Vdet1 and Vdet2. However, since the priority of wireless power supply is set higher than the priority of USB power supply in the control logic circuit 21245, the low-level first gain control is performed from the input voltage selection switch control logic circuit 21246 at the final timing of the period T2. A signal CNT1 and a high-level second gain control signal CNT2 are generated. Accordingly, the first gain Gain1 of the first variable transmission circuit 2124Y1 and the second gain Gain2 of the second variable transmission circuit 2124Y2 are set to a low gain and a high gain, respectively. As a result, the voltage comparison / selection circuit 21243 detects that the voltage of the second node Node2 is higher than the first node Node1, and the supply voltage of the supply terminal T2 of the second input voltage 2 of the second node Node2 is It is generated as the output voltage Vcc of the selection circuit 21243. Accordingly, the wireless power feeding is controlled to be in the off state, the USB power feeding is controlled to be in the on state, and automatic selection of the power source to be used is executed.

  However, as shown in FIG. 10, at the switching timing between the period T2 and the period T3, a power failure occurs in the power supply voltage of the USB power supply at the supply terminal T2 of the second input voltage 2 set in the higher priority order. Therefore, after this switching timing, the result of amplification of the wireless power supply voltage at the first supply terminal T1 by the low gain first gain Gain1 of the first variable transmission circuit 2124Y1 is the USB power supply voltage at the second supply terminal T2. The voltage becomes higher than the voltage of the second node Node2, which is the result of amplification by the second gain Gain2 of the high gain of the second variable transmission circuit 2124Y2.

  Therefore, as shown in FIG. 10, at the switching timing between the period T3 and the period T4, the first gain control signal CNT1 generated from the input voltage selection switch control logic circuit 21246 changes from the low level to the high level to select the input voltage. The second gain control signal CNT2 generated from the switch control logic circuit 21246 changes from a high level to a low level. Therefore, at the switching timing between the period T3 and the period T4, the first gain Gain1 of the first variable transmission circuit 2124Y1 changes from low gain to high gain, and the second gain Gain2 of the second variable transmission circuit 2124Y2 changes from high gain. Change to low gain.

  As a result, as shown in FIG. 10, from period T4, the voltage comparison / selection circuit 21243 detects that the voltage of the first node Node1 is higher than the second node Node2, and the first input voltage 1 of the first node Node1 The supply voltage of the supply terminal T1 is generated as the output voltage Vcc of the voltage comparison / selection circuit 21243. Further, the control by the input voltage detection circuit 21248 and the control logic circuit 21245 controls the switch SW2 inside the semiconductor integrated circuit 212 according to the first embodiment shown in FIG. 2 to the on state, while setting the switch SW3 to the off state. Control. As a result, the supply voltage from the supply terminal T1 of the first input voltage 1 is used for charging the secondary battery 26 via the step-down DC-DC converter 2121, the switch SW2, and the P-channel MOS transistor Mp0, and also on the power receiving side. Used to supply power to the system 3. Accordingly, the wireless power supply is controlled to be in an on state, the USB power supply is controlled to be in an off state, and automatic selection is performed in which a power supply to be used is selected again from a plurality of power supplies in response to a power failure.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the first variable transmission circuit 2124Y1 and the second variable transmission circuit 2124Y2 of the variable transmission circuit 2124Y of the input voltage selection circuit 2124 of the first embodiment shown in FIG. 7 are not limited to the variable gain amplifier shown in FIG. Further, it is also possible to configure with a variable attenuator (variable attenuator) in which the attenuation amount as a gain is variably controlled.

  Furthermore, the electronic device on which the semiconductor integrated circuit is mounted is not limited to a portable personal computer such as a multi-function mobile phone or a tablet PC, but a digital video camera, a digital still camera, a portable music player, a portable DVD, etc. It can be applied to players and the like.

  Furthermore, an electronic device in which the semiconductor integrated circuit is mounted can be applied to a mobile phone having functions such as an automatic ticket gate system and electronic money by incorporating an RFID card.

DESCRIPTION OF SYMBOLS 1 ... Power transmission circuit 2 ... Power reception circuit 3 ... Power receiving side system 10 ... AC adapter 11 ... Microcontroller unit (MCU)
DESCRIPTION OF SYMBOLS 111 ... Authentication processing function 112 ... Encryption processing function 12 ... Power transmission control circuit 121 ... Rectification circuit 122 ... RF driver 122
DESCRIPTION OF SYMBOLS 13 ... Power transmission side antenna coil 21 ... Power reception control circuit 211 ... Rectification circuit 22 ... Microcontroller unit (MCU)
221 ... Authentication processing function 222 ... Encryption processing function 23 ... USB connection interface 24 ... AC power connection interface 24
25 ... Receiving side antenna coil 26 ... Secondary battery 212 ... Semiconductor integrated circuit T1-T10 ... Terminals D1, D2 ... Schottky diode 2121 ... Step-down DC-DC converter 2122 ... Linear regulator 2123 ... USB type detection circuit 2124 ... Input voltage Detection circuit 2125 ... External interface 2126 ... Built-in regulator 2127 ... Gate drive control circuit Mp0 ... P-channel MOS transistor SW1, SW2, SW3, SW4 ... Switch L1 ... Inductor C1 ... Capacitance 21241 ... Linear regulator 21242 ... Input voltage selection switch 21243 ... Voltage comparison / selection circuit 2124X ... Power-on reset auxiliary circuit 2124X
2124Y ... variable transmission circuit 2124Y1 ... first variable transmission circuit 2124Y2 ... second variable transmission circuit CNT1 ... first gain control signal CNT2 ... second gain control signal Ref_Gen1 ... first reference voltage generation circuit Ref_Gen2 ... second reference voltage generation circuit Ref_Gen3 ... 3rd reference voltage generation circuit Ref_Gen4 ... 4th reference voltage generation circuit DA1 ... Differential amplifier DA2 ... Differential amplifier DA3 ... Differential amplifier DA4 ... Differential amplifier BA1 ... 1st buffer circuit BA2 ... 2nd buffer circuit 21244 ... Power On-reset circuit 21245 ... Control logic circuit 21246 ... Input voltage selection switch control logic circuit 21247 ... Clock generation circuit 21248 ... Input voltage detection circuit 21249 ... Gate drive circuit 2128 ... Analog circuit Mn1, Mn2 ... N channel MOS transistor

Claims (20)

The semiconductor integrated circuit includes: a first supply terminal capable of supplying a first power supply voltage; a second supply terminal capable of supplying a second power supply voltage; and the first supply terminal and the second supply terminal. A connected input voltage selection circuit, a first power switch, and a second power switch;
The input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit, a first variable transmission circuit, a second variable transmission circuit, a voltage comparison / selection circuit, and a control circuit,
The input terminal of the first variable transmission circuit and the input terminal of the second variable transmission circuit are connected to the first supply terminal and the second supply terminal, respectively.
The voltage comparison / selection circuit has a first input terminal, a second input terminal, and an output terminal, the first input terminal is connected to the output terminal of the first variable transmission circuit, and the second input terminal is Connected to the output terminal of the second variable transmission circuit;
An operating voltage supplied to the power-on reset circuit and the input voltage detection circuit is generated from the output terminal of the voltage comparison / selection circuit,
The voltage comparison / selection circuit compares the voltage of the first input terminal and the voltage of the second input terminal to select a high voltage, and thereby selects the high voltage from the output terminal to the power-on reset circuit and the input. Output as the operating voltage supplied to the voltage detection circuit,
The first input voltage detection circuit detects the supply of either the first or second power supply voltage to the first or second supply terminal at the end of the power-on reset operation of the power-on reset circuit. In this case, the control circuit in response to the detection controls to turn on the power switch corresponding to the supply terminal from which the supply is detected among the first and second power switches,
In the first case, the control circuit detects the signal transmission amount of the variable transmission circuit corresponding to the supply terminal from which the supply is detected among the first variable transmission circuit and the second variable transmission circuit. Set larger than the signal transmission amount of the variable transmission circuit corresponding to the supply terminal that is not
The input voltage detection circuit detects the supply of both the first and second power supply voltages to both the first and second supply terminals at the end of the power-on reset operation of the power-on reset circuit. In this case, the control circuit in response to the detection controls the power switch having a higher priority order set in advance among the first and second power switches to an ON state,
In the second case, the control circuit includes the power supply having the higher priority order among the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. The signal transmission amount of the variable transmission circuit corresponding to the switch is set larger than the signal transmission amount of the variable transmission circuit not corresponding to the power switch having the high priority order,
After the power switch having the high priority order is controlled to the on state, the input voltage detection circuit supplies the power switch having the high priority order among the first and second power switches. To detect a power failure of the power supply
In response to the detection result of the power failure by the input voltage detection circuit, the control circuit has a power switch having a low priority order set in advance among the first power switch and the second power switch. Control to ON state,
In response to the detection result of the power failure by the input voltage detection circuit, the control circuit includes the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. A semiconductor integrated circuit that sets a signal transmission amount of a variable transmission circuit corresponding to the power switch having a low priority order to be larger than a signal transmission amount of a variable transmission circuit corresponding to the power switch having a high priority order. In claim 1,
The semiconductor integrated circuit further includes a first external output terminal and a second external output terminal for supplying the first power supply voltage or the second power supply voltage to a first external load and a second external load as loads, respectively. Equipped
The semiconductor integrated circuit further comprises an output P-channel MOS transistor connected between the first external output terminal and the second external output terminal,
When either the first power switch or the second power switch is controlled to be in the on state after the power-on reset operation is completed and in response to the detection result of the power failure, the output is performed by the control circuit. The P-channel MOS transistor is controlled to be on,
When the output P-channel MOS transistor is controlled to be in the ON state, the first power supply voltage or the second power supply voltage is applied to the second external load from the output P-channel MOS transistor and the second external output terminal. A semiconductor integrated circuit that can be supplied via In claim 2,
The first external output terminal is configured to be able to supply the first power supply voltage or the second power supply voltage to the first external load which is another semiconductor integrated circuit as an active device. Is,
The output P-channel MOS transistor and the second external output terminal are configured to be able to supply the first power supply voltage or the second power supply voltage to the second external load that is a battery. Semiconductor integrated circuit. In claim 3,
The first variable transmission circuit and the second variable transmission circuit are semiconductor integrated circuits each including a first variable gain amplifier and a second variable gain amplifier. In claim 3,
The first variable transmission circuit and the second variable transmission circuit are semiconductor integrated circuits each including a first variable attenuator and a second variable attenuator. In claim 3,
The voltage comparison / selection circuit includes a first P-channel MOS transistor, a second P-channel MOS transistor, and a differential amplifier,
The source and drain of the first P-channel MOS transistor are connected to the first input terminal and the output terminal of the voltage comparison / selection circuit, respectively.
The source and drain of the second P-channel MOS transistor are connected to the second input terminal and the output terminal of the voltage comparison / selection circuit, respectively.
The other differential input terminal of one differential input terminal of the differential amplifier is connected to the first input terminal and the second input terminal of the voltage comparison / selection circuit,
A semiconductor integrated circuit connected to the gate of the first P-channel MOS transistor and the gate of the second P-channel MOS transistor, respectively, with one of the differential output terminals of the differential amplifier. In claim 6,
The semiconductor integrated circuit further comprises an external interface for executing serial data communication with an external microcontroller unit,
The control circuit of the input voltage selection circuit is a semiconductor integrated circuit that controls the operation of the external interface. In claim 7,
A semiconductor integrated circuit in which the control circuit is reset by a power-on reset operation of the power-on reset circuit. In claim 8,
The semiconductor integrated circuit further comprises a step-down DC-DC converter and a linear regulator connected in parallel between the first supply terminal and the first power switch,
The linear regulator operates as a series regulator that operates immediately after power-on due to the supply of the first power supply voltage to the first supply terminal,
The step-down DC-DC converter 2121 is a semiconductor integrated circuit that operates as a switching regulator having higher power efficiency than the linear regulator. In claim 9,
The first supply terminal can be supplied with a power supply voltage for wireless power feeding via a first Schottky diode and an AC-DC conversion power supply voltage for an AC power connection interface via a second Schottky diode. The supply terminal is configured,
A semiconductor integrated circuit in which the second supply terminal is configured so that a USB power supply voltage of a USB connection interface can be supplied to the second supply terminal. A first supply terminal capable of supplying a first power supply voltage, a second supply terminal capable of supplying a second power supply voltage, and an input voltage connected to the first supply terminal and the second supply terminal An operation method of a semiconductor integrated circuit comprising a selection circuit, a first power switch, and a second power switch,
The input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit, a first variable transmission circuit, a second variable transmission circuit, a voltage comparison / selection circuit, and a control circuit,
The input terminal of the first variable transmission circuit and the input terminal of the second variable transmission circuit are connected to the first supply terminal and the second supply terminal, respectively.
The voltage comparison / selection circuit has a first input terminal, a second input terminal, and an output terminal, the first input terminal is connected to the output terminal of the first variable transmission circuit, and the second input terminal is Connected to the output terminal of the second variable transmission circuit;
An operating voltage supplied to the power-on reset circuit and the input voltage detection circuit is generated from the output terminal of the voltage comparison / selection circuit,
The voltage comparison / selection circuit compares the voltage of the first input terminal and the voltage of the second input terminal to select a high voltage, and thereby selects the high voltage from the output terminal to the power-on reset circuit and the input. Output as the operating voltage supplied to the voltage detection circuit,
The first input voltage detection circuit detects the supply of either the first or second power supply voltage to the first or second supply terminal at the end of the power-on reset operation of the power-on reset circuit. In this case, the control circuit in response to the detection controls to turn on the power switch corresponding to the supply terminal from which the supply is detected among the first and second power switches,
In the first case, the control circuit detects the signal transmission amount of the variable transmission circuit corresponding to the supply terminal from which the supply is detected among the first variable transmission circuit and the second variable transmission circuit. Set larger than the signal transmission amount of the variable transmission circuit corresponding to the supply terminal that is not
The input voltage detection circuit detects the supply of both the first and second power supply voltages to both the first and second supply terminals at the end of the power-on reset operation of the power-on reset circuit. In this case, the control circuit in response to the detection controls the power switch having a higher priority order set in advance among the first and second power switches to an ON state,
In the second case, the control circuit includes the power supply having the higher priority order among the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. The signal transmission amount of the variable transmission circuit corresponding to the switch is set larger than the signal transmission amount of the variable transmission circuit not corresponding to the power switch having the high priority order,
After the power switch having the high priority order is controlled to the on state, the input voltage detection circuit supplies the power switch having the high priority order among the first and second power switches. To detect a power failure of the power supply
In response to the detection result of the power failure by the input voltage detection circuit, the control circuit has a power switch having a low priority order set in advance among the first power switch and the second power switch. Control to ON state,
In response to the detection result of the power failure by the input voltage detection circuit, the control circuit includes the first and second power switches of the first variable transmission circuit and the second variable transmission circuit. Operation of a semiconductor integrated circuit for setting a signal transmission amount of a variable transmission circuit corresponding to the power switch having a low priority order to be larger than a signal transmission amount of a variable transmission circuit corresponding to the power switch having a high priority order Law method. In claim 11,
The semiconductor integrated circuit further includes a first external output terminal and a second external output terminal for supplying the first power supply voltage or the second power supply voltage to a first external load and a second external load as loads, respectively. Equipped
The semiconductor integrated circuit further comprises an output P-channel MOS transistor connected between the first external output terminal and the second external output terminal,
When either the first power switch or the second power switch is controlled to be in the on state after the power-on reset operation is completed and in response to the detection result of the power failure, the output is performed by the control circuit. The P-channel MOS transistor is controlled to be on,
When the output P-channel MOS transistor is controlled to be in the ON state, the first power supply voltage or the second power supply voltage is applied to the second external load from the output P-channel MOS transistor and the second external output terminal. A method of operating a semiconductor integrated circuit that can be supplied via In claim 12,
The first external output terminal is configured to be able to supply the first power supply voltage or the second power supply voltage to the first external load which is another semiconductor integrated circuit as an active device. Is,
The output P-channel MOS transistor and the second external output terminal are configured to be able to supply the first power supply voltage or the second power supply voltage to the second external load that is a battery. Method of operating a semiconductor integrated circuit. In claim 13,
A method of operating a semiconductor integrated circuit, wherein the first variable transmission circuit and the second variable transmission circuit are respectively constituted by a first variable gain amplifier and a second variable gain amplifier. In claim 13,
A method of operating a semiconductor integrated circuit, wherein the first variable transmission circuit and the second variable transmission circuit are each composed of a first variable attenuator and a second variable attenuator. In claim 13,
The voltage comparison / selection circuit includes a first P-channel MOS transistor, a second P-channel MOS transistor, and a differential amplifier,
The source and drain of the first P-channel MOS transistor are connected to the first input terminal and the output terminal of the voltage comparison / selection circuit, respectively.
The source and drain of the second P-channel MOS transistor are connected to the second input terminal and the output terminal of the voltage comparison / selection circuit, respectively.
The other differential input terminal of one differential input terminal of the differential amplifier is connected to the first input terminal and the second input terminal of the voltage comparison / selection circuit,
Operation method of a semiconductor integrated circuit connected to the gate of the first P-channel MOS transistor and the gate of the second P-channel MOS transistor, respectively, with one of the differential output terminals of the differential amplifier Method. In claim 16,
The semiconductor integrated circuit further comprises an external interface for executing serial data communication with an external microcontroller unit,
A method for operating a semiconductor integrated circuit, wherein the control circuit of the input voltage selection circuit controls the operation of the external interface. In claim 17,
A method for operating a semiconductor integrated circuit, wherein the control circuit is reset by a power-on reset operation of the power-on reset circuit. In claim 18,
The semiconductor integrated circuit further comprises a step-down DC-DC converter and a linear regulator connected in parallel between the first supply terminal and the first power switch,
The linear regulator operates as a series regulator that operates immediately after power-on due to the supply of the first power supply voltage to the first supply terminal,
The step-down DC-DC converter 2121 is a method of operating a semiconductor integrated circuit that operates as a switching regulator having higher power efficiency than the linear regulator. In claim 19,
The first supply terminal can be supplied with a power supply voltage for wireless power feeding via a first Schottky diode and an AC-DC conversion power supply voltage for an AC power connection interface via a second Schottky diode. The supply terminal is configured,
A method of operating a semiconductor integrated circuit in which the second supply terminal is configured so that the USB supply voltage of the USB connection interface can be supplied to the second supply terminal.

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