CN103456716B

CN103456716B - 3-D multi-chip lamination module and manufacture method thereof

Info

Publication number: CN103456716B
Application number: CN201210169820.4A
Authority: CN
Inventors: 陈士弘
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2012-05-29
Filing date: 2012-05-29
Publication date: 2016-05-11
Anticipated expiration: 2032-05-29
Also published as: CN103456716A

Abstract

The invention discloses a kind of 3-D multi-chip lamination module and manufacture method thereof, this 3-D stacks multi-chip module comprises the lamination with W IC chip, each chip has a patterned conductive layer, comprise that one has the electric contact district of electric conductor, in some examples, more comprise the element circuitry on substrate; Electric conductor in laminated chips aligns mutually, and multiple electric connectors extend along lamination is inner, to contact the connection gasket in electric conductor, produce a 3-D stacks multi-chip module; Electric connector can be through vertical through hole interior in electric contact district; Connection gasket can arranged in step shape; This laminated multi-chip module can be made with N etching mask, and wherein 2^N-1Be less than W, and 2^NBe more than or equal to W; These a little etching masks cover alternately and expose 2^n-1Individual connection gasket, wherein n=1,2...N.

Description

3-D multi-chip lamination module and manufacture method thereof

Technical field

The invention relates to a kind of 3-D stacks multi-chip (circle) module, particularly use about one3-D stacks multi-chip (circle) module and the manufacture method thereof of TSV fabrication techniques.

Background technology

The manufacture of a kind of three dimensional integrated circuits (three-dimensionalintegratedcircuit, 3DIC)Method is by multiple semiconductor Chip Vertical ground laminations bonding, to produce single 3DIC. FromOutside connection gasket is to the electric connection of the electric conductor in 3DIC, and in 3DIC different conductive layers itBetween electric connection can several different methods reach. For example,, in a kind of method of routing bonding, by phaseThe edge of adjacent chip can steppedly stagger. So can be with outside bonding wire by the weld pad of chip and liningWeld pad at the end connects.

The another kind of method being electrically connected between laminated chips be called silicon through hole (through-siliconvia,TSV), caused great concern. By the more traditional outside of laminated chips connecing in TSVRouting bonding techniques has several advantages. TSV laminated chips is compared with connecting with outside routing bonding techniquesLaminated chips, can show wider bandwidth, and then has more I/O. And TSV providesShort access path, and then improve processing speed and reduce power consumption.

Can adopt the wafer scale lamination (waferscalestacking) with separation or stripping and slicing contraposition chipComplete TSV. Wafer scale lamination provides low cost and high-throughput, but because one chip in laminationFault can cause the fault of whole lamination, and has low-yield problems. In addition, the processing of wafer wear down isA major challenge in manufacture process, may cause damage or the breaking-up of product. Also can adopt chip-scale foldedLayer (diescalestacking) completes TSV. The advantage that adopts chip-scale lamination is to process than being easier to,But cost is also relatively high.

Another shortcoming of tradition TSV technology is, general TSV technique need to be to each chip orWafer carries out 11 steps: TSV photoresist layer deposition, TSV etching, silicon dioxide layer deposition,Barrier layer/kind of crystal layer deposition, patterning photoresist, Cu/W layer deposition, photoresist layer remove, Cu/WThe chemically mechanical polishing of layer, support/operation (support/handlingdiebonding) that chip sticks together,Chip wear down, and bonding. The time and the cost that need except carrying out these a little steps, individually chip instituteThe processing needing and technique also cause the reduction of output.

Summary of the invention

In view of this, the invention provides a kind of example of 3-D stacks multi-chip module, comprise and havingOne lamination of W IC chip. Each chip of this lamination comprises a patterned conductive layer. FigureCase conductive layer is positioned on a substrate and comprises an electric contact district, and electric contact district comprises multiple electric conductors.In these a little electric conductors, at least comprise a connection gasket. Lamination comprises one first chip and one second chip, theOne chip is positioned at one end of lamination, and the second chip is positioned at the other end of lamination, the substrate surface of the first chipTo the patterned conductive layer of the second chip. The connection gasket of each chip, with the company of other chips in laminationConnection pad alignment. Multiple electric connectors are extended in lamination by a surface of lamination, and electrical with connection gasketConnect, to manufacture a 3-D stacks multi-chip module with W chip layer. Other examples can compriseFollowing one or more features of mentioning. Electric connector directly contacts the plurality of connection gasket. At least one portionThe chip dividing comprises an element circuitry, and this element circuitry and electric contact interval are every setting. One material layer,Be positioned on the patterned conductive layer of the first chip. Electric connector is vertically logical by one in electric contact districtHole. Each electric connector is electrically connected at a connection gasket of a chip layer. Electrically connect with electric connectorThe connection gasket connecing is arranged with step-wise manner.

The example of the many wafer modules of 3-D stacks comprises a lamination of multiple IC wafers, itsIn each IC wafers comprise many lattice chip region. At least some chips in each IC wafersDistrict, aligns with the chip region of other wafers in lamination. Each chip region comprises the one as described in epimere3-D stacks multi-chip module.

A kind of example in order to the first method of manufacturing 3-D stacks multi-chip module can be as following enforcement.One lamination with W IC chip is provided. Each chip of this lamination comprises a patterningConductive layer. Patterned conductive layer is positioned on a substrate and comprises an electric contact district, and electric contact district comprises manyIndividual electric conductor, electric conductor comprises multiple connection gaskets. In installation one operation chip extremely chip, one is selectedThe patterned conductive layer of chip on. Remove an exposed surface of selected chip, to produce an enhancingOperation chip. Use and strengthen operation chip, repeat above-mentioned installation and remove step, and making each chipConnection gasket align with the connection gasket of other chips, until W all installation of chip, to produceA 3-D stacks chip. Form multiple electric connectors in a surface of 3-D stacks chip, this is electricity a bitConnector contacts with connection gasket aligned with each other in each chip, has W chip layer to produce one3-D stacks multi-chip module.

The example of the first method more can comprise following one or more feature. Form multiple electric connectorsIn step, at least some chips comprise an element circuitry, and element circuitry and electric contact interval are every setting.The step of fitting operation chip more comprise deposition one dielectric, stickiness enhancement layer operation chip and chip itBetween. Chip selection has a chip of a substrate, and substrate has one first side and one second side, firstSide is positioned at patterned conductive layer district, and the second side is positioned at the subtend of the first side, and exposed surface is from substrate the second sideSome be removed. In 3-D stacks multi-chip module, the operation chip of at least a portion is removed,To produce an exposed surface. Manufacture multiple contact openings in the surface of this module, contact openings is positioned at oftenOn the connection gasket of one chip layer electric conductor; Select N etching mask, wherein N is selected from and makes 2^N-1Be less than W and 2^NBe more than or equal to the numeral of W; Use N those W chips of etching mask etchingThe contact openings of layer, N etching mask numbered with n, wherein n=1,2...N, uses N etchingThe step of mask etching comprises being numbered the mask etching 2 of n^n-1Chip layer in effectively half connectTouch opening; Electric conductor can be formed in contact openings, to be electrically connected with the connection gasket of each chip layer.After removing operation chip, cover this surface of this module with a dielectric material, the plurality of in manufactureIn the step of contact openings, more comprise the dielectric material that removes at least a portion. Use those N etchingThe step of mask more comprises covering alternately and exposes 2^n-1Individual connection gasket, wherein n=1,2...N.

A kind of the second method of manufacturing multiple 3-D stacks multi-chip modules is as described below. Provide WIC wafers. Each wafer comprises many lattice chip region. Each chip region comprises an ic coreSheet, chip comprises a patterned conductive layer, patterned conductive layer comprises an electric contact district. Electric contact districtComprise multiple connection gaskets. The patterning of one handle wafer to a selecteed wafer in wafer lamination is installedOn conductive layer. Remove an exposed surface of selected wafer, to produce an enhancing handle wafer. UseStrengthen handle wafer, repeat above-mentioned installation and remove step, and make the connection gasket of each wafer and otherThe connection gasket alignment of wafer, until W all installation of wafer, to produce many lattice 3-D stacks coreSheet. Form multiple electric connectors in a surface of 3-D stacks wafer, in electric connector and each chipConnection gasket contact aligned with each other, to produce the 3-D stacks multi-chip mould of the multiple W of having chip layerPiece. Taking the multiple 3-D stacks multi-chip modules of physical method for separation as independent 3-D stacks multi-chip mouldPiece.

The example of the second method also can be as described below formation electric connector step carry out. In this threeMultiple contact openings are manufactured on the surface of dimension laminated wafer module, and contact openings is positioned at 3-D stacks multi-chipOn the connection gasket of each chip layer electric conductor of module. Select N etching mask, wherein N choosingFrom in making 2^N-1Be less than W and 2^NPower is more than or equal to the numeral of W. Use N etching maskThe contact openings of etching W chip layer, N etching mask numbered with n, wherein n=1,2...N, makesComprise the core of the n-1 power of the mask etching 2 that is numbered n by the step of N etching mask etchingEffective half contact openings in lamella. Electric conductor can be formed in contact openings, with each chipThe connection gasket of layer is electrically connected. The example of the second method also can use N etching mask first to cover alternatelyLid 2^n-1Individual connection gasket, then expose 2^n-1Individual connection gasket, wherein n=1,2...N.

Brief description of the drawings

Fig. 1 is the simple enlarged drawing of the section of an IC chip 12.

The upper surface that Fig. 2 is illustrated in the patterned conductive layer 22 of Fig. 1 chip 12 deposits a hard mask layerStructure after 30.

After the bottom 36 that Fig. 3 illustrates the substrate 28 of Fig. 2 chip 12 is removed, make one in residueSubstrate 41 in the tool enhancing operation chip 38 of bonding face 40 once.

The enhancing operation chip 38 that Fig. 4 illustrates Fig. 3 is arranged on the top of another chip 42.

After the substrate bottom that Fig. 5 illustrates each chip 12 in Fig. 4 is all removed, the laminated core of generationThe structure of sheet 46.

Fig. 6 illustrates after the step of repetition Fig. 4 and Fig. 5, one first 3-D stacks chip of generation.

Fig. 7 illustrates the first 3-D stacks chip 48 of Fig. 6, removes the operation core of at least a portionAfter sheet 34, the one second 3-D stacks chip 50 with an exposed surface 52 of generation.

Fig. 8 illustrates deposition one dielectric layer 54 after the exposed surface 52 of Fig. 7, one the 33 of generationDimension laminated chips 56.

Fig. 9-Figure 18 illustrates and sets up as the electric connector 60 of laminated chips module 61 in Figure 18 continuousStep.

Fig. 9 illustrates and on the dielectric layer 54 of Fig. 8, produces after an initial photoresist mask 57, and etching is situated betweenElectricity layer 54 is until the structure that hard mask layer 30 produces.

The one first photoresist mask 66 that Figure 10 illustrates, is formed in Fig. 9 structure except conduction positionPut the opening 58 outside 1,3,5,7.

Figure 11 illustrates after the first photoresist mask 66 that removes Figure 10, forms one second photoresist and coversThe structure of mould 72.

Figure 12 illustrates with 4 layers of one the 3rd photoresist mask etchings, produces one and extends to the logical of every one deckHole.

Figure 13 illustrates the part that in etched substrate 41, through hole 77 exposes, and produces recess 88.

It is for example the line style through hole of the dielectric materials such as oxide material 94 modifieds that Figure 14 illustrates.

Figure 15 illustrates one the 4th photoresist mask and covers the part except earth connection position.

Figure 16 illustrates the result that waits tropism's etching on the substrate of grounding through hole.

Figure 17 illustrates the result in recess deposition of insulative material.

Figure 18 illustrates through hole and the expansion of inserting Figure 17 with metal or other applicable conductive materials and connectsGround through hole, to form the result of earth connection 64 and electric connector 60.0-60.7.

Figure 19-Figure 21 illustrates the simplified plan view of three kinds of chips. Wherein each chip has more than oneElectric contact district, and more than one active component circuit.

Figure 22 illustrates the top view of IC wafer that has grid line and divide a chip region.

Figure 23 illustrates a side cutaway view of the chip of Figure 22.

Figure 24 A to Figure 24 B illustrates four kinds and has the different of 90% non-defective unit chip and 10% bad product chipWafer.

Figure 25 illustrates the result of four kinds of wafers in stacked graph 24A to Figure 24 B.

[main element symbol description]

GC: earth connection position 62: contact pad

0-7: electric conductor position 64: earth connection

12,42,124,126: 66: the first photoresist masks of chip

18: electric contact district 68: the superiors' (ground floor)

20: active component circuit 70: the second layer

22: 72: the second photoresist masks of patterned conductive layer

24: three layers of electric conductors 74: the

26: four layers of dielectric layers 76: the

28,41: 78: the three photoresist masks of substrate

30: hard mask layer 80: layer 5

32: upper surface 82: layer 6

36: bottom 84: layer 7

38: strengthen eight layers of operation chips 86: the

40: lower bonding face 88,90,104: recess

46: laminated chips 92,96: through hole

48: the first 3-D stacks chips 94: dielectric material

50: the second 3-D stacks chips 98,98.0-98.7: connection gasket

52: 100: the four photoresist masks of exposed surface

54: dielectric layer 102,108: grounding through hole

56: the three 3-D stacks chips 106: insulating materials

56.1: the three 3-D stacks wafers 110: structure

57: initial photoresist mask 120: wafer

58: opening 122: grid line

60,60.0-60.7: electric connector 123: chip region

61: laminated chips module

Detailed description of the invention

The present invention can wafer scale lamination (waferscalestacking) or chip-scale lamination (diescaleStacking) complete. In Fig. 1-Figure 21, will the present invention be described in detail in detail with regard to chip-scale lamination. Adopt waferLevel lamination is implemented the advantage that the present invention obtains, and will describe in detail with Figure 22-Figure 25. Phase in wafer or chipSame element will represent with similar label.

Fig. 1 is the simple enlarged drawing of the section of an IC chip 12, and this chip is applicable to the side with following descriptionFormula, sets up a 3-D stacks multi-chip module. The chip 12 that Fig. 1 illustrates comprises an electric contact district18 and an active component circuit 20, within both are all positioned at a patterned conductive layer 22. Patterning is ledElectricity layer 22 comprises a dielectric layer 26, covers on the substrate 28 of chip 12, and supported by substrate 28.Normally silicon of substrate 28. Electric contact district 18 comprises multiple electric conductors 24, these a little electric conductors conventionally by asThe applicable metal such as copper or tungsten is made. Dielectric layer 26 is generally the oxide as silica and so on.In this example, electric conductor 24 and active component circuit 20 are formed among dielectric layer 26 and to be situated betweenThe material interval of electricity layer arranges. Comprise the active component circuit 20 of the mission function circuit of chip, betterBe and electric contact district 18 intervals arrange, so will can not be positioned at the below in electric contact district 18. ActiveElement circuitry 20 can comprise the memory circuitry of flash memory circuit, other types, applied special circuit(applicationspecificcircuit), general processor, programmable logic element (programmableLogicdevice), for the combination of the circuit of chip apparatus system, and this little and other types electricityThe combination on road. In Fig. 1, active component circuit 20 illustrate be a relatively little element be because ofThe object of drawing. The relative size of active component circuit and contact areas 18 depends on specific application.

Fig. 2 illustrates at the upper surface of the patterned conductive layer 22 of Fig. 1 chip 12 and deposits a hard mask layer30. Hard mask layer 30 is one dielectric layers arbitrarily, for insulation and enhancing adhesive force. One operationChip 34 (handlingdie) is arranged on the hard mask layer 30 of chip 12. Preferably select thickThe operation chip 34 that degree and intensity are enough, to prevent in the processing step continuing, operation chip 34The damage of lower square chip 12 and the follow-up chip adding 12. The normally naked crystalline substance of a silicon of operation chip 34.While using wafer scale lamination, a handle wafer is set on wafer, this handle wafer be conventionally arranged onCover the corresponding hard mask layer of hard mask layer 30 on wafer. Preferably select thickness enough withEnough firm handle wafer, to prevent in the processing step continuing, handle wafer below wafer and afterThe damage of the continuous wafer adding. The normally naked Silicon Wafer of handle wafer.

After the bottom 36 that Fig. 3 illustrates the substrate 28 of Fig. 2 chip 12 is removed, be formed in remainingThe tool enhancing operation chip 38 of bonding face 40 once in substrate 41. Because operation chip 34 provides downChip 12 sufficient intensities of side, therefore can carry out these chip wear down steps. In wafer scale operation,These a little operations will produce an enhancing handle wafer corresponding with strengthening operation chip 38.

The enhancing operation chip 38 that Fig. 4 illustrates Fig. 3 is arranged on the top of another chip 42. Another coreSheet 42 is similar in appearance to the chip 12 of Fig. 1, but preferably comprises and be formed on the upper of patterned conductive layer 22The hard mask layer 30 on surface 32. The lower bonding face 40 that strengthens operation chip 29 is arranged on another chip42 hard mask layer 30. Similarly, in wafer scale operation, the lower surface that strengthens handle wafer is establishedPut the hard mask layer at another wafer.

After the substrate bottom that Fig. 5 illustrates each chip 12 in Fig. 4 is all removed, the laminated core that producesThe structure of sheet 46. Fig. 6 illustrates the technique step that uses extra chip 42 to repeat Fig. 4 and Fig. 5Suddenly the one first 3-D stacks chip 48, producing. Reduce one of advantage of laminated chips 46 thicknessBe the via depth of palpus etching and filling in reduction Fig. 9-Figure 18. Because it is common to increase via depthNeed to increase the diameter of through hole, lower via depth thereby more simplified technique. In practical operation, logicalHole may be taper, and the technology of filling vias has also limited aspect than (via depth/width)Through hole. In the time that wafer scale operates, produce the one first three-dimensional wafer of piling up by similar method.

Fig. 7 illustrates the first 3-D stacks chip 48 of Fig. 6, removes the operation core of at least a portionAfter sheet 34, the one second 3-D stacks chip 50 with an exposed surface 52 of generation. Fig. 8 illustratesDeposit a dielectric layer 54 after the exposed surface 52 of Fig. 7, one the 3rd 3-D stacks chip 56 of generation.In wafer scale operation, produce with similar method that the second 3-D stacks wafer and Figure 25 illustrate theThree 3-D stacks wafers 56.1. Fig. 9-Figure 18 has illustrated and has set up as laminated chips module 61 in Figure 18The consecutive steps of electric connector 60, these a little electric connectors 60 contact with electric conductor 24. Electrical connectionThe connection gasket 98 that device 60 connects the electric conductor 24 that is positioned at different layers is to contact pad 62. As shown in figure 18,Each different electric connector 60, with label 60.0-60.7 annotation, is wherein positioned at the electrical connection of the leftmost sideThe label of device is 60.0. In graphic, the position that electric connector 60 contacts with corresponding electric conductor 24 with0 to 7 sign. Label is that the position of GC is the position of earth connection 64, earth connection conventionally with every one deckElectric conductor 24 be electrically connected. Although 24 of the electric conductors of each layer and an electric connector 60 in graphicConnect, in practical operation, can connect the electric conductor with layer with many different electric connectors 6024. In wafer scale operation, the basic technology step identical with the 3rd 3-D stacks wafer 56.1 will be usedRapid laminated multi-chip module 61 arrays that produce.

Fig. 9 illustrates and on the dielectric layer 54 of Fig. 8, produces after an initial photoresist mask 57, and etching is situated betweenElectricity layer 54 is until the structure that hard mask layer 30 produces. The opening 58 of making is aimed at the position of earth connectionGC and electric conductor position 0-7.

The one first photoresist mask 66 that Figure 10 illustrates, is formed in Fig. 9 structure except conduction positionPut the opening 58 outside 1,3,5,7. The alignment electric conductor that this is not covered by photoresist mask 66 a bit24 opening, then etching by hard mask layer 30, be positioned at electric conductor 24, the dielectric of the superiors 68Layer 26 and silicon substrate 41, etching stopping is on the electric conductor 24 of the second layer 70. Though in graphicElectric connector 60 be arranged in a horizontally-arranged, other layouts are possible. For instance, electric connector60 can be arranged in horizontally-arranged parallel or extending transversely. For example, the electric contact district 18 that Fig. 1 illustrates can wrapDraw together electric connectors 60 more than two rows.

Then, as shown in figure 11, remove the first photoresist mask 66, then form one second photoetchingGlue mask 72 is in the structure of Figure 10, cover earth connection position GC and electric conductor position 0,1,4,5. And etching is two-layer in the following manner. Part etching under electric conductor position 2 and 6 is two-layer, wearsCross the electric conductor 64 of ground floor 68 and the second layer 70 and these a little layers. Under electric conductor position 3 and 7Partial etching two-layer, through electric conductor 24 of the second layer 70 and the 3rd layer 74 and these a little layers. WithThis produces as the structure of Figure 11.

Then, remove the second photoresist mask 72 and form one the 3rd photoresist mask covering earth connectionPosition GC and electric conductor position 0,1,2,3. The electric conductor position 4,5,6,7 exposing thenFour layers of etchings, namely respectively through the layer 5 80 of electric conductor position 4,5,6,7, the 6th layer82, the 7th layer 84 and the 8th layers 86, to produce through hole 77 structures as Figure 12.

Then remove the 3rd photoresist mask 78, then etc. tropism's etching (isotropicetch) substrate 41The part that upper through hole 77 exposes, to produce the recess 88 as Figure 13. Make through hole 77 Deng tropism's etchingElectric conductor 24 form electric conductor recess 90. The through hole 92 of modified is through a little etch step formation thus.

It is for example the line style through hole 92 of the dielectric materials such as oxide material 94 modifieds that Figure 14 illustrates,Its center dant 88 and 90 is filled up with oxide material. Dielectric material 94 can be nitrogenize for instanceSilicon SiN or silicon oxide sio₂. As connection gasket 98 under the through hole 96 forming extends to openElectric conductor.

Figure 15-Figure 17 illustrates the step that electric connector 60 forms, and earth connection 64 is illustrated in Figure 18.In Figure 15, one the 4th photoresist mask 100 covers the part except the GC of earth connection position.Figure 15 separately illustrates etching ground floor to layer 7 (68,70,74,76,80,82,84), etchingStop at the electric conductor 24 of the 8th layer 86, the grounding through hole 102 of generation. Figure 16 illustrates ground connection logicalOn the substrate 41 in hole 102, wait after tropism's etching, in grounding through hole 102, produce recess 104.After these a little steps complete, then remove the 4th photoresist mask 100.

Figure 17 illustrates in recess 104 deposition of insulative material 106, for example, be organic material of polymer and so onThe result of material. In addition, the dielectric layer 26 exposing in grounding through hole 108 is etched back (etchback),Form one and expand grounding through hole 108. So will increase electric conductor 24 by expanding grounding through hole 108Sidewall expose contact-making surface.

Figure 18 illustrates with metal or other applicable conductive materials and inserts the through hole 96 of Figure 17 and expandLarge grounding through hole 108, to form earth connection 64 and electric connector 60.0-60.7. So also produce threeEnclose laminated multi-chip module 61. Multi-chip module 61 is connected with structure 110 with contact pad 62. Due toThe flexibility that this technology provides, for instance, structure 110 can be operation chip or tool active componentChip, be for example memory component or logic element, or the above-mentioned combination of mentioning element. Work as structure110 comprise active component, structure 110 can by with the electric connection of contact pad 62, and lamination multicoreThe interior connection of sheet module 61, and then be connected with electric connector 60 is interior. Earth connection 64 and electric connector 60Be essentially multistage conductive material of the same race. In contrast to the electric connector that tradition forms with TSV technique,Its every layer indivedual through hole are to form respectively, then in the time of chip or the mutual lamination bonding of wafer, electrically connectConnect, because many junction resistance makes bonding interface have high resistance and reliability issues. In addition,Assist bonding (reduction technology difficulty) if this interface contains pad (BondingPAD), have welderingThe more high value that dish design criteria is difficult for micro and causes because of pad.

Although be used to form the chip 12 of the first 3-D stacks chip 48 shown in Fig. 6, its conductor 24Can be at diverse location, and there is independently pattern structure, preferably or can select the position of conductorPut and chip that pattern structure is identical, to simplify technique. Especially, the connection gasket 98 of every one deckNeed especially alignment.

The method of above-mentioned manufacture electric connector 60, available binary representation, with 2⁰...2^N-1In nRepresent n step etching. That is to say that the first photoresist mask 66 of Figure 10 first covers alternately2⁰Individual connection gasket 98, then expose 2⁰Individual connection gasket 98; The second photoresist mask 72 of Figure 11, hands overFirst cover 2 wrongly¹Individual connection gasket 98, then expose 2¹Individual connection gasket 98; The 3rd photoresist of Figure 12Mask 78, first covers 2 alternately²Individual connection gasket 98, then expose 2²Individual connection gasket 98, the rest may be inferred.Utilize the method for this binary representation, can use n mask, in 2ⁿIn the structure of layer, provide passage to make2ⁿIndividual connection gasket 98 and 2ⁿIndividual electric conductor 24 connects. Therefore, 3 masks of use can be in 8 layers of structureIn provide passage that 8 connection gaskets 98 are connected with 8 electric conductors 24. Use 5 masks to providePassage makes 32 connection gaskets 98 be connected with 32 electric conductors 24. Etching not necessarily will be with n-1=0, and 1,2... order is implemented. For example the n-1 of first step etching can be 2, and the n-1 of second step etching can be 0,The n-1 of the 3rd step etching can be 1. So can obtain the structure identical with Figure 12. In typical operationEvery step etching is by the contact openings of etching half. When being more than or equal to, the number of plies that can be etched will be etchedWhen the number of plies, for example, use 29 contact openings of 5 mask etchings to be communicated with 29 connection gaskets, maskTo can not be used for the contact openings of etching half, but in order to " the effectively contact openings " of etching half.

More about electrical connectors 60 method to the connection gasket 98 of electric conductor 24, be described inIn Application No. 13/049,303 and 13/114,931, the assignee institute that this two case is the applicationOwn together, and in this as reference.

Figure 19-Figure 21 is the simplified plan view of three chip 12 examples. Wherein each chip has oneIndividual above electric contact district 18, and more than one active component circuit 20. These a little chips 12 canCan be identical, or can be different. For instance, logic chip is as CPU or controller,Can use together with memory chip. In the example of Figure 19, active component circuit 20 compositing chips12 main part, and electric contact district 18 is along an edge setting of chip 12. In the example of Figure 20In son, electric contact region 18 is along three side settings of active component circuit 20. Figure 21'sIn example, two active component circuit 20 by single electric contact district 18 separately. Due to TSV workOne of advantage of skill is outside connection gasket and connecting line technology, shortens online distance, thereforeEach chip is by You Gengduo electric contact district 18. Estimate one or more electric contacts district 18 and active unitThe minimum range that part circuit is 20 is for example 2 microns. Owing to can producing stress in TSV technique,May need such minimum range. Wherein a kind of application is IO memory widely.

An advantage of the present invention is, can the Production Example 3-D stacks of 3-D stacks memory component in this wayMulti-chip module significantly reduces time and the expense of manufacturing traditional TSV laminated semiconductor element simultaneously.In addition, than traditional TSV technique, the present invention reduces the handling procedure to each chip, and thenCan improve output. Except thinner element (this is extremely important to the device as mobile phone and so on) is provided,By removing chip bottom 36, the thickness that reduces laminated chips 12 also has several advantages. These a little advantagesComprise and reduce 24 couplings mutually of electric connector, and be coupled to the length of connection gasket 98, and then subtractFew resistance and relevant heat loss, improve transmission speed.

The present invention adopts chip-scale lamination as can using as discussed above, also can adopt waferLevel lamination, adopts wafer scale lamination can obtain other advantages as described below. Figure 22 illustrates a toolThere is the top view of the IC wafers 120 of grid line 122. These a little grid lines 122 indicate chip region 123,Individual chips 12 will be cut out by wafer 120. Figure 23 illustrates and is positioned at wafer 120C-7 position, oneThe profile of typical chip 12, this chip is same as in fact the chip 12 of Fig. 1. In this example,Wafer 120 can produce 50 chips 12 altogether. Suppose in Figure 22, illustrate 5 with darker shadeThe chip 124 of individual defect or fault. In this case, on wafer 120, account for 90% chip 126Be non-defective unit, and account for 10% chip 124 for failure chip.

In the example of Figure 24 A to Figure 24 B, 4 different IC wafers 120 respectively have 50 coresSection 123, wherein 10% chip region 123 is bad. If by independent IC wafer 120 stripping and slicing,Then can select non-defective unit chip to use chip-scale stack technology, produce the laminated multi-chip of 90% outputModule. But, because needs use chip-scale stack technology to locate separately to each multi-chip module 61Reason, makes cost process simultaneously 50 laminated multi-chip modules 61 with wafer-level scale more expensive.

IC wafer 24 laminations in Figure 24 A to Figure 24 B are made the 3rd 3-D stacks crystalline substance in Figure 25Circle 56.1. Laminated wafer 56.1 has 15 and is labeled as 2 or 3 chip region 123, represents that these are a little4 chips of lamination wherein 2 or 3 be non-defective unit. Do not make marks represent its every one deck chip allFor non-defective unit. If 4 different IC wafers 120 of lamination bind mutually and stripping and slicing, and with as routingThe mode processing that bonding or TSV etc. are traditional, each has the lamination multicore that exceedes 1 bad product chipSheet module can cause whole multi-chip module because of defect back pieces, because the chip in each multi-chip moduleIt must be non-defective unit. In this example, the non-defective unit laminated multi-chip module of 70% output will be only had, namely35/50ths. But, this technology will be removed as in aforementioned paragraphs, about with chip-scale scale laminationRelevant disposal cost.

Utilize the present invention, the laminated multi-chip module of part tool defect can separate is used as imperfect chipUse. For instance, as fruit chip 12 core that is CPU, if imperfect module 61 toolsThere are 2 non-defective unit chips 12, can be used as a pair of nucleus module, as imperfect module 61 has 3Non-defective unit chip, can be used as three nucleus modules. Similarly, if each chip is depositing of a 1GBReservoir chip, imperfect module 61 optionally can be used as the memory module 2 of 3GB or 2GBGB. In this example, will there is good laminated multi-chip module 61, but also have 2 non-defective units of 5 toolsThe imperfect module 61 of chip 12, and the imperfect module 61 of 3 non-defective unit chips 12 of 10 tools.Due to the singular association pad of each layer in individual other connector link lamination, interconnect technology described hereinDefective chip in can isolated lamination. In the technique of laminated chips and formation connector, defectChip can with can operate chip isolation, a kind of method is the quantity and position according to defective chip in laminationPut, form connector with mask. The recycling of imperfect module 61, contributes to more traditional waferLevel process technology more reduces costs.

In above narration, for example used is " top ", " below ", " top ", " bottom ", " itOn " or " under " etc. term, these a little location expressions be in order to help understand content of the present invention andClaim scope, and can not cause restriction.

In sum, although the present invention discloses as above with preferred embodiment, so it is not in order to limitThe present invention. Persond having ordinary knowledge in the technical field of the present invention, is not departing from spirit of the present inventionIn scope, when being used for a variety of modifications and variations. Therefore, protection scope of the present invention is worked as depending on enclosingBeing as the criterion of defining of claim scope.

Claims

1. a 3-D stacks multi-chip module, comprising:

Have a lamination of W IC chip, each chip of this lamination comprises a patterningConductive layer, this patterned conductive layer is positioned on a substrate and comprises an electric contact district, this electric contact district bagDraw together multiple electric conductors, in the plurality of electric conductor, at least comprise a connection gasket;

This lamination comprises one first chip and one second chip, and this first chip is positioned at one end of this lamination,This second chip is positioned at the other end of this lamination, and this substrate surface of this first chip is to this second chipThis patterned conductive layer;

The plurality of connection gasket of each chip aligns with the plurality of connection gasket of other chips in this lamination;And

Multiple electric connectors, the plurality of electric connector is extended also in this lamination by a surface of this laminationBe electrically connected with the plurality of connection gasket, to manufacture one, to have the 3-D stacks of lamination of W chip manyChip module, the plurality of electric connector comprises the conductive material that multistage is of the same race.

2. module according to claim 1, wherein the plurality of electric connector directly contacts that these are manyIndividual connection gasket.

3. module according to claim 1, wherein the plurality of chip of at least a portion comprisesOne element circuitry, this element circuitry and the plurality of electric contact interval are every setting.

4. module according to claim 3, wherein this element circuitry of at least one chip is positioned atOne first part of this chip, this electric contact district is positioned at this first part and one second part of this chip.

5. module according to claim 3, wherein this element circuitry is positioned at one of this chipSome and one second part, and this electric contact district is positioned between this first part and this second partOne the 3rd part.

6. module according to claim 1, more comprises a material layer, is positioned at this first chipPatterned conductive layer on.

7. module according to claim 1, wherein the plurality of electric connector is by the plurality of electricityA vertical through hole in contact areas.

8. module according to claim 1, wherein each electric connector is electrically connected at oneOne connection gasket of chip layer.

9. module according to claim 1, is wherein electrically connected with the plurality of electric connectorThe plurality of connection gasket is arranged with step-wise manner.

10. the many wafer modules of 3-D stacks, comprising:

One lamination of multiple IC wafers;

Each IC wafers comprises many lattice chip region;

At least some chip region in each IC wafers, with those cores of other wafers in this laminationSection alignment; And

Each lattice chip region comprises a kind of 3-D stacks multi-chip module as claimed in claim 1.

11. 1 kinds of 3-D stacks multi-chip modules, comprising:

The plurality of chip of at least a portion comprises an element circuitry, and this element circuitry and the plurality of electricity connectPoint is interval every setting;

One material layer, is positioned on the patterned conductive layer of this first chip;

The plurality of connection gasket of each chip, aligns with the plurality of connection gasket of other chips in this lamination;And

Multiple electric connectors, the plurality of electric connector is by a vertical through hole, and by a table of this laminationIn this lamination, extend and be electrically connected the plurality of selecteed connection gasket with selecteed connection gasketStepped arrangement, to manufacture a 3-D stacks multi-chip module with the lamination of W chip.

12. 1 kinds of many wafer modules of 3-D stacks, comprising:

One lamination of multiple IC wafers;

Each IC wafers comprises many lattice chip region;

At least some chip region in each IC wafers, the plurality of with other wafers in this laminationChip region alignment; And

Each lattice chip region comprises a kind of 3-D stacks multi-chip module as claimed in claim 11.

Manufacture the method for 3-D stacks multi-chip module, comprising for 13. 1 kinds:

W IC chip is provided, and each chip comprises a patterned conductive layer, this patterningConductive layer comprises an electric contact district, and this electric contact district comprises multiple connection gaskets;

One operation chip this patterned conductive layer to a selecteed chip in the plurality of chip is installedOn;

Remove an exposed surface of this selected chip, to produce an enhancing operation chip;

Use this enhancing operation chip, repeat above-mentioned installation and remove step, and make being somebody's turn to do of each chipMultiple connection gaskets align with the plurality of connection gasket of other chips, until those W chip is all installedComplete, to produce a 3-D stacks chip; And

Form multiple electric connectors in a surface of this 3-D stacks chip, the plurality of electric connector is with everyThe plurality of connection gasket contact aligned with each other in one chip, to produce a lamination with W chip3-D stacks multi-chip module.

14. methods according to claim 13, wherein form in the step of multiple electric connectors,At least some chips comprise an element circuitry, and this element circuitry and the plurality of electric contact interval are every setting.

15. methods according to claim 13, wherein the step of fitting operation chip more comprisesDeposit a dielectric and stickiness enhancement layer between this operation chip and this chip.

16. methods according to claim 13, wherein provide the step of chip more to comprise selectionHave a chip of a substrate, this substrate has one first side and one second side, and this first side is positioned at thisPatterned conductive layer district, this second side is positioned at the subtend of this first side.

17. methods according to claim 16, wherein remove step and more comprise and remove this substrateThe some of this second side.

18. methods according to claim 13, more comprise and remove 3-D stacks multi-chip moduleIn, the operation chip of at least a portion, to produce an exposed surface.

19. methods according to claim 13, the step bag that wherein multiple electric connectors formDraw together:

Multiple contact openings are manufactured on a surface in this module, and the plurality of contact openings is positioned at each chipOn the connection gasket of layer electric conductor;

Select N etching mask, wherein N is selected from and makes 2^N-1Power is less than W and 2^NBe greater than or etc.In the numeral of W;

Use the contact openings of the lamination of those N those W of etching mask etching chip, thoseN etching mask numbered with n, wherein n=1, and 2...N, uses those N etching mask etchingsStep comprises being numbered the mask etching 2 of n^n-1Chip layer in effectively the plurality of contact of half openMouthful; And

The plurality of electric conductor can be formed in the plurality of contact openings, the plurality of with each chip layerConnection gasket is electrically connected.

20. methods according to claim 19, be more included in remove operation chip after, withOne dielectric material covers this surface of this module; And

In the step of manufacturing the plurality of contact openings, more comprise this dielectric material that removes at least a portionMaterial.

21. methods according to claim 19, are wherein used the step of those N etching maskSuddenly more comprise and cover alternately and expose 2^n-1Individual connection gasket, wherein n=1,2...N.

Manufacture the method for multiple 3-D stacks multi-chip modules, comprising for 22. 1 kinds:

W IC wafers is provided, and each wafer comprises many lattice chip region, each chip region bagDraw together an IC chip, this chip comprises a patterned conductive layer, and this patterned conductive layer comprises oneElectric contact district, this electric contact district comprises multiple connection gaskets;

Install a handle wafer to this patterned conductive layer of a selecteed wafer in those wafers itOn;

Remove an exposed surface of this selected wafer, to produce an enhancing handle wafer;

Use this enhancing handle wafer, repeat above-mentioned installation and remove step, and make being somebody's turn to do of each waferMultiple connection gaskets align with the plurality of connection gasket of other chips, until those W wafer is all installedComplete, to produce many lattice 3-D stacks chip; And

Form multiple electric connectors in a surface of this 3-D stacks wafer, the plurality of electric connector is with everyThe plurality of connection gasket aligned with each other in one chip contacts, to produce the folded of multiple W of having chipThe 3-D stacks multi-chip module of layer;

Taking this many lattice 3-D stacks multi-chip module of physical method for separation as independent 3-D stacks multicoreSheet module.

23. methods according to claim 22, the step bag that wherein multiple electric connectors formDraw together:

Multiple contact openings are manufactured on this surface in this 3-D stacks wafer module, the plurality of contact openingsBe positioned on the connection gasket of each chip layer electric conductor of the plurality of 3-D stacks multi-chip module;

Select N etching mask, wherein N is selected from and makes 2^N-1Be less than W and 2^NBe more than or equal to WNumeral;

24. methods according to claim 23, are wherein used the step of those N etching maskSuddenly more comprise and cover alternately and expose 2^n-1Individual connection gasket, wherein n=1,2...N.

25. 1 kinds of 3-D stacks multi-chip modules, comprising:

One chip-stack, each chip in this lamination comprises an electric contact district, is formed on a substrate,This electric contact district comprises multiple connection gaskets;

This chip-stack comprises one first chip and one second chip, and this first chip is positioned at this laminationOne end, this second chip is positioned at the other end of this lamination, this substrate surface of this first chip to this secondThe plurality of connection gasket of chip;

The plurality of connection gasket of each chip aligns with other chips in this lamination; And

One conductive material, this conductive material connects at least one connection in this first chip through through hole and is padded onThe connection gasket of correspondence on this second chip.