TWI467725B - 3d stacked multichip module and method for fabrication the same - Google Patents

Description

Three-dimensional multi-wafer stacking module and manufacturing method thereof

The present invention relates to a three-dimensional stacked multi-wafer (circular) module, and more particularly to a three-dimensional stacked multi-wafer (circular) module fabricated using TSV technology and a method of fabricating the same.

A three-dimensional integrated circuit (3D IC) manufacturing method is to vertically stack and bond a plurality of semiconductor wafers to produce a single 3D IC. The electrical connection from the external connection pads to the conductors within the 3D IC, as well as the electrical connections between the different conductive layers within the 3D IC, can be accomplished in a variety of ways. For example, in a wire bonding method, the edges of adjacent wafers may be staggered in a stepwise manner. In this way, the pad of the wafer and the pad on the substrate can be connected by an external bonding wire.

Another method of electrically connecting between stacked wafers, known as through-silicon via (TSV), has drawn significant attention. Stacked wafers interconnected by TSV have several advantages over conventional external wire bonding techniques. TSV stacked wafers can exhibit a wider bandwidth and thus more I/O than stacked wafers connected by external wire bonding technology. And TSV provides a shorter connection path, which increases processing speed and reduces power consumption.

The TSV can be accomplished using wafer scale stacking with separate or diced alignment wafers. Wafer-level stacking provides low cost and high throughput, but failure of a single wafer in a stack can cause failure of the entire stack with low yield issues. In addition, the processing of wafer thinning is the manufacturing process. A major challenge may result in damage or destruction of the product. The TSV can also be completed using die scale stacking. The advantage of using wafer level stacking is that it is easier to handle, but at a higher cost. Another disadvantage of the traditional TSV technology is that the general TSV process requires 11 steps for each wafer or wafer: TSV photoresist layer deposition, TSV etching, ruthenium dioxide layer deposition, barrier layer/seed layer deposition, Patterned photoresist, Cu/W layer deposition, photoresist layer removal, chemical mechanical polishing of Cu/W layers, support/handling die bonding, wafer thinning, and bonding. In addition to the time and expense required to perform these steps, the processing and processing required for individual wafers also results in reduced yields.

An example of a three-dimensional stacked multi-wafer module includes a stack of one of the W integrated circuit chips. Each wafer of the stack includes a patterned conductive layer. The patterned conductive layer is on a substrate and includes an electrical contact region including a plurality of electrical conductors. At least one of the electrical conductors includes a connection pad. The stack includes a first wafer at one end of the stack and a second wafer at the other end of the stack, the substrate of the first wafer facing the patterned conductive layer of the second wafer. The pad of each wafer is aligned with the pads of the other wafers in the stack. A plurality of electrical connectors extend from one surface of the stack into the stack and are electrically connected to the connection pads to fabricate a three-dimensional stacked multi-chip module having a W wafer layer. Other examples may include one or more of the features mentioned below. The electrical connector directly contacts the connection pads. At least a portion of the wafer includes a component circuit that is spaced from the electrical contact region. A layer of material overlying the patterned conductive layer of the first wafer. The electrical connector passes through one of the vertical through holes in the electrical contact area. Each of the electrical connectors is electrically connected to one of the connection pads of a wafer layer. The connection pads electrically connected to the electrical connector are arranged in a stepwise manner.

An example of a three-dimensional stacked multi-wafer module includes a stack of a plurality of integrated circuit wafers, wherein each integrated circuit wafer includes a plurality of wafer regions. At least some of the wafer areas in each integrated circuit wafer are aligned with the wafer areas of other wafers in the stack. Each wafer area includes a three-dimensional stacked multi-chip module as described in the above paragraph.

An example of a first method for fabricating a three-dimensional stacked multi-wafer module can be implemented as follows. A stack of one of the W integrated circuit chips is provided. Each wafer of the stack includes a patterned conductive layer. The patterned conductive layer is disposed on a substrate and includes an electrical contact region, the electrical contact region includes a plurality of electrical conductors, and the electrical conductor includes a plurality of connection pads. A handle wafer is mounted over the patterned conductive layer of a selected wafer in the wafer. One of the exposed layers of the selected wafer is removed to create an enhanced operational wafer. Using the enhanced operation wafer, the above steps of mounting and removing are repeated, and the pads of each wafer are aligned with the pads of the other wafers until all of the W wafers are mounted to produce a three-dimensional stacked wafer. A plurality of electrical connectors are formed on one surface of the three-dimensional stacked wafer, and the electrical connectors are in contact with mutually aligned connection pads in each of the wafers to produce a three-dimensional stacked multi-chip module having a W wafer layer.

An example of the first method may further include one or more of the following features. In the step of forming a plurality of electrical connectors, at least some of the wafers comprise a component circuit, and the component circuits are spaced apart from the electrical contact regions. The step of mounting the operational wafer further includes depositing a dielectric, viscous enhancement layer between the handle wafer and the wafer. The wafer is selected to have a wafer having a first side and a second side, the first side is located in the patterned conductive layer region, the second side is opposite to the first side, and the exposed layer is from the second side of the substrate. Part of it was removed. In the three-dimensional stacked multi-chip module, at least a portion of the handle wafer is removed to create an exposed surface. Making a plurality of contact openings on the surface of the module, the contact openings being located on the connection pads of the conductors of each of the wafer layers; and selecting N etch masks, wherein N is selected from 2 ^{N-1 is} less than W and 2 ^{N is} greater than Or equal to the number of W; etch the contact openings of the W wafer layers using N etch masks, N etch masks numbered n, where n = 1, 2...N, etched using N etch masks The step includes etching an effective half of the contact openings in the 2 ^n-1 wafer layer with a mask numbered n; the electrical conductors may be formed in the contact openings to electrically connect to the connection pads of each of the wafer layers. After removing the handle wafer, the surface of the module is covered with a dielectric material, and the step of fabricating the contact openings further includes removing at least a portion of the dielectric material. The step of using the N etch masks further includes staggering and exposing 2 ^n-1 connection pads, where n = 1, 2...N.

A second method of fabricating a plurality of three-dimensional stacked multi-chip modules is as follows. W integrated circuit wafers are provided. Each wafer includes a multi-cell wafer area. Each wafer area includes an integrated circuit wafer, the wafer including a patterned conductive layer, and the patterned conductive layer includes an electrical contact region. The electrical contact area includes a plurality of connection pads. An operational wafer is mounted over the patterned conductive layer of a selected wafer in the wafer stack. One of the exposed layers of the selected wafer is removed to create an enhanced operational wafer. Using the enhanced operation wafer, the above steps of mounting and removing are repeated, and the pads of each wafer are aligned with the pads of the other wafers until all of the W wafers are mounted to produce a multi-dimensional three-dimensional stacked wafer. Forming a plurality of electrical connectors on one surface of the three-dimensional stacked wafer, electrically connecting The contacts are in contact with mutually aligned connection pads in each wafer to produce a plurality of three-dimensional stacked multi-chip modules having W wafer layers. Physically separating a plurality of three-dimensional stacked multi-chip modules into separate three-dimensional stacked multi-chip modules.

An example of the second method can also be practiced as described below to form an electrical connector. A plurality of contact openings are formed on the surface of the three-dimensional stacked wafer module, and the contact openings are located on the connection pads of each of the wafer layer conductors of the three-dimensional stacked multi-chip module. N etch masks are selected, wherein N is selected from a number such that 2 ^{N-1 is} less than W and 2 ^{N is} greater than or equal to W. The contact openings of the W wafer layer are etched using N etch masks, N etch masks are numbered n, where n = 1, 2...N, and the step of etching using N etch masks includes masking with number n The mask etches an effective half of the contact opening in the n-1 power of the wafer layer. Electrical conductors may be formed in the contact openings to electrically connect to the connection pads of each of the wafer layers. An example of the second method may also use an N etch mask to alternately cover 2 ^n-1 connection pads first, and then expose 2 ^n-1 connection pads, where n = 1, 2...N.

The invention can be accomplished by wafer scale stacking or die scale stacking. In Figure 1-21, the invention will be described in detail for wafer level stacking. The advantages obtained by implementing the invention using wafer level stacking will be detailed in Figures 22-25. The same elements in a wafer or wafer will be referred to by like reference numerals.

Figure 1 is a simplified enlarged cross-sectional view of an IC wafer 12 suitable for creating a three-dimensional stacked multi-chip module in the manner described below. The wafer 12 shown in FIG. 1 includes an electrical contact region 18 and an active component circuit. 20, both are located within a patterned conductive layer 22. The patterned conductive layer 22 includes a dielectric layer 26 overlying the substrate 28 of the wafer 12 and supported by the substrate 28. Substrate 28 is typically germanium. The electrical contact region 18 includes a plurality of electrical conductors 24, which are typically made of a suitable metal such as copper or tungsten. Dielectric layer 26 is typically an oxide such as cerium oxide. In this example, the electrical conductors 24 and the active device circuitry 20 are formed in the dielectric layer 26 and are spaced apart by the material of the dielectric layer. The active component circuit 20, including the task function circuit of the wafer, is preferably spaced from the electrical contact region 18 such that it will not be located below the electrical contact region 18. The active component circuit 20 may include a flash memory circuit, other types of memory circuits, an application specific circuit, a general purpose processor, a programmable logic device, and a chip device system. Combination of circuits, and combinations of these with other types of circuits. In Figure 1, active component circuit 20 is depicted as a relatively small component for drawing purposes. The relative size of the active component circuit to the contact region 18 depends on the particular application.

FIG. 2 illustrates the deposition of a hard mask layer 30 on the upper surface of the patterned conductive layer 22 of the wafer 12 of FIG. The hard mask layer 30 is an optional dielectric layer for insulating and enhancing adhesion. A handling die 34 is disposed on the hard mask layer 30 of the wafer 12. It is preferred to use the handle wafer 34 of sufficient thickness and strength to prevent damage to the wafer 12 under the wafer 34 and subsequent wafers 12 during subsequent processing steps. The handle wafer 34 is typically a die of bare metal. When wafer level stacking is used, an operational wafer is placed on the wafer, which is typically mounted on a hard mask layer corresponding to the hard mask layer 30 overlying the wafer. The preferred thickness is sufficient Operating the wafer with sufficient robustness to prevent damage to the wafer under the wafer and subsequent wafers during subsequent processing steps. The handling wafer is typically a bare wafer.

FIG. 3 illustrates the enhanced operation wafer 38 having the lower bonding surface 40 in the remaining substrate 41 after the bottom end 36 of the substrate 28 of the wafer 12 of FIG. Since the wafer 34 is operated to provide sufficient strength to the underlying wafer 12, such wafer thinning steps can be performed. In wafer level operation, such operations will result in an enhanced operational wafer corresponding to the enhanced operational wafer 38.

4 shows that the enhanced operation wafer 38 of FIG. 3 is disposed above another wafer 42. The other wafer 42 is similar to the wafer 12 of FIG. 1, but preferably includes a hard mask layer 30 formed on the upper surface 32 of the patterned conductive layer 22. The lower bonding surface 40 of the enhancement operating wafer 29 is disposed on the hard mask layer 30 of the other wafer 42. Similarly, in wafer level operation, the lower surface of the enhanced handle wafer is placed on the hard mask layer of the other wafer.

FIG. 5 is a view showing the structure of the stacked wafer 46 produced after the bottom end of the substrate of each of the wafers 12 in FIG. 4 is removed. FIG. 6 illustrates a first three-dimensional stacked wafer 48 produced by repeating the process steps of FIGS. 4 and 5 using additional wafers 42. One of the advantages of reducing the thickness of the stacked wafer 46 is to reduce the depth of the vias to be etched and filled in Figures 9-18. Since increasing the via depth generally requires increasing the diameter of the via, reducing the via depth and simplifying the process. In practice, the vias may be tapered, and the technique of filling the vias also limits the vias of large aspect ratio (via depth/width). At the wafer level operation, a first three-dimensional stacked wafer is produced by a similar method.

Figure 7 shows the first three-dimensional stacked wafer 48 of Figure 6, removed After at least a portion of the wafer 34 is manipulated, a second three-dimensional stacked wafer 50 having an exposed surface 52 is produced. FIG. 8 illustrates a third three-dimensional stacked wafer 56 produced after depositing a dielectric layer 54 on the exposed surface 52 of FIG. In wafer level operation, a second three-dimensional stacked wafer and a third three-dimensional stacked wafer 56.1 depicted in FIG. 25 are produced in a similar manner. Figures 9-18 illustrate successive steps of establishing an electrical connector 60 for stacking wafer modules 61 as shown in Fig. 18, such electrical connectors 60 being in contact with electrical conductors 24. The electrical connector 60 connects the connection pads 98 of the electrical conductors 24 at different layers to the contact pads 62. As shown in Fig. 18, the various electrical connectors 60 are labeled with the reference numerals 60.0-60.7, wherein the leftmost electrical connector is numbered 60.0. In the drawings, the position at which the electrical connector 60 contacts the corresponding electrical conductor 24 is indicated by 0 to 7. The location labeled GC is the location of ground line 64, which is typically electrically coupled to conductor 24 of each layer. Although the electrical conductors 24 of the various layers in the drawings are only connected to one electrical connector 60, in practice, a plurality of different electrical connectors 60 can be used to connect the electrical conductors 24 of the same layer. At wafer level operation, an array of stacked multi-chip modules 61 will be produced using the same basic process steps as the third three-dimensional stacked wafer 56.1.

FIG. 9 illustrates the structure in which the dielectric layer 54 is etched until the hard mask layer 30 is formed after an initial photoresist mask 57 is formed on the dielectric layer 54 of FIG. The finished opening 58 is aligned with the location GC of the ground line and the conductor locations 0-7.

Figure 10 illustrates a first photoresist mask 66 forming an opening 58 in addition to conductor locations 1, 3, 5, 7 in the structure of Figure 9. The openings of the alignment conductors 24 that are not covered by the photoresist mask 66 are then etched through the hard mask layer 30, the conductors 24 located at the uppermost layer 68, the dielectric layer 26, and the germanium substrate 41, and the etching stops at the second Above the electrical conductors 24 of layer 70. Although the electrical connectors 60 in the drawings are arranged in a horizontal row, other layouts are possible. For example, the electrical connectors 60 can be arranged in a horizontal row that expands in parallel or laterally. For example, the electrical contact region 18 illustrated in FIG. 1 can include more than two rows of electrical connectors 60.

Next, as shown in FIG. 11, the first photoresist mask 66 is removed, and then a second photoresist mask 72 is formed in the structure of FIG. 10, covering the ground line position GC and the conductor positions 0, 1, 4 , 5. The two layers were etched in the following manner. The portions below the conductor locations 2 and 6 etch two layers through the first layer 68 and the second layer 70 and the conductors 64 of the layers. The portions below the electrical conductor locations 3 and 7 etch two layers through the second layer 70 and the third layer 74 and the electrical conductors 24 of the layers. Thereby, the structure as shown in Fig. 11 is produced.

Next, the second photoresist mask 72 is removed and a third photoresist mask is formed to cover the ground line position GC and the conductor locations 0, 1, 2, 3. The exposed conductor locations 4, 5, 6, and 7 are then etched into four layers, that is, fifth layer 80, sixth layer 82, seventh layer 84, and eighth through conductor positions 4, 5, 6, and 7, respectively. Layer 86 is used to create a via 77 structure as shown in FIG.

Next, the third photoresist mask 78 is removed, and the exposed portion of the via 77 on the substrate 41 is isotropically etched to produce the recess 88 as shown in FIG. The isotropic etching causes the electrical conductors 24 of the vias 77 to form the electrical conductor recesses 90. The modified vias 92 are formed via such etching steps.

Fig. 14 is a view showing a linear via 92 modified with a dielectric material 94 such as an oxide material, wherein the recesses 88 and 90 are filled with an oxide material. Dielectric material 94 can be, for example, tantalum nitride SiN or hafnium oxide SiO2. The formed through hole 96 extends to open the electrical conductor as the connection pad 98 underneath.

15-17 illustrate the steps of forming the electrical connector 60, and the grounding line 64 is shown in FIG. In Fig. 15, a fourth photoresist mask 100 covers portions other than the ground line position GC. FIG. 15 further illustrates etching the first to seventh layers (68, 70, 74, 76, 80, 82, 84), and etching stops the electrical conductors 24 of the eighth layer 86 to form the ground vias 102. FIG. 16 illustrates that the recess 104 is formed in the ground via 102 after isotropic etching on the substrate 41 of the ground via 102. After these steps are completed, the fourth photoresist mask 100 is then removed.

Figure 17 depicts the result of depositing an insulating material 106, such as an organic material such as a polymer, in the recess 104. In addition, the exposed dielectric layer 26 in the ground vias 108 is etched back to form an enlarged ground via 108. This will increase the electrical conductors 24 by exposing the sidewalls of the ground vias 108 to expose the contact faces.

Figure 18 illustrates the filling of the vias 96 of Figure 17 and the enlarged ground vias 108 with metal or other suitable conductive material to form the ground lines 64 and the electrical connectors 60.0-60.7. This also produces a three-dimensional stacked multi-chip module 61. The multi-chip module 61 is connected to the structure 110 by a contact pad 62. Due to the flexibility provided by this technique, for example, structure 110 can be a wafer that operates a wafer or has an active component, such as a memory component or a logic component, or a combination of the above-mentioned components. When the structure 110 includes an active component, the structure 110 can be electrically connected to the contact pad 62 and connected to the stacked multi-chip module 61 to be connected to the inside of the electrical connector 60. The ground line 64 and the electrical connector 60 are substantially a plurality of electrically conductive materials of the same type. Compared with the conventional electrical connector formed by the TSV process, each of the individual via holes is formed separately, and then electrically connected when the wafer or the wafer is stacked on each other, because the junction is electrically The resistance makes the bonding interface have high resistance and reliability problems. In addition, if the interface contains a bonding pad (Bonding PAD) to assist bonding (to reduce the difficulty of the process), there will be a pad design criterion that is not easily miniaturized and a higher resistance due to the pad.

Although the wafer 12 used to form the first three-dimensional stacked wafer 48 shown in FIG. 6 has conductors 24 at different positions and has a separate patterned structure, it is preferable to select the position of the conductor and the same patterned structure. The wafer is used to simplify the process. In particular, the connection pads 98 of each layer need to be aligned.

The above method of manufacturing the electrical connector 60 can be expressed in binary, and the nth step etching is represented by n in 2 ⁰ ... 2 ^N-1 . That is, the first photoresist mask 66 of FIG. 10, alternately ²⁰ to cover the connection pads 98, ²⁰ and then exposed connection pads 98; the second photoresist mask 72 of FIG. 11, alternately first cover ²¹ connection pads 98, ²¹ and then exposed connection pads 98; the third photoresist mask 78 of FIG. 12, alternately ²² to cover the connection pads 98, ²² and then exposed connection pads 98, So on and so forth. Using this binary representation, n masks can be used to provide channels in the 2 ⁿ layer structure to connect 2 ⁿ connection pads 98 to 2 ⁿ conductors 24. Thus, the use of three masks provides a channel in an eight-layer structure to connect eight connection pads 98 to eight electrical conductors 24. The use of five masks provides a channel for connecting 32 connection pads 98 to 32 electrical conductors 24. The etching does not have to be performed in the order of n-1=0, 1, 2.... For example, n-1 of the first etching may be 2, n-1 of the second etching may be 0, and n-1 of the third etching may be 1. Thus, the same structure as in Fig. 12 can be obtained. In a typical operation, each step of etching will etch half of the contact openings. When the number of layers that can be etched is greater than or equal to the number of layers to be etched, for example, using 29 masks to etch 29 contact openings to connect 29 connection pads, the mask will not be used to etch half of the contact openings, but instead Used to etch half of the "effective contact opening".

A more detailed description of the method of connecting the electrical connector 60 to the connection pad 98 of the electrical conductor 24 is described in U.S. Patent Application Serial Nos. 13/049,303, the entire disclosure of which is assigned to This is used as a reference.

Figures 19-21 are simplified plan views of three wafer 12 examples. Each of the wafers has more than one electrical contact region 18, and more than one active component circuit 20. Such wafers 12 may be identical or may vary. For example, a logic chip such as a CPU or controller can be used with a memory chip. In the example of FIG. 19, the active device circuit 20 constitutes a major portion of the wafer 12, and the electrical contact region 18 is disposed along one edge of the wafer 12. In the example of Fig. 20, the electrical contact regions 18 are disposed along the three sides of the active device circuit 20. In the example of Fig. 21, the two active component circuits 20 are separated by a single electrical contact region 18. One of the advantages of the TSV process is that there is more electrical contact area 18 per wafer than with, for example, external connection pads and wire technology, which shortens the distance of the wires. The minimum distance between one or more of the electrical contact regions 18 and the active component circuitry 20 is estimated to be, for example, 2 microns. This minimum distance may be required due to stress in the TSV process. One such application is a wide range of IO memories.

One advantage of the present invention is that a three-dimensional stacked multi-wafer module, such as a three-dimensional stacked memory component, can be fabricated while significantly reducing the time and expense of fabricating conventional TSV stacked semiconductor components. In addition, the present invention reduces the processing procedure for each wafer compared to the conventional TSV process, thereby enabling an increase in throughput. In addition to providing thinner components (this is very heavy for devices like mobile phones There are several advantages to reducing the thickness of the stacked wafer 12 by removing the bottom end 36 of the wafer. These advantages include reducing the mutual coupling between the electrical connectors 24 and the length of the coupling pads 98, thereby reducing electrical resistance and associated heat losses and increasing transmission speed.

The present invention can be implemented using wafer level stacking as discussed above, or wafer level stacking, with wafer level stacking to achieve other advantages as described below. FIG. 22 is a top view of an integrated circuit wafer 120 having gate lines 122. Such gate lines 122 designate wafer regions 123 from which individual wafers 12 will be cut. Figure 23 is a cross-sectional view of a typical wafer 12 at wafer 120C-7, which wafer is substantially identical to wafer 12 of Figure 1. In this example, wafer 120 can produce a total of 50 wafers 12. Assume that in Fig. 22, five defective or failed wafers 124 are depicted in darker shades. In this case, 90% of the wafers 126 on the wafer 120 are good, and 10% of the wafers 124 are faulty.

In the example of Figures 24A-B, four different IC wafers 120 each have 50 wafer regions 123, of which 10% of the wafer regions 123 are bad. If the IC wafer 120 is individually diced, then a good wafer can be selected using wafer level stacking techniques to produce a stacked multi-wafer module with 90% yield. However, since it is necessary to separately process each multi-chip module 61 using wafer level stacking technology, it is more expensive to process 50 stacked multi-chip modules 61 at the wafer level.

The IC wafer 24 in Figures 24A-B is stacked to form a third three-dimensional stacked wafer 56.1 in Figure 25. The stacked wafer 56.1 has 15 wafer regions 123 labeled 2 or 3, indicating that 2 or 3 of the 4 stacked wafers are good. Unmarked indicates that each of its layers of wafers is good. Such as If four different IC wafers 120 are stacked, bonded to each other and diced, and processed in a conventional manner such as wire bonding or TSV, each stacked multi-chip module having more than one defective wafer will result in the entire multi-wafer. Modules are returned due to defects because the wafers in each multi-wafer module must be good. In this case, only 70% of the output will be stacked on a multi-wafer module, which is 35 percent. However, this technique will remove the processing costs associated with wafer level scale stacking as in the previous paragraph.

With the present invention, some of the defective stacked multi-chip modules can be separated for use as non-ideal wafers. For example, if the chip 12 is a core of the CPU, the non-ideal module 61 can serve as a dual core module if it has two good chips 12. For example, the non-ideal module 61 has three good chips, which can be used as a three core. Module. Similarly, if each wafer is a 1GB memory chip, the non-ideal module 61 can be used as a 3GB or 2GB memory module 2GB as appropriate. In this example, there will be a good stacked multi-chip module 61, but there are also five non-ideal modules 61 with two good wafers 12, and ten non-ideal modules 61 with three good wafers 12. The interconnect technology described herein is capable of isolating defective wafers in a stack since individual connectors connect a single connection pad of each layer in the stack. In the process of stacking wafers and forming connectors, the defective wafers can be isolated from the operable wafers. One method is to form a connector by masking depending on the number and location of defective wafers in the stack. The reuse of the non-ideal module 61 helps to reduce costs compared to conventional wafer level processing techniques.

In the above description, terms such as "above", "below", "top", "bottom", "above" or "below" are used to help understand the contents of the present invention and Apply for a patent scope without Causes restrictions.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

GC‧‧‧ Grounding wire position

0-7‧‧‧Electrical conductor position

12, 42, 124, 126‧‧‧ wafers

18‧‧‧Electrical contact area

20‧‧‧Active component circuit

22‧‧‧ patterned conductive layer

24‧‧‧Electric conductor

26‧‧‧Dielectric layer

28, 41‧‧‧ substrate

30‧‧‧hard mask layer

32‧‧‧ upper surface

36‧‧‧ bottom

38‧‧‧Enhanced Operational Wafer

40‧‧‧ lower joint

46‧‧‧Stacked wafer

48‧‧‧First three-dimensional stacked wafer

50‧‧‧ second three-dimensional stacked wafer

52‧‧‧ exposed surface

54‧‧‧Dielectric layer

62‧‧‧Contact pads

64‧‧‧ Grounding wire

66‧‧‧First photoresist mask

68‧‧‧Upper level (first floor)

70‧‧‧ second floor

72‧‧‧Second photoresist mask

74‧‧‧ third floor

76‧‧‧ fourth floor

78‧‧‧ Third photoresist mask

80‧‧‧5th floor

82‧‧‧6th floor

84‧‧‧ seventh floor

86‧‧‧ eighth floor

88, 90, 104‧‧ ‧ recess

92, 96‧‧‧through holes

94‧‧‧ dielectric materials

98, 98.0-98.7‧‧‧ connection pads

100‧‧‧4th photoresist mask

102, 108‧‧‧ Grounding through hole

56‧‧‧ Third three-dimensional stacked wafer

56.1‧‧‧ Third 3D stacked wafer

57‧‧‧Initial photoresist mask

58‧‧‧ openings

60, 60.0-60.7‧‧‧ electrical connectors

61‧‧‧Stacked wafer module

106‧‧‧Insulation materials

110‧‧‧ structure

120‧‧‧ wafer

122‧‧‧ grid line

123‧‧‧ wafer area

1 is a simplified enlarged view of a section of an IC wafer 12.

FIG. 2 is a view showing a structure in which a hard mask layer 30 is deposited on the upper surface of the patterned conductive layer 22 of the wafer 12 of FIG.

3 shows that the bottom end 36 of the substrate 28 of the wafer 12 of FIG. 2 is removed, and an enhanced operation wafer 38 having a lower bonding surface 40 in the remaining substrate 41 is formed.

4 shows that the enhanced operation wafer 38 of FIG. 3 is disposed above another wafer 42.

FIG. 5 is a view showing the structure of the stacked wafer 46 produced after the bottom end of the substrate of each of the wafers 12 in FIG. 4 is removed.

Figure 6 illustrates the generation of one of the first three-dimensional stacked wafers after repeating the steps of Figures 4 and 5.

FIG. 7 illustrates the first three-dimensional stacked wafer 48 of FIG. 6. After removing at least a portion of the handle wafer 34, a second three-dimensional stacked wafer 50 having an exposed surface 52 is produced.

FIG. 8 illustrates a third three-dimensional stacked wafer 56 produced after depositing a dielectric layer 54 on the exposed surface 52 of FIG.

Figures 9-18 illustrate successive steps of establishing an electrical connector 60 for stacking wafer modules 61 as in Figure 18.

FIG. 9 illustrates the structure in which the dielectric layer 54 is etched until the hard mask layer 30 is formed after an initial photoresist mask 57 is formed on the dielectric layer 54 of FIG.

Figure 10 illustrates a first photoresist mask 66 forming an opening 58 in addition to conductor locations 1, 3, 5, 7 in the structure of Figure 9.

FIG. 11 illustrates a structure in which a second photoresist mask 72 is formed after the first photoresist mask 66 of FIG. 10 is removed.

Figure 12 illustrates etching four layers with a third photoresist mask to create a via extending to each layer.

Figure 14 illustrates a linear via modified with a dielectric material 94 such as an oxide material.

Figure 15 illustrates a fourth photoresist mask covering portions other than the ground line location.

Figure 16 shows the results of isotropic etching on the substrate of the ground via.

Figure 17 shows the result of depositing an insulating material in the recess.

Figure 18 illustrates the result of filling the via of Figure 17 with metal or other suitable conductive material and expanding the ground via to form ground line 64 and electrical connectors 60.0-60.7.

Figures 19-21 illustrate simplified plan views of three wafers. Each of the wafers has more than one electrical contact zone and more than one active component circuit.

Figure 22 is a top view of an IC wafer having a gate line dividing the wafer region.

Fig. 23 is a side sectional view showing the wafer of Fig. 22.

Figures 24A-B illustrate four different wafers with 90% good wafers and 10% bad wafers.

Figure 25 shows the results of stacking the four wafers in Figures 24A-B.

GC‧‧‧ Grounding wire position

0-7‧‧‧Electrical conductor position

20‧‧‧Active component circuit

24, 24.0-24.7‧‧‧Electrical conductor

26‧‧‧Dielectric layer

28, 41‧‧‧ substrate

30‧‧‧hard mask layer

54‧‧‧Dielectric layer

61‧‧‧Stacked wafer module

60.0-60.7‧‧‧Electrical connector

62‧‧‧Contact pads

64‧‧‧ Grounding wire

68‧‧‧Upper level (first floor)

70‧‧‧ second floor

74‧‧‧ third floor

76‧‧‧ fourth floor

80‧‧‧5th floor

82‧‧‧6th floor

84‧‧‧ seventh floor

86‧‧‧ eighth floor

94‧‧‧ dielectric materials

98.0-98.7‧‧‧ connection pad

110‧‧‧ structure

Claims (25)

A three-dimensional stacked multi-chip module comprising: a stack of W integrated circuit wafers, each of the stacked wafers comprising a patterned conductive layer, the patterned conductive layer being on a substrate and including an electrical contact region The electrical contact region includes a plurality of electrical conductors, the electrical conductors including at least one connection pad; the stack includes a first wafer and a second wafer, the first wafer is located at one end of the stack, the second wafer Located at the other end of the stack, the substrate of the first wafer faces the patterned conductive layer of the second wafer; the connection pads of each wafer are aligned with the connection pads of other wafers in the stack; and a plurality of An electrical connector extending from a surface of the stack into the stack and electrically connected to the connecting pads, and each of the electrical connectors is electrically connected to one of different wafer layers in the stack A pad to fabricate a three-dimensional stacked multi-wafer module having a W wafer layer, the electrical connectors comprising a plurality of substantially identical conductive materials. The module of claim 1, wherein the electrical connectors directly contact the connection pads. The module of claim 1, wherein at least a portion of the chips comprise a component circuit, the component circuit being spaced apart from the electrical contact regions. The module of claim 3, wherein the component circuit of at least one of the chips is located in a first portion of the wafer, the electrical contact region being located at the first portion and the second portion of the wafer Share. The module of claim 3, wherein the component circuit is located at the first portion and the second portion of the wafer, and the electrical contact region is located at the first portion and the second portion A third part between the shares. The module of claim 1, further comprising a material layer on top of the patterned conductive layer of the first wafer. The module of claim 1, wherein the electrical connectors pass through one of the electrical contact regions. The module of claim 1, wherein each of the electrical connectors is electrically connected to one of the pad layers of the wafer layer. The module of claim 1, wherein the connection pads electrically connected to the electrical connectors are arranged in a stepwise manner. A three-dimensional stacked multi-wafer module includes: a stack of a plurality of integrated circuit wafers; each integrated circuit wafer includes a plurality of chip regions; at least some of the wafer regions of each integrated circuit wafer, and The wafer areas of the other wafers in the stack are aligned; and each of the wafer areas includes a three-dimensional stacked multi-chip module as described in claim 1. A three-dimensional stacked multi-chip module comprising: a stack of W integrated circuit wafers, each of the stacked wafers comprising a patterned conductive layer, the patterned conductive layer being on a substrate and including an electrical contact region The electrical contact region includes a plurality of electrical conductors, the electrical conductors including at least one connection pad; at least a portion of the wafers include a component circuit, the component circuit is spaced apart from the electrical contact regions; The stack includes a first wafer and a second wafer, the first wafer is located at one end of the stack, and the second wafer is located at the other end of the stack, and the substrate of the first wafer faces the pattern of the second wafer a conductive layer; a material layer on the patterned conductive layer of the first wafer; the connection pads of each wafer are aligned with the connection pads of other wafers in the stack; and a plurality of electrical connectors, The electrical connectors pass through a vertical through hole and extend from one surface of the stack into the stack and are electrically connected to the selected connection pads. The selected connection pads are arranged in a stepwise manner, and each of the electrical connections The devices are electrically connected to one of the different wafer layers in the stack to fabricate a three-dimensional stacked multi-chip module having a W wafer layer. A three-dimensional stacked multi-wafer module includes: a stack of a plurality of integrated circuit wafers; each integrated circuit wafer includes a plurality of chip regions; at least some of the wafer regions of each integrated circuit wafer, and The wafer areas of the other wafers in the stack are aligned; and each of the wafer areas includes a three-dimensional stacked multi-chip module as described in claim 11. A method of fabricating a three-dimensional stacked multi-chip module, comprising: providing W integrated circuit chips, each wafer including a patterned conductive layer, the patterned conductive layer comprising an electrical contact region, the electrical contact region comprising a plurality Connecting pads; mounting an operating wafer onto the patterned conductive layer of a selected one of the wafers; removing an exposed layer of the selected wafer to produce an enhanced operating crystal Using the enhanced operation wafer, repeating the mounting and removing steps, and aligning the connection pads of each wafer with the connection pads of other wafers until the W wafers are installed to generate a three-dimensional Stacking a wafer; and forming a plurality of electrical connectors on one surface of the three-dimensional stacked wafer, the electrical connectors being in contact with the connection pads aligned with each other in each of the wafers, and each of the electrical connectors is electrically connected to different One of the wafer layers is connected to the pad to create a three-dimensional stacked multi-chip module having a W wafer layer. The method of claim 13, wherein in the step of forming the plurality of electrical connectors, at least some of the wafers comprise a component circuit, the component circuits being spaced apart from the electrical contact regions. The method of claim 13, wherein the step of mounting the operational wafer further comprises depositing a dielectric and adhesion enhancing layer between the operational wafer and the wafer. The method of claim 13, wherein the step of providing a wafer further comprises selecting a wafer having a substrate having a first side and a second side, the first side being located on the patterned conductive layer The second side is located opposite the first side. The method of claim 16, wherein the removing step further comprises removing a portion of the second side of the substrate. The method of claim 13, further comprising removing at least a portion of the three-dimensional stacked multi-wafer module to produce an exposed surface. The method of claim 13, wherein the forming of the plurality of electrical connectors comprises: forming a plurality of contact openings on a surface of the module, the contact openings being located at the connection pads of the conductors of each of the wafer layers Above; selecting N etch masks, wherein N is selected from a number such that 2 ^{N-1 is} less than W and 2 ^{N is} greater than or equal to W; and the contacts of the W wafer layers are etched using the N etch masks Opening, the N etch masks are numbered n, where n=1, 2...N, and the step of etching using the N etch masks comprises etching the 2 ^n-1 wafer with a mask numbered n The contact openings are effective in the layer; and the electrical conductors may be formed in the contact openings to electrically connect the connection pads of each of the wafer layers. The method of claim 19, further comprising covering the surface of the module with a dielectric material after removing the handle wafer; and further comprising removing at least a portion of the step of manufacturing the contact openings The dielectric material. The method of claim 19, wherein the step of using the N etch masks further comprises alternately covering and exposing 2 ^n-1 connection pads, wherein n=1, 2...N. A method of fabricating a plurality of three-dimensional stacked multi-chip modules, comprising: providing W integrated circuit wafers, each wafer including a plurality of wafer regions, each wafer region including an integrated circuit wafer, the wafer including a pattern a conductive layer, the patterned conductive layer comprising an electrical contact region comprising a plurality of connection pads; and a patterned conductive layer mounted on the wafer to a selected one of the wafers Above Removing an exposed layer of the selected wafer to generate an enhanced operation wafer; repeating the mounting and removing steps using the enhanced operation wafer, and making the connection pads of each wafer and other wafers The connection pads are aligned until the W wafers are installed to generate a plurality of three-dimensional stacked wafers; and a plurality of electrical connectors are formed on one surface of the three-dimensional stacked wafer, the electrical connectors and each The connection pads in the wafer are in contact with each other, and each of the electrical connectors is electrically connected to one of the different wafer layers to generate a plurality of three-dimensional stacked multi-chip modules having a W wafer layer; physically separated The three-dimensional stacked multi-chip modules are separate three-dimensional stacked multi-chip modules. The method of claim 22, wherein the forming of the plurality of electrical connectors comprises: forming a plurality of contact openings on the surface of the three-dimensional stacked wafer module, wherein the contact openings are located in the three-dimensional stacked Above each of the wafer layer conductors of the wafer module; N etch masks are selected, wherein N is selected from a number such that 2 ^{N-1 is} less than W and 2 ^{N is} greater than or equal to W; using the N An etch mask etches contact openings of the W wafer layers, wherein the N etch masks are numbered n, wherein n=1, 2...N, and the step of etching using the N etch masks is numbered The mask of n etches half of the contact openings of the 2 ^n-1 wafer layer; and the electrical conductors may be formed in the contact openings to electrically connect the connection pads of each wafer layer. The method of claim 23, wherein the step of using the N etch masks further comprises alternately covering and exposing 2 ^n-1 connection pads, wherein n=1, 2...N. A three-dimensional stacked multi-chip module includes: a wafer stack, each of the wafers including an electrical contact region formed on a substrate, the electrical contact region including a plurality of connection pads; the wafer stack includes a a first wafer and a second wafer, the first wafer is located at one end of the stack, the second wafer is located at the other end of the stack, the substrate of the first wafer faces the connection pads of the second wafer; The connection pads of the wafer are aligned with the other wafers in the stack; and a substantially electrically conductive material is coupled to the at least one connection pad of the first wafer to the corresponding connection pad on the second wafer through the via.