CN103439844A - Array substrate, display device and method for manufacturing array substrate - Google Patents
Array substrate, display device and method for manufacturing array substrate Download PDFInfo
- Publication number
- CN103439844A CN103439844A CN2013103893723A CN201310389372A CN103439844A CN 103439844 A CN103439844 A CN 103439844A CN 2013103893723 A CN2013103893723 A CN 2013103893723A CN 201310389372 A CN201310389372 A CN 201310389372A CN 103439844 A CN103439844 A CN 103439844A
- Authority
- CN
- China
- Prior art keywords
- connecting portion
- metal connecting
- array base
- base palte
- insulation course
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 226
- 238000009413 insulation Methods 0.000 claims description 42
- 239000010408 film Substances 0.000 claims description 39
- 239000010409 thin film Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention relates to an array substrate, a display device and a method for manufacturing the array substrate. The array substrate comprises a first metal connecting portion and a second metal connecting portion, wherein the first metal connecting portion and the second metal connecting portion are located in different layers. The array substrate further comprises a transparent conductive film layer used for connecting the first metal connecting portion and the second metal connecting portion. The first metal connecting portion is separated form the second metal connecting portion through a first insulating layer, and the first metal connecting portion and the second metal connecting portion are at least partly overlapped in the direction perpendicular to the plane where the array substrate is located. The array substrate, the display device and the method for manufacturing the array substrate have the advantages that the first metal connecting portion and the second metal connecting portion are at least partly overlapped in the direction perpendicular to the plane where the array substrate is located, the distance from the transparent conductive film layer used for connecting the first metal connecting portion and the second metal connecting portion to the array substrate in the parallel direction is greatly shortened, the size of the contact resistance when the transparent conductive film layer makes contact with the first metal connecting portion and the second metal connecting portion is reduced, and the generation of a transparent conductive film layer slope is avoided.
Description
Technical field
The present invention relates to technical field of liquid crystal display, a kind of method that relates in particular to array base palte, display device and make array base palte.
Background technology
Array base palte comprises underlay substrate 1, and be formed on successively the grid metal connecting portion 2 on underlay substrate 1, the first insulation course 3, source/leakage metal connecting portion 4, the second insulation course 5, need to connect Gate(grid metal connecting portion) and SD(source/leakage metal connecting portion) during metal, meeting arrange respectively the first insulation course 3 and the second insulation course 5 above the first via hole 7 and the second via hole 8 removal grid metal connecting portions on Gate and SD metal, and the second insulation course 5 of removal source/leakage metal connecting portion 4 tops, then use the ITO(transparent conductive film layer) 6 connections, as shown in Figure 1, because existing the angle of gradient and insulation course, via hole exist section poor, and the distance between grid metal connecting portion 2 and source/leakage metal connecting portion 4 is long, a plurality of slope structures appear in the ITO6 between grid metal connecting portion 2 and source/leakage metal connecting portion 4, and make the resistance between grid metal connecting portion 2 and source/leakage metal connecting portion 4 increase, and phenomenon of rupture easily appears in ITO6.
Summary of the invention
In order to solve the problems of the technologies described above, a kind of method that the invention provides array base palte, display device and make array base palte, the slope structure of the transparent conductive film layer between minimizing grid metal connecting portion, source/leakage metal connecting portion, reduce resistance.
In order to achieve the above object, the technical solution used in the present invention is: a kind of array base palte, comprise: be positioned at the first metal connecting portion and the second metal connecting portion of different layers, also comprise for connecting the transparent conductive film layer of described the first metal connecting portion and the second metal connecting portion;
Described the first metal section and described the second metal connecting portion separate by the first insulation course; Described the first metal connecting portion and described the second metal connecting portion are overlapping at least partly on the direction perpendicular to the array base palte plane.
Further, also comprise:
With described the second metal connecting portion with layer or the second insulation course of forming on described the second metal connecting portion;
The first opening that runs through described the second insulation course and the first insulation course, described the first opening exposes at least a portion of described the first metal connecting portion and at least a portion of described the second metal connecting portion; Described transparent conductive film layer covers described the first opening to connect described the first metal connecting portion and described the second metal connecting portion.
Further, at least part of edge of described the first metal connecting portion is concordant on the direction perpendicular to the array base palte plane with at least part of edge of described the second metal connecting portion, and described the first opening exposes the edge of this concordant described the first metal connecting portion and the edge of described the second metal connecting portion.
Further, described the second metal connecting portion is directly over described the first metal connecting portion.
Further, described the first opening also runs through described the second metal connecting portion, and exposes the part of described the first metal connecting portion upper surface.
Further, described array base palte is thin-film transistor array base-plate, and described the first metal connecting portion and the second metal connecting portion are in the neighboring area of described array base palte; Described the first metal connecting portion is grid metal connecting portion, and described the second metal connecting portion is source/leakage metal connecting portion.
Further, the described grid metal connecting portion on described array base palte, the first insulation course, described source/leakage metal connecting portion, the second insulation course are successively set on the underlay substrate of described array base palte; Or,
The described source of described array base palte/leakage metal connecting portion, the first insulation course, described grid metal connecting portion, the second insulation course are successively set on the underlay substrate of described array base palte.
Further,
One end connecting portion of the grid line that described grid metal connecting portion is described array base palte, the end connecting portion that described source/leakage metal connecting portion is the grid line extension line, described transparent conductive film layer is for being electrically connected to described grid line and described grid line extension line by described the first opening; Perhaps,
One end connecting portion of the data line that described source/leakage metal connecting portion is described array base palte, one end connecting portion of the data line extension line that described grid metal connecting portion is described array base palte, described transparent conductive film layer is for being electrically connected to described data line and described data line extension line by described the first opening; Perhaps,
Be an end connecting portion of the signal wire of described array base palte one of in described grid metal connecting portion and described source/leakage metal connecting portion, another repair line that is this signal wire, described transparent conductive film layer is for being electrically connected to described signal wire and described repair line by described the first opening, and wherein said signal wire is grid line or data line; Perhaps,
Described grid metal connecting portion and described source/leakage metal connecting portion is respectively the connecting portion between the different line segments of public electrode lead-in wire of described array base palte, described transparent conductive film layer for by described the first opening by this difference line segment electrical connection.
The present invention also provides a kind of display device, comprises above-mentioned array base palte.
The present invention also provides a kind of manufacture method of array base palte, comprising:
Form the first metal connecting portion and the second metal connecting portion that are positioned at different layers on array base palte by composition technique;
Be formed for connecting the transparent conductive film layer of described the first metal connecting portion and the second metal connecting portion on array base palte by composition technique;
Described method also comprises; Form the first insulation course between described the first metal section and described the second metal connecting portion;
And described the first metal connecting portion and described the second metal connecting portion are overlapping at least partly on the direction perpendicular to base plan.
Further, also comprise
Form the second insulation course on the described first metal connecting portion of array base palte top layer or described the second metal connecting portion;
By composition technique, run through described the second insulation course and the first insulation course and form the first opening, described the first opening exposes at least a portion of described the first metal connecting portion and at least a portion of described the second metal connecting portion;
By composition technique, form described transparent conductive film layer to connect described the first metal connecting portion and described the second metal connecting portion on described the first opening.
The invention has the beneficial effects as follows: described the first metal connecting portion and described the second metal connecting portion are overlapping at least partly on the direction perpendicular to base plan, for the transparent conductive film layer that is communicated with described the first metal connecting portion, described the second metal connecting portion with described underlay substrate parallel direction on distance greatly shorten, reduce the size of the contact resistance that transparent conductive film layer contacts with described the first metal connecting portion, the second metal connecting portion, reduced the domatic generation of transparent conductive film layer.
The accompanying drawing explanation
Fig. 1 means array base palte schematic cross-section in prior art;
Fig. 2 means array base palte schematic cross-section in one embodiment of the invention;
Fig. 3 means array base palte schematic cross-section in one embodiment of the invention;
Fig. 4 means array base palte schematic cross-section in one embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, structure of the present invention and principle are elaborated, illustrated embodiment, only for explaining the present invention, not limits protection scope of the present invention with this.
As shown in Figure 2, the present embodiment provides a kind of array base palte, comprising: be positioned at the first metal connecting portion 2 and the second metal connecting portion 4 of different layers, also comprise for connecting the transparent conductive film layer 6 of described the first metal connecting portion 2 and the second metal connecting portion 4;
Described the first metal section 2 separates by the first insulation course 3 with described the second metal connecting portion 4; Described the first metal connecting portion 2 is overlapping at least partly on the direction perpendicular to the array base palte plane with described the second metal connecting portion 4.
In the present embodiment, described the first metal connecting portion and described the second metal connecting portion are overlapping at least partly on the direction perpendicular to base plan, for the transparent conductive film layer that is communicated with described the first metal connecting portion, described the second metal connecting portion with described underlay substrate parallel direction on distance greatly shorten, reduce the size of the contact resistance that transparent conductive film layer contacts with described the first metal connecting portion, the second metal connecting portion, reduced the domatic generation of transparent conductive film layer.Promote image quality, reduced the domatic generation of transparent conductive film layer simultaneously, greatly reduced the possibility of nesa coating fault rupture.
With described the second metal connecting portion with layer or the second insulation course of forming on described the second metal connecting portion;
The first opening that runs through described the second insulation course 5 and the first insulation course 3, described the first opening exposes at least a portion of described the first metal connecting portion 2 and at least a portion of described the second metal connecting portion 4; Described transparent conductive film layer 6 covers described the first opening to connect described the first metal connecting portion 2 and described the second metal connecting portion 4.
Only adopt the version that replaces two openings of the prior art that arranges of an opening of the first opening in the present embodiment, reduced the domatic generation of transparent conductive film layer, greatly reduced the possibility of nesa coating fault rupture.
In the present embodiment, in order to realize that described the first metal connecting portion 2 and described the second metal connecting portion 4 are zero in the gap with the parallel plane direction of array base palte, with the slope structure of realizing the transparent conductive film layer 6 for being communicated with described the first metal connecting portion 2, described the second metal connecting portion 4, reduce, the setting of described the first metal connecting portion 2, described the second metal connecting portion 4 is preferably following version:
As shown in Figure 3, in one embodiment, at least part of edge of described the first metal connecting portion 2 is concordant on the direction perpendicular to the array base palte plane with at least part of edge of described the second metal connecting portion 4, and described the first opening exposes the edge of this concordant described the first metal connecting portion 2 and the edge of described the second metal connecting portion 4.
It should be noted that, at least part of edge of described the first metal connecting portion 2 is concordant on the direction perpendicular to the array base palte plane with at least part of edge of described the second metal connecting portion 4, be that at least part of edge of described the first metal connecting portion 2 and at least part of edge of described the second metal connecting portion 4 are overlapping on the direction perpendicular to the array base palte plane, a kind of embodiment during to be the first metal connecting portion 2 described in above-mentioned described embodiment overlapping at least partly on the direction perpendicular to the array base palte plane with described the second metal connecting portion 4.
As shown in Figure 4, in an embodiment, described the second metal connecting portion 4 be positioned at described the first metal connecting portion 2 directly over.
Described the first opening also runs through described the second metal connecting portion 4, and exposes the part of described the first metal connecting portion 2 upper surfaces.
In the present embodiment, described array base palte is thin-film transistor array base-plate, described the first metal connecting portion 2 and the second metal connecting portion 4 are positioned at the neighboring area of described array base palte, and (array base palte can be display base plate, it can be also the substrate of other purposes, such as solar panel etc., the neighboring area here, refer to and draw, comprise the zone of wiring cabling, liner etc., for example non-display area of display base plate periphery at the array base palte periphery for signal wire); Described the first metal connecting portion 2 is grid metal connecting portion, and described the second metal connecting portion 4 is source/leakage metal connecting portion.
Described grid metal connecting portion, described source/leakage metal connecting portion are overlapping at least partly, only be arranged on described grid metal connecting portion, described source/leakage metal connecting portion transparent conductive film layer 6 can be directly by described grid metal connecting portion, described former/leak the metal connecting portion to be communicated with, reduced contact resistance, increase with respect to the whole shared ratio of transparent conductive film layer on array base palte with described grid metal connecting portion, part that described source/leakage metal connecting portion contacts on transparent conductive film layer 6, reduced the possibility of transparent conductive film layer 6 fractures simultaneously.
Described grid metal connecting portion on described array base palte, the first insulation course 3, described source/leakage metal connecting portion, the second insulation course 5 are successively set on the underlay substrate 1 of described array base palte; Or,
The described source of described array base palte/leakage metal connecting portion, the first insulation course 3, described grid metal connecting portion, the second insulation course 5 are successively set on the underlay substrate 1 of described array base palte.
In the present embodiment, one end connecting portion of the grid line that described grid metal connecting portion is described array base palte, the end connecting portion that described source/leakage metal connecting portion is the grid line extension line, described transparent conductive film layer is for being electrically connected to described grid line and described grid line extension line by described the first opening; Perhaps,
One end connecting portion of the data line that described source/leakage metal connecting portion is described array base palte, one end connecting portion of the data line extension line that described grid metal connecting portion is described array base palte, described transparent conductive film layer is for being electrically connected to described data line and described data line extension line by described the first opening; Perhaps,
Be an end connecting portion of the signal wire of described array base palte one of in described grid metal connecting portion and described source/leakage metal connecting portion, another repair line that is this signal wire, described transparent conductive film layer is for being electrically connected to described signal wire and described repair line by described the first opening, and wherein said signal wire is grid line or data line; Perhaps,
Described grid metal connecting portion and described source/leakage metal connecting portion is respectively the connecting portion between the different line segments of public electrode lead-in wire of described array base palte, described transparent conductive film layer for by described the first opening by this difference line segment electrical connection.
A kind of display device also is provided in the embodiment of the present invention, comprises above-mentioned array base palte.
A kind of manufacture method of array base palte also is provided in the embodiment of the present invention, and this array base palte can be the array base palte of above-mentioned any one type, and described method comprises:
Form the first metal connecting portion and the second metal connecting portion that are positioned at different layers on array base palte by composition technique;
Be formed for connecting the transparent conductive film layer of described the first metal connecting portion and the second metal connecting portion on array base palte by composition technique;
Described method also comprises; Form the first insulation course between described the first metal section and described the second metal connecting portion;
And described the first metal connecting portion and described the second metal connecting portion are overlapping at least partly on the direction perpendicular to base plan.
Also comprise: form the second insulation course on the described first metal connecting portion of array base palte top layer or described the second metal connecting portion;
By composition technique, run through described the second insulation course and the first insulation course and form the first opening, described the first opening exposes at least a portion of described the first metal connecting portion and at least a portion of described the second metal connecting portion;
By composition technique, form described transparent conductive film layer to connect described the first metal connecting portion and described the second metal connecting portion on described the first opening.The above is preferred embodiment of the present invention, it should be pointed out that to those skilled in the art, under the prerequisite that does not break away from principle of the present invention, can also make some improvements and modifications, and these improvements and modifications also should be considered as protection domain of the present invention.
Claims (11)
1. an array base palte, comprising: be positioned at the first metal connecting portion and the second metal connecting portion of different layers, also comprise for connecting the transparent conductive film layer of described the first metal connecting portion and the second metal connecting portion;
It is characterized in that, described the first metal section and described the second metal connecting portion separate by the first insulation course; Described the first metal connecting portion and described the second metal connecting portion are overlapping at least partly on the direction perpendicular to the array base palte plane.
2. array base palte according to claim 1, is characterized in that, also comprises:
With described the second metal connecting portion with layer or the second insulation course of forming on described the second metal connecting portion;
The first opening that runs through described the second insulation course and the first insulation course, described the first opening exposes at least a portion of described the first metal connecting portion and at least a portion of described the second metal connecting portion; Described transparent conductive film layer covers described the first opening to connect described the first metal connecting portion and described the second metal connecting portion.
3. array base palte according to claim 2, it is characterized in that, at least part of edge of described the first metal connecting portion is concordant on the direction perpendicular to the array base palte plane with at least part of edge of described the second metal connecting portion, and described the first opening exposes the edge of this concordant described the first metal connecting portion and the edge of described the second metal connecting portion.
4. array base palte according to claim 2, is characterized in that, described the second metal connecting portion is directly over described the first metal connecting portion.
5. array base palte according to claim 4, is characterized in that, described the first opening also runs through described the second metal connecting portion, and expose the part of described the first metal connecting portion upper surface.
6. according to the described array base palte of claim 2-5 any one, it is characterized in that, described array base palte is thin-film transistor array base-plate, and described the first metal connecting portion and the second metal connecting portion are in the neighboring area of described array base palte; Described the first metal connecting portion is grid metal connecting portion, and described the second metal connecting portion is source/leakage metal connecting portion.
7. array base palte according to claim 6, is characterized in that, the described grid metal connecting portion on described array base palte, the first insulation course, described source/leakage metal connecting portion, the second insulation course are successively set on the underlay substrate of described array base palte; Or,
The described source of described array base palte/leakage metal connecting portion, the first insulation course, described grid metal connecting portion, the second insulation course are successively set on the underlay substrate of described array base palte.
8. array base palte according to claim 6, is characterized in that,
One end connecting portion of the grid line that described grid metal connecting portion is described array base palte, the end connecting portion that described source/leakage metal connecting portion is the grid line extension line, described transparent conductive film layer is for being electrically connected to described grid line and described grid line extension line by described the first opening; Perhaps,
One end connecting portion of the data line that described source/leakage metal connecting portion is described array base palte, one end connecting portion of the data line extension line that described grid metal connecting portion is described array base palte, described transparent conductive film layer is for being electrically connected to described data line and described data line extension line by described the first opening; Perhaps,
Be an end connecting portion of the signal wire of described array base palte one of in described grid metal connecting portion and described source/leakage metal connecting portion, another repair line that is this signal wire, described transparent conductive film layer is for being electrically connected to described signal wire and described repair line by described the first opening, and wherein said signal wire is grid line or data line; Perhaps,
Described grid metal connecting portion and described source/leakage metal connecting portion is respectively the connecting portion between the different line segments of public electrode lead-in wire of described array base palte, described transparent conductive film layer for by described the first opening by this difference line segment electrical connection.
9. a display device, is characterized in that, comprises the described array base palte of claim 1-8 any one.
10. the manufacture method of an array base palte comprises:
Form the first metal connecting portion and the second metal connecting portion that are positioned at different layers on array base palte by composition technique;
Be formed for connecting the transparent conductive film layer of described the first metal connecting portion and the second metal connecting portion on array base palte by composition technique;
It is characterized in that, described method also comprises:
Form the first insulation course between described the first metal section and described the second metal connecting portion;
And described the first metal connecting portion and described the second metal connecting portion are overlapping at least partly on the direction perpendicular to base plan.
11. the method for making of array base palte according to claim 10, is characterized in that, also comprises
Form the second insulation course on the described first metal connecting portion of array base palte top layer or described the second metal connecting portion;
By composition technique, run through described the second insulation course and the first insulation course and form the first opening, described the first opening exposes at least a portion of described the first metal connecting portion and at least a portion of described the second metal connecting portion;
By composition technique, form described transparent conductive film layer to connect described the first metal connecting portion and described the second metal connecting portion on described the first opening.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310389372.3A CN103439844B (en) | 2013-08-30 | 2013-08-30 | The method of array substrate, display unit and making array substrate |
| PCT/CN2013/089379 WO2015027619A1 (en) | 2013-08-30 | 2013-12-13 | Array substrate, display apparatus, and method for manufacturing array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310389372.3A CN103439844B (en) | 2013-08-30 | 2013-08-30 | The method of array substrate, display unit and making array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103439844A true CN103439844A (en) | 2013-12-11 |
| CN103439844B CN103439844B (en) | 2016-06-01 |
Family
ID=49693546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310389372.3A Active CN103439844B (en) | 2013-08-30 | 2013-08-30 | The method of array substrate, display unit and making array substrate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103439844B (en) |
| WO (1) | WO2015027619A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104362153A (en) * | 2014-09-17 | 2015-02-18 | 京东方科技集团股份有限公司 | Array substrate, production method thereof and display device |
| WO2015027619A1 (en) * | 2013-08-30 | 2015-03-05 | 京东方科技集团股份有限公司 | Array substrate, display apparatus, and method for manufacturing array substrate |
| CN105140179A (en) * | 2015-08-13 | 2015-12-09 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display panel and display device |
| CN106094371A (en) * | 2016-08-24 | 2016-11-09 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display floater and display device |
| CN110262139A (en) * | 2019-06-11 | 2019-09-20 | 惠科股份有限公司 | Contact hole structure, array substrate and display panel |
| WO2023169189A1 (en) * | 2022-03-07 | 2023-09-14 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method therefor, and display apparatus |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6326641B1 (en) * | 1998-11-27 | 2001-12-04 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device having a high aperture ratio |
| CN101369078A (en) * | 2007-08-17 | 2009-02-18 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and manufacturing method thereof |
| CN101398585A (en) * | 2007-09-27 | 2009-04-01 | 北京京东方光电科技有限公司 | Array substrate of LCD |
| CN101847640A (en) * | 2009-03-27 | 2010-09-29 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and liquid crystal display panel |
| CN102566165A (en) * | 2010-12-20 | 2012-07-11 | 北京京东方光电科技有限公司 | Array substrate, array substrate production method and liquid crystal display |
| WO2012132953A1 (en) * | 2011-03-25 | 2012-10-04 | シャープ株式会社 | Display device |
| CN103149757A (en) * | 2011-12-07 | 2013-06-12 | 乐金显示有限公司 | Liquid crystal display device and method for fabricating the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003338628A (en) * | 2002-05-20 | 2003-11-28 | Seiko Epson Corp | Thin-film semiconductor device, electrooptical device, electronic equipment, manufacturing method for thin- film semiconductor device, and manufacturing method for electrooptical device |
| CN202975551U (en) * | 2012-12-26 | 2013-06-05 | 北京京东方光电科技有限公司 | Array substrate and display device |
| CN103439844B (en) * | 2013-08-30 | 2016-06-01 | 京东方科技集团股份有限公司 | The method of array substrate, display unit and making array substrate |
-
2013
- 2013-08-30 CN CN201310389372.3A patent/CN103439844B/en active Active
- 2013-12-13 WO PCT/CN2013/089379 patent/WO2015027619A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6326641B1 (en) * | 1998-11-27 | 2001-12-04 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device having a high aperture ratio |
| CN101369078A (en) * | 2007-08-17 | 2009-02-18 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and manufacturing method thereof |
| CN101398585A (en) * | 2007-09-27 | 2009-04-01 | 北京京东方光电科技有限公司 | Array substrate of LCD |
| CN101847640A (en) * | 2009-03-27 | 2010-09-29 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and liquid crystal display panel |
| CN102566165A (en) * | 2010-12-20 | 2012-07-11 | 北京京东方光电科技有限公司 | Array substrate, array substrate production method and liquid crystal display |
| WO2012132953A1 (en) * | 2011-03-25 | 2012-10-04 | シャープ株式会社 | Display device |
| CN103149757A (en) * | 2011-12-07 | 2013-06-12 | 乐金显示有限公司 | Liquid crystal display device and method for fabricating the same |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015027619A1 (en) * | 2013-08-30 | 2015-03-05 | 京东方科技集团股份有限公司 | Array substrate, display apparatus, and method for manufacturing array substrate |
| CN104362153A (en) * | 2014-09-17 | 2015-02-18 | 京东方科技集团股份有限公司 | Array substrate, production method thereof and display device |
| CN104362153B (en) * | 2014-09-17 | 2017-07-04 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN105140179A (en) * | 2015-08-13 | 2015-12-09 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display panel and display device |
| WO2017024755A1 (en) * | 2015-08-13 | 2017-02-16 | 京东方科技集团股份有限公司 | Array substrate and production method therefor, display panel, and display apparatus |
| CN105140179B (en) * | 2015-08-13 | 2018-12-14 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel and display device |
| CN106094371A (en) * | 2016-08-24 | 2016-11-09 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display floater and display device |
| CN110262139A (en) * | 2019-06-11 | 2019-09-20 | 惠科股份有限公司 | Contact hole structure, array substrate and display panel |
| CN110262139B (en) * | 2019-06-11 | 2021-07-06 | 惠科股份有限公司 | Contact hole structure, array substrate and display panel |
| WO2023169189A1 (en) * | 2022-03-07 | 2023-09-14 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method therefor, and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103439844B (en) | 2016-06-01 |
| WO2015027619A1 (en) | 2015-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106325608B (en) | Touch display panel and touch display device | |
| CN103439844A (en) | Array substrate, display device and method for manufacturing array substrate | |
| CN103293811B (en) | A kind of array base palte and preparation method thereof, display unit | |
| CN106158882A (en) | A kind of display device, display floater, array base palte and preparation method thereof | |
| CN102937767B (en) | The method for making of array base palte, display device and array base palte | |
| CN104730790B (en) | Liquid crystal display device, liquid crystal display and preparation method thereof and dim spot operational method | |
| CN104699321A (en) | Touch display substrate and touch display device | |
| CN203365869U (en) | Array substrate and display device | |
| CN103728804B (en) | A kind of motherboard, array base palte and preparation method, display device | |
| CN103474436B (en) | A kind of array base palte and preparation method thereof, display unit | |
| CN104731412A (en) | Array substrate, display panel and display device | |
| CN104570515A (en) | Array substrate and manufacture method thereof, display panel and display device | |
| CN102708771B (en) | Array substrate, manufacturing method and display unit thereof | |
| CN102315165B (en) | Edge electric field type liquid crystal display array substrate and manufacture method thereof | |
| CN104680957B (en) | Display device and its manufacture and method of testing | |
| CN106094272B (en) | A kind of display base plate, its production method and display device | |
| CN103560134A (en) | Array substrate, manufacturing method thereof and display device | |
| CN104932128A (en) | Array base board, display device, maintenance method and manufacturing method | |
| CN107490913A (en) | Array base palte, display panel and display device | |
| CN104716147B (en) | A kind of tft array substrate and preparation method thereof, display device | |
| KR102078807B1 (en) | Liquid crystal display | |
| CN103715202A (en) | Array substrate, array substrate manufacturing method and display device | |
| CN102945846A (en) | Array substrate, manufacturing method thereof and display device | |
| CN104319274A (en) | Array substrate, manufacturing method of array substrate, display panel and display device | |
| WO2014015636A1 (en) | Array substrate, method for manufacturing same, and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |