CN102708771B - Array substrate, manufacturing method and display unit thereof - Google Patents
Array substrate, manufacturing method and display unit thereof Download PDFInfo
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- CN102708771B CN102708771B CN201210149512.5A CN201210149512A CN102708771B CN 102708771 B CN102708771 B CN 102708771B CN 201210149512 A CN201210149512 A CN 201210149512A CN 102708771 B CN102708771 B CN 102708771B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The invention discloses an array substrate, a manufacturing method and a display unit thereof, relates to the design field of display units, and is used for achieving testing of signals of any data line in the display unit. The array substrate comprises a display area and a non-display area, and the non-display area comprises at least one data line lead pattern unit; a plurality of data line leads are arranged in each of the at least one data line lead pattern unit, the data line lead comprises a first connecting portion which is used for being electrically connected with a chip, at least one test line is further arranged in each of the at least one data line lead pattern unit, each of the at least one test line is crosswise arranged with all data line leads in a same one data line lead pattern unit, and insulation layers are arranged among the test lines and the data line leads; wherein the test line comprises a second connecting portion which is used for being electrically connected with the chip, and is connected with test points of a printed circuit board through the chip. The array substrate, the manufacturing method and the display unit thereof are used for designing and manufacturing array substrates.
Description
Technical field
The present invention relates to the design field of display device, particularly relate to a kind of array base palte and manufacture method, display device.
Background technology
As shown in Figure 1, the display panel structure of current TFT-LCD (Thin Film Transistor (TFT)-liquid crystal display) comprising: the array base palte 11 be shaped to box and color membrane substrates 12, and the liquid crystal between two substrates.Because the data line on array base palte and grid line all need to be connected driving circuit, so array base palte 11 is more bigger than color membrane substrates 12, to leave the space connected needed for driving circuit.Above-mentioned two substrates is by fluid sealant adhesion, and liquid crystal is filled in the inner side of fluid sealant, and for showing image, so the region inside fluid sealant on array base palte can be called viewing area, other regions are called non-display area.For clear description, the data line being positioned at non-display area is called data cable lead wire, the grid line being positioned at non-display area is called that grid line goes between.Further describe for data cable lead wire below.
With reference to the enlarged drawing shown in figure 2, at non-display area, one group of compact arranged data cable lead wire region is called a data line lead pattern unit, and the data cable lead wire 31 in each data line lead pattern unit all needs a chip 13 and PCB (Printed Circuit Board, printed circuit board (PCB)) 14 to be electrically connected; Wherein, this chip bearing has IC (integrated circuit, integrated circuit), and the comparatively normal chip used is COF (Chip On Film, thin film chip).
For realizing the test to data line signal, method general at present utilizes the cabling design on chip, is electrically connected, the data line corresponding to each chip both sides of the edge to realize the test to data line signal with the test point on pcb board 14.Obviously, said method is only achieve test function to other data line individual, so just brings inconvenience to the performance test of later stage failure analysis and panel.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacture method, display device, in order to realize the test to data line signal arbitrary in display device, thus improve the work efficiency of later stage failure analysis and panel performance test.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, the invention provides a kind of array base palte, comprising: viewing area and non-display area, described non-display area comprises at least one data line lead pattern unit; A plurality of data lines lead-in wire is provided with in each described data line lead pattern unit, described data cable lead wire comprises the first connecting portion, this first connecting portion is used for connecing with chip electrical, at least one p-wire is also provided with in each described data line lead pattern unit, every bar p-wire is positioned at same data line lead pattern unit all data cable lead wires with it are arranged in a crossed manner, and are provided with insulation course between described p-wire and described data cable lead wire; Wherein, described p-wire comprises the second connecting portion, and this second connecting portion is used for connecing with described chip electrical, and connects the test point of printed circuit board (PCB) by described chip.
On the other hand, present invention also offers a kind of manufacture method of array base palte, comprising:
Underlay substrate makes grid line metallic film, and forms grid line metal layer pattern by patterning processes, described grid line metal layer pattern comprises: grid line, grid line go between and be positioned at least one p-wire of each data line lead pattern unit; Described p-wire comprises the second connecting portion, and this second connecting portion is used for connecing with chip electrical, and connects the test point of printed circuit board (PCB) by described chip;
Continue to form gate insulation layer, active layer, data wire metal layer pattern; Described data wire metal layer pattern comprises: data line, data cable lead wire, and wherein, described data cable lead wire comprises the first connecting portion, and this first connecting portion is used for connecing with chip electrical;
Make passivation layer, and at least form via hole in the position of described first connecting portion and described second connecting portion by patterning processes;
Make the first transparent conductive film, and form the first transparency electrode, the first contact site be connected with described first connecting portion, the second contact site of being connected with described second connecting portion by patterning processes.
Again on the one hand, present invention also offers a kind of display device, comprising: color membrane substrates and above-mentioned array base palte, chip, printed circuit board (PCB);
First connecting portion and second connecting portion of described chip and described array base palte are electrically connected, and are electrically connected with the test point of described printed circuit board (PCB) by the second connecting portion of described chip.
A kind of array base palte that the embodiment of the present invention provides and manufacture method, display device, at least one p-wire is provided with in each described data line lead pattern unit, and every bar p-wire is positioned at same data line lead pattern unit all data cable lead wires with it are arranged in a crossed manner, like this when needing to test the signal of a wherein data line, the data cable lead wire of this data line and p-wire are coupled together, disconnects after completing test; Thus the test that can realize data line signal arbitrary in display device, and then improve the work efficiency of later stage failure analysis and panel performance test.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of display panel in prior art;
Fig. 2 is the close-up schematic view of Fig. 1;
Fig. 3 is the structural representation of a kind of array base palte provided by the invention;
Fig. 4 is a kind of close-up schematic view of Fig. 3;
Fig. 5 is the another kind of close-up schematic view of Fig. 3;
Fig. 6 is another close-up schematic view of Fig. 3;
Fig. 7 is the close-up schematic view of another kind of array base palte provided by the invention;
Sectional view in the manufacture method process that Fig. 8-Figure 12 is array base palte shown in Fig. 4.
Reference numeral:
11-array base palte, 12-color membrane substrates, 13-chip, 14-PCB plate;
21-viewing area, 22-non-display area, 221-data line lead pattern unit, 222-grid line lead pattern unit;
31-data cable lead wire, 311-first connecting portion, 32-grid line goes between, 33-p-wire, 331-second connecting portion;
41-first contact site, 43-second contact site;
51-gate insulation layer, 52-passivation layer.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Fig. 3-Fig. 7, embodiments provide a kind of array base palte, comprising: viewing area 21 and non-display area 22, described non-display area 22 comprises at least one data line lead pattern unit 221; Be provided with a plurality of data lines lead-in wire 31 in each described data line lead pattern unit 221, described data cable lead wire 31 comprises the first connecting portion 311, and this first connecting portion 311 is for connecing with chip electrical.Certainly, non-display area also comprises at least one grid line lead pattern unit 222, is provided with many grid line lead-in wires 32 in each grid line lead pattern unit 222.
In all embodiments of the present invention, viewing area refers to that array base palte is to the region be in during box inside fluid sealant, and this region is used for filling liquid crystal to show image, and other regions are called non-display area.For convenience of describing, the part of data line in viewing area is still called data line, is then called data cable lead wire in the part of non-display area, equally, the part of grid line in viewing area is still called grid line, is then called that grid line goes between in the part of non-display area.By in non-display area, one group of compact arranged data cable lead wire region is called a data line lead pattern unit, and one group of compact arranged grid line lead-in wire region is called a grid line lead pattern unit.
In embodiments of the present invention, mainly improve in data line lead pattern unit 221.At least one p-wire 33 is also provided with in each described data line lead pattern unit 221, every bar p-wire 33 is positioned at same data line lead pattern unit all data cable lead wires 31 with it are arranged in a crossed manner, and are provided with insulation course between described p-wire 33 and described data cable lead wire 31; Wherein, described p-wire 33 comprises the second connecting portion 331, and this second connecting portion 331 for connecing with described chip electrical, and connects the test point of printed circuit board (PCB) by described chip.
It should be noted that, insulation course refers to the Rotating fields with insulating effect.
Fig. 3-Fig. 6 is to be provided with a p-wire, and Fig. 7 is to arrange two p-wires.Owing to arranging n (n >=1) bar p-wire 33, just can test the signal of n bar data line, the p-wire that is arranged is more simultaneously, and the data line signal simultaneously can tested just can be more.But, consider the restriction in data line lead pattern unit space, one or two p-wires be preferably set.
The array base palte that the embodiment of the present invention provides, at least one p-wire is provided with in each described data line lead pattern unit, and every bar p-wire is positioned at same data line lead pattern unit all data cable lead wires with it are arranged in a crossed manner, like this when needing to test the signal of a wherein data line, the data cable lead wire of this data line and p-wire are coupled together, disconnects after completing test; Thus the test that can realize data line signal arbitrary in display device, and then improve the work efficiency of later stage failure analysis and panel performance test.
Further, the second connecting portion 331 of described p-wire 33 is positioned at one end of this p-wire 33.When not changing data cable lead wire distribution, p-wire can be set up like this.
Further, in same data line lead pattern unit, the crossover location of p-wire 33 and data cable lead wire 31 can reference diagram 4, Fig. 7 is in the outside of the first connecting portion 311 of this data cable lead wire 31, also can overlap with the first connecting portion 311 of data cable lead wire 31 by reference diagram 5, also can reference diagram 6 in the inner side of the first connecting portion 311 of data cable lead wire 31.In embodiments of the present invention, for a data cable lead wire 31, with the first connecting portion 311 for boundary is divided into both sides, wherein the side near array base palte edge is called the outside of the first connecting portion 311, opposite side is called the inner side of the first connecting portion 311.
With reference to figure 5, in same data line lead pattern unit, the crossover location of p-wire 33 and data cable lead wire 31 overlaps with the first connecting portion 311 of data cable lead wire.When needs are tested data line signal, according to distance the second connecting portion 331 from as far as near order (namely diagram order) from left to right, successively the signal of each data cable lead wire 31 is tested.For the signal testing of a wherein data cable lead wire 31, be specially, first laser technology is adopted to be connected with the crossover location (i.e. posetionof weld) of data cable lead wire 31 to be tested at both by p-wire 33, to make it possible to the test point signal of data cable lead wire 31 to be tested being incorporated into pcb board; After completion of testing, the p-wire 33 utilizing laser technology this to be completed between the data cable lead wire 31 of test and next data cable lead wire 31 to be tested is needed to cut off.
With reference to figure 6, in same data line lead pattern unit, the crossover location of p-wire 33 and data cable lead wire 31 is in the inner side of the first connecting portion 311 of data cable lead wire.When needs are tested data line signal, with reference to above-mentioned method of testing, repeat no more.
Preferably, with reference to figure 4, Fig. 7 in same data line lead pattern unit, the crossover location of p-wire 33 and data cable lead wire 31 is positioned at the outside of the first connecting portion 311 of this data cable lead wire.When needing to test the arbitrary data line signal in this data line lead pattern unit, laser technology is then adopted to be connected with the crossover location (i.e. posetionof weld) of data cable lead wire 31 to be tested at both by p-wire 33, after completion of testing, need to utilize laser technology to be switched by the data cable lead wire 31 between this crossover location and the first connecting portion 311.This scheme without the need to carrying out the test of data line signal in a fixed order, more flexibly.
Further, the grid line in described p-wire and described viewing area is arranged with layer.So-called to arrange at least two kinds of patterns with layer, refer to the structure of at least two kinds of pattern setting on same layer film, concrete, be the thin film made in same material by patterning processes is formed described at least two kinds of patterns.So just change the pattern that patterning processes is formed, and without the need to increasing making step.
Preferably, described p-wire is parallel with the grid line in viewing area.
Because general grid line, data cable lead wire are all covered by least one layer insulating, therefore data cable lead wire, the p-wire that arranges with layer with grid line all need through insulation course, can connect chip; Therefore in embodiments of the present invention, preferably, described first connecting portion 311 connects the first contact site 41 by via hole, and described first connecting portion 311 comprises for connecing with chip electrical: described first connecting portion 311 is for connecing with chip electrical by described first contact site 41; Described second connecting portion 331 connects the second contact site 43 by via hole, and described second connecting portion 331 comprises for connecing with described chip electrical: described second connecting portion 331 is for connecing with described chip electrical by described second contact site 43.
Wherein, the material of the first contact site 41 and the second contact site 43 is conductive material.
Preferred further, described first contact site 41, described second contact site 43 are arranged with layer with the top transparent electrode in described viewing area.It should be noted that, top transparent electrode refers to the transparency electrode of array base palte farthest away from underlay substrate, namely according to the transparency electrode that making order finally completes.Concrete, for the array base palte being only provided with a kind of transparency electrode, the such as array base palte of TN (Twist Nematic, twisted-nematic) type LCD, it comprises pixel electrode, and now, this transparency electrode is top transparent electrode.For the array base palte being provided with two kinds of transparency electrodes (pixel electrode and public electrode), such as FFS (FringeField Switching, fringe field switching) array base palte of type LCD, now, top transparent electrode is then the transparency electrode away from underlay substrate.
The embodiment of the present invention additionally provides a kind of manufacture method of array base palte, it should be noted that, the accompanying drawing of this manufacture method is for the cut-open view at the C-C tangent plane place of Fig. 4.Described manufacture method comprises:
S101, as shown in Figure 8, underlay substrate makes grid line metallic film, and forming grid line metal layer pattern by patterning processes, described grid line metal layer pattern comprises: grid line, grid line go between and be positioned at least one p-wire of each data line lead pattern unit; Described p-wire comprises the second connecting portion 331, and this second connecting portion 331 for connecing with chip electrical, and connects the test point of printed circuit board (PCB) by described chip;
S102, as shown in Figure 9, continues to form gate insulation layer 51, active layer;
S103, as shown in Figure 10, forms data wire metal layer pattern; Described data wire metal layer pattern comprises: data line, data cable lead wire, and wherein, described data cable lead wire comprises the first connecting portion 311, and this first connecting portion 311 is for connecing with chip electrical;
S104, as shown in figure 11, makes passivation layer 52, and at least forms via hole in the position of described first connecting portion 311 and described second connecting portion 331 by patterning processes;
S104, as shown in figure 12, make the first transparent conductive film, and form the first transparency electrode, the first contact site 41 be connected with described first connecting portion 311, the second contact site 43 of being connected with described second connecting portion 331 by patterning processes.
It should be noted that, only embody the structure at each A-A tangent plane place in each accompanying drawing, although other parts fail to embody in the example shown, those skilled in the art can know the structure determining whole array base palte according to foregoing description.
Above-mentioned is the manufacture method of the array base palte of TN type LCD, and comprise the array base palte of two kinds of transparency electrodes, the such as array base palte of FFS type LCD, its manufacture method, between the described active layer of above-mentioned formation and described data wire metal layer pattern, namely at least also comprises between step S102 and S103:
S105, form the second transparent conductive film, and form the second transparency electrode by patterning processes.
The embodiment of the present invention additionally provides a kind of display device, comprising: color membrane substrates and above-mentioned any one array base palte chip, printed circuit board (PCB);
First connecting portion and second connecting portion of described chip and described array base palte are electrically connected, and are electrically connected with the test point of described printed circuit board (PCB) by the second connecting portion of described chip.
The array base palte made according to above-mentioned manufacture method and comprise the display device of this array base palte, when needing to test the signal of a wherein data line, coupling together the data cable lead wire of this data line and p-wire, disconnecting after completing test; Thus the test that can realize data line signal arbitrary in display device, and then improve the work efficiency of later stage failure analysis and panel performance test.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (9)
1. an array base palte, comprising: viewing area and non-display area, and described non-display area comprises at least one data line lead pattern unit; Be provided with a plurality of data lines lead-in wire in each described data line lead pattern unit, described data cable lead wire comprises the first connecting portion, and this first connecting portion is used for connecing with chip electrical, it is characterized in that,
At least one p-wire is also provided with in each described data line lead pattern unit, every bar p-wire is positioned at same data line lead pattern unit all data cable lead wires with it are arranged in a crossed manner, and are provided with insulation course between described p-wire and described data cable lead wire; Wherein, described p-wire comprises the second connecting portion, and this second connecting portion is used for connecing with described chip electrical, and connects the test point of printed circuit board (PCB) by described chip;
In same data line lead pattern unit, the crossover location of p-wire and data cable lead wire is positioned at the outside of the first connecting portion of this data cable lead wire.
2. array base palte according to claim 1, is characterized in that, the second connecting portion of described p-wire is in one end of this p-wire.
3. array base palte according to claim 1 and 2, is characterized in that, the grid line in described p-wire and described viewing area is arranged with layer.
4. array base palte according to claim 3, is characterized in that, described p-wire is parallel with described grid line.
5. array base palte according to claim 4, it is characterized in that, described first connecting portion connects the first contact site by via hole, and described first connecting portion is used for connecing with chip electrical comprising: described first connecting portion is used for being connect by described first contact site and chip electrical;
Described second connecting portion connects the second contact site by via hole, and described second connecting portion is used for connecing with described chip electrical comprising: described second connecting portion is used for being connect by described second contact site and described chip electrical.
6. array base palte according to claim 5, is characterized in that, the top transparent electrode in described first contact site, described second contact site and described viewing area is arranged with layer.
7. a manufacture method for array base palte, is characterized in that, comprising:
Underlay substrate makes grid line metallic film, and forms grid line metal layer pattern by patterning processes, described grid line metal layer pattern comprises: grid line, grid line go between and be positioned at least one p-wire of each data line lead pattern unit; Described p-wire comprises the second connecting portion, and this second connecting portion is used for connecing with chip electrical, and connects the test point of printed circuit board (PCB) by described chip;
Continue to form gate insulation layer, active layer, data wire metal layer pattern; Described data wire metal layer pattern comprises: data line, data cable lead wire, and wherein, described data cable lead wire comprises the first connecting portion, and this first connecting portion is used for connecing with chip electrical; In same data line lead pattern unit, the crossover location of p-wire and data cable lead wire is positioned at the outside of the first connecting portion of this data cable lead wire;
Make passivation layer, and at least form via hole in the position of described first connecting portion and described second connecting portion by patterning processes;
Make the first transparent conductive film, and form the first transparency electrode, the first contact site be connected with described first connecting portion, the second contact site of being connected with described second connecting portion by patterning processes.
8. manufacture method according to claim 7, is characterized in that, between the described active layer of formation and described data wire metal layer pattern, at least also comprises:
Form the second transparent conductive film, and form the second transparency electrode by patterning processes.
9. a display device, is characterized in that, comprising: color membrane substrates and the array base palte described in any one of claim 1-6, chip, printed circuit board (PCB);
First connecting portion and second connecting portion of described chip and described array base palte are electrically connected, and are electrically connected with the test point of described printed circuit board (PCB) by the second connecting portion of described chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210149512.5A CN102708771B (en) | 2012-05-14 | 2012-05-14 | Array substrate, manufacturing method and display unit thereof |
| PCT/CN2012/084396 WO2013170594A1 (en) | 2012-05-14 | 2012-11-09 | Array substrate, manufacturing method and display unit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210149512.5A CN102708771B (en) | 2012-05-14 | 2012-05-14 | Array substrate, manufacturing method and display unit thereof |
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| CN102708771A CN102708771A (en) | 2012-10-03 |
| CN102708771B true CN102708771B (en) | 2015-04-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102708771B (en) * | 2012-05-14 | 2015-04-15 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display unit thereof |
| CN103280177B (en) * | 2012-12-05 | 2016-05-18 | 上海中航光电子有限公司 | Gate drivers and detection method thereof |
| CN104133333A (en) * | 2014-07-22 | 2014-11-05 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method |
| CN104332475B (en) * | 2014-09-02 | 2018-09-21 | 合肥鑫晟光电科技有限公司 | Array substrate and preparation method thereof, display device |
| CN104777637B (en) * | 2015-05-08 | 2018-01-02 | 上海中航光电子有限公司 | Array base palte, touch control display apparatus and its method of testing |
| CN106409192A (en) * | 2015-07-29 | 2017-02-15 | 南京瀚宇彩欣科技有限责任公司 | Display panel circuit module and test method thereof |
| CN109239999B (en) * | 2018-11-12 | 2020-12-04 | 惠科股份有限公司 | Flexible circuit board, display panel and display device |
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| KR101293569B1 (en) * | 2006-08-03 | 2013-08-06 | 삼성디스플레이 주식회사 | Flexible member and liquid crystal display device having the same |
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| CN102708771B (en) * | 2012-05-14 | 2015-04-15 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display unit thereof |
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| CN102236179A (en) * | 2010-05-07 | 2011-11-09 | 北京京东方光电科技有限公司 | Thin film transistor-liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
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