CN203365869U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203365869U CN203365869U CN 201320490654 CN201320490654U CN203365869U CN 203365869 U CN203365869 U CN 203365869U CN 201320490654 CN201320490654 CN 201320490654 CN 201320490654 U CN201320490654 U CN 201320490654U CN 203365869 U CN203365869 U CN 203365869U
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Abstract
The utility model provides an array substrate and a display device. The array substrate comprises a display zone and a peripheral zone on the periphery of the display zone, wherein at least transparent conductive layers, grid lines and data lines are arranged in the display zone; a plurality of grid line leads which are connected to the grid lines are distributed in a first part region of the peripheral zone; a first virtual transparent conductive layer is arranged in a second part region of the peripheral zone which is free from the grid line leads, and the first virtual transparent conductive layer is on the same layer with the transparent conductive layers. The array substrate provided by the utility model, through the first virtual transparent conductive layer which is arranged in the peripheral zone and is on the same layer with the transparent conductive layers in the display zone, can solve the problem that the transparent conductive layers are uneven on central and edge positions of the display zone, and can reduce generation of adverse spots; the array substrate can not increase the load of the grid lines.
Description
Technical field
The utility model relates to the display technique field, relates in particular to a kind of array base palte and display device.
Background technology
Liquid crystal display is current flat-panel monitor commonly used, and wherein TFT-LCD (Thin Film-Transistor Liquid Crystal Display, Thin Film Transistor-LCD) is the main product in liquid crystal display.Liquid crystal panel is the vitals of liquid crystal display, existing display panels comprises two substrates: color film (CF) substrate and array (Array) substrate, the surrounding of two substrates to box, is provided with the liquid crystal layer that liquid crystal material forms by the sealing frame between two substrates.
Be illustrated in figure 1 the structural representation of the array base palte of existing TFT-LCD panel.Usually liquid crystal panel is divided into viewing area (AA) and is formed at the peripheral neighboring area B in viewing area (AA), as shown in Figure 1, the viewing area of array base palte is distributed with grid line arranged in a crossed manner 10 and data line 20, the adjacent both sides of array base palte are respectively data electrode side and gate electrode side, wherein in the data electrode side, corresponding neighboring area B is distributed with many single data lead-in wires 21, data lead 21 1 end connection data lines 20, the other end is connected with data electrode 22, array base palte has binding (Bonding) zone of covering brilliant thin-film package plate (data COF) 23 for pasting data in the data electrode side, data electrode 22 is in the Bonding zone and data drive circuit (data I C) 24 and pcb board (Printed Circuit Board that paste data COF23, printed circuit board) 25 connect, neighboring area B corresponding to data electrode side also is distributed with public electrode connecting line 26(COM electrode connecting line), be used for connecting two adjacent data driving circuits 24, in gate electrode side, corresponding neighboring area B is distributed with many grid line lead-in wires 11, one end of grid line lead-in wire 11 connects grid line 10, the other end connects grid 12, array base palte has binding (Bonding) zone of covering brilliant thin-film package plate (grid COF) 13 for pasting grid in gate electrode side, grid 12 is connected with gate driver circuit (grid IC) 14 in binding (Bonding) zone that pastes grid and cover brilliant thin-film package plate (grid COF) 13, in gate electrode side, corresponding neighboring area B also is distributed with control signal lead-in wire (the PLG signal wire) 15 for connecting PCB board 25 and two gate driver circuits 14.In addition, also be provided with pixel electrode 30 and the public electrode (not shown) formed by transparency conducting layer on array base palte.
In order to increase transmitance, now the width W (width) of the transparency conducting layer (ITO layer) of the striated on array base palte/area S (space) becomes 4/6,3/5,2/6 successively from original 5/5, and the width of the transparency conducting layer of striated is more and more less.Along with diminishing of the transparency conducting layer width of striated, inhomogeneous phenomenon may occur in the middle position of effective display area territory (AA) and the transparency conducting layer of marginal position, will cause so the bad generation of spot (mura).
The reason that produces this phenomenon is, transparency conducting layer is covered in viewing area (AA), on array base palte, the transparency conducting layer of striated is to form by photoetching process, narrower in width due to the transparency conducting layer of striated, through overexposure, after development, in the process of etching, the center of viewing area (AA) is different from the etching liquid wear rate of marginal position, cause the etching liquid density unevenness, finally cause the center of viewing area (AA) after etching and the transparency conducting layer (ITO) inhomogeneous (live width has nuance) of marginal position, thereby cause mura bad.
In order to address this problem, current method is the virtual transparency conducting layer (dummy ITO) 40 with the same layer of transparency conducting layer of striated in neighboring area B setting.Like this, in photoetching process, because the neighboring area B of the marginal position periphery of viewing area (AA) also has transparency conducting layer, that is to say, the edge of transparency conducting layer is positioned at neighboring area and is not positioned at the marginal position of viewing area (AA), the middle position of (AA) is identical with the wear rate of marginal position in viewing area can to guarantee like this etching liquid, etching liquid concentration is even, thus make transparency conducting layer in viewing area the middle position of (AA) and marginal position evenly (live width indifference).
As shown in Figure 2, current virtual transparency conducting layer 40 covers on the grid line lead-in wire 11 of neighboring area B, although can avoid like this generation of the transparency conducting layer phenomenon in uneven thickness of viewing area and neighboring area, but thisly be designed with a shortcoming, virtual transparency conducting layer covers on grid line lead-in wire 11, can cause the load on grid line 10 to strengthen, postponing (delay) increases, and the increase of delay can cause pixel charge rate deficiency.
The utility model content
The purpose of this utility model is to provide a kind of array base palte, display panel and display device, in the problem of the transparency conducting layer uneven thickness that solves viewing area and neighboring area, also can not increase the grid line load.
Technical scheme provided by the utility model is as follows:
A kind of array base palte, comprise viewing area and the neighboring area that is positioned at periphery, described viewing area, described viewing area at least is provided with transparency conducting layer, grid line and data line, and first's areal distribution of described neighboring area has many grid line lead-in wires that are connected with described grid line
Second portion region division at the described grid line lead-in wire of not arranging of described neighboring area has the first virtual transparency conducting layer, and the described first virtual transparency conducting layer and the same layer setting of described transparency conducting layer.
Further, at least one side of described array base palte is provided with printed circuit board (PCB);
Every described grid line end that goes between connects described grid line, the other end is connected with gate driver circuit in the first binding zone that grid covers brilliant thin-film package plate that is covered with of described array base palte, and not arranging on the second portion zone that described grid line goes between of described neighboring area is distributed with the many control signal connecting lines for described printed circuit board (PCB) is electrically connected to described gate driver circuit;
The described first virtual transparency conducting layer is arranged at the position corresponding with described control signal connecting line, and the described first virtual transparency conducting layer is electrically connected to described control signal connecting line.
Further, the described first virtual transparency conducting layer comprises that shape is complementary with the shape of each described control signal connecting line respectively, and with a plurality of first virtual electrically conducting transparent line of described control signal connecting line in different layers.
Further, described array base palte be covered with grid cover brilliant thin-film package plate first the binding region division the first conductive electrode layer and the first medium layer that can be connected with gate driver circuit arranged, described first medium layer is provided with the first via hole, and wherein said control signal connecting line and the described first virtual electrically conducting transparent line are electrically connected to described the first conductive electrode layer by the first via hole on described first medium layer respectively.
Further, at least one side of described array base palte is provided with printed circuit board (PCB);
The second portion zone that described grid line lead-in wire is not set of described neighboring area also is distributed with many single data lead-in wires, every described data lead one end connects described data line, the other end covers the second binding zone of brilliant thin-film package plate and is connected with data drive circuit in the data that are covered with of described array base palte, described data drive circuit has two at least, and the second portion zone of described neighboring area also is distributed with for the many public electrode connecting lines by being electrically connected between adjacent two described data drive circuits;
Position corresponding with described public electrode connecting line on described neighboring area is provided with the second virtual transparency conducting layer, the described second virtual transparency conducting layer and described transparency conducting layer arrange with layer, and the described second virtual transparency conducting layer is electrically connected to described public electrode connecting line.
Further, the described second virtual transparency conducting layer comprises that shape is complementary with the shape of each described public electrode connecting line respectively, and with a plurality of second virtual electrically conducting transparent line of described public electrode connecting line in different layers.
Further, described array base palte be covered with grid cover brilliant thin-film package plate first the binding region division the second conductive electrode layer and the second medium layer that can be connected with data drive circuit arranged, described second medium layer is provided with the second via hole, and described public electrode connecting line and the described second virtual electrically conducting transparent line are electrically connected to described the second conductive electrode layer by the second via hole on described second medium layer respectively.
A kind of display device, it comprises array base palte as above.
The beneficial effect that the utility model brings is as follows:
Array base palte provided by the utility model, by the first virtual transparency conducting layer with the same layer of transparency conducting layer of viewing area in the neighboring area setting, can solve the inhomogeneous problem of transparency conducting layer of the middle position of viewing area and marginal position, reduce the bad generation of spot; And the first virtual transparency conducting layer of neighboring area is arranged at the zone that the grid line lead-in wire is not set, with the grid line lead-in wire, without overlapping part, can not increase the load of grid line.
The accompanying drawing explanation
Fig. 1 means the schematic diagram of array base palte in prior art;
Fig. 2 means the position schematic diagram of virtual transparency conducting layer in prior art;
Fig. 3 means the schematic diagram of array base palte provided by the utility model.
Embodiment
Below in conjunction with accompanying drawing, principle of the present utility model and feature are described, example, only for explaining the utility model, is not intended to limit scope of the present utility model.
As shown in Figure 3, the utility model provides a kind of array base palte, comprise viewing area AA and the neighboring area B that is positioned at AA periphery, described viewing area, described viewing area AA at least is provided with the transparency conducting layer that is striated, grid line 100 and data line 200, first's areal distribution at the described neighboring area B of gate electrode side has many grid line lead-in wires 101 that are connected with described grid line 100, second portion region division at the described grid line lead-in wire 101 of not arranging of described neighboring area B has the first virtual transparency conducting layer 400, and the described first virtual transparency conducting layer 400 arranges with layer with described transparency conducting layer.
Such scheme, by the first virtual transparency conducting layer 400 of transparency conducting layer in same layer with viewing area AA in neighboring area B setting, can solve the inhomogeneous problem of transparency conducting layer of the middle position of viewing area AA and marginal position, reduce the bad generation of spot; And the first virtual transparency conducting layer 400 of neighboring area B is arranged at the zone that grid line lead-in wire 101 is not set, with grid line lead-in wire 101, without overlapping part, can not increase the load of grid line 100.
In addition, also it should be noted that, for the FFS technology, transparency conducting layer on array base palte can be as required as pixel electrode or public electrode, when pixel electrode is the striated structure, the described first virtual transparency conducting layer arranges with layer with described pixel electrode, and when public electrode is the striated structure, the described first virtual transparency conducting layer arranges with layer with described public electrode.
The preferred embodiment of array base palte provided by the utility model below is described.Figure 3 shows that the structural representation of a kind of preferred embodiment of array base palte provided by the utility model.The data electrode side of common described array base palte and at least one side in gate electrode side are provided with printed circuit board (PCB).In the present embodiment, the data electrode side that the printed circuit board (PCB) of take is arranged at array base palte illustrates the preferred embodiment of array base palte provided by the utility model as example.
As shown in Figure 3, in the present embodiment, array base palte is provided with printed circuit board (PCB) 205 in the data electrode side, be distributed with many grid line lead-in wires 101 at its neighboring area of gate electrode side B, every described grid line lead-in wire 101 1 ends connect described grid line 100, the other end connects gate electrode 102, and gate electrode 102 covers brilliant thin-film package plate 103 by grid and is connected with gate driver circuit 104 in the first binding zone that grid covers brilliant thin-film package plate 103 of being covered with of described array base palte;
The second portion zone that described grid line lead-in wire 101 is not set of described neighboring area B also is distributed with many single data lead-in wires 201 in the data electrode side, every described data lead 201 1 ends connect described data line 200, other end connection data electrode 202, data electrode 202 covers the second binding zone of brilliant thin-film package plate and covers brilliant thin-film package plate 203 by data and be connected with data drive circuit 204 and printed circuit board (PCB) 205 in the data that are covered with of described array base palte;
Also be distributed with many control signal connecting lines 105 on the second portion zone of the described grid line lead-in wire 101 of not arranging of the described neighboring area B of gate electrode side, described control signal connecting line 105 is for described printed circuit board (PCB) 205 is electrically connected to described gate driver circuit 104, to carry out the signal transmission;
Wherein in the present embodiment, gate driver circuit 104 and grid cover brilliant thin-film package plate 103 and have respectively two at least, data drive circuit 204 and data are covered brilliant thin-film package plate 203 and are also had respectively two at least, because printed circuit board (PCB) 205 is arranged at the data electrode side, therefore, in the present embodiment, at least two paste grid cover brilliant thin-film package plate 103 first the binding zone between, and at least one pastes the first binding zone that grid covers brilliant thin-film package plate 103 and pastes data with at least one and cover second of brilliant thin-film package plate 203 and bind between zone and be distributed with described control signal connecting line 105, preferred in the present embodiment, the described first virtual transparency conducting layer 400 is arranged at the position corresponding with described control signal connecting line 105, and the described first virtual transparency conducting layer 400 is electrically connected to described control signal connecting line 105.
In such scheme, the second portion zone that the neighboring area B of common array base palte does not arrange grid line lead-in wire 101 can be furnished with the control signal connecting line 105 that for making, can carry out the signal transmission between gate driver circuit 104 and printed circuit board (PCB) 205, in the present embodiment, the first virtual transparency conducting layer 400 is arranged on to the position corresponding with control signal connecting line 105, and make the first virtual transparency conducting layer 400 be electrically connected to control signal connecting line 105, the first virtual transparency conducting layer 400 will be identical with the current potential of control signal connecting line 105 thus, but can not affect the load of control signal connecting line 105, and the first virtual transparency conducting layer 400 does not have overlapping with grid line lead-in wire 101 fully, can not go between to grid line 101 influential, can not increase the load of grid line 100.
In the present embodiment, preferred, the described first virtual transparency conducting layer 400 comprises that shape is complementary with the shape of each described control signal connecting line 105 respectively, and with a plurality of first virtual electrically conducting transparent line of described control signal connecting line 105 in different layers.That is to say, in the present embodiment, the shape of the preferred first virtual transparency conducting layer 400, size and control signal connecting line 105 are in full accord.
Due to control signal connecting line 105 and the first virtual electrically conducting transparent line in different layers, below, in explanation array base palte provided by the utility model, the described first virtual transparency conducting layer 400 realizes with described control signal connecting line 105 a kind of preferred implementation be electrically connected to.
In this preferred embodiment, the first virtual transparency conducting layer 400 and described control signal connecting line 105 are electrically connected in the first binding zone that is covered with described grid and covers brilliant thin-film package plate 103.Particularly, usually, be covered with described grid cover brilliant thin-film package plate 103 first the binding region division the first conductive electrode layer and the first medium layer that can be connected with gate driver circuit 104 arranged, described first medium layer is provided with the first via hole, and the end of wherein said control signal connecting line 105 can realize being electrically connected to by the first via hole on the first medium layer and the first conductive electrode.Preferred in the present embodiment, the end of the first virtual electrically conducting transparent line directly is connected and gets final product with the first conductive electrode layer by described the first via hole, can realize thus being electrically connected between the described first virtual electrically conducting transparent line and described control signal connecting line 105, so that the described first virtual electrically conducting transparent line is identical with the current potential of described control signal connecting line 105.Should be understood that, in actual applications, the described first virtual electrically conducting transparent line realizes that with described control signal connecting line 105 mode be electrically connected to is not limited to this, can also, by via hole being set on such as insulation course and realizing being formed at other each dielectric layers between the described first virtual electrically conducting transparent line and described control signal connecting line 105, at this, will not enumerate.
In addition, in the present embodiment, as shown in Figure 2, the second portion zone of described neighboring area B also is distributed with for the many public electrode connecting lines 206 by being electrically connected between adjacent two described data drive circuits 204; Data electrode side at described neighboring area B also is provided with the second virtual transparency conducting layer 401 corresponding with described public electrode connecting line 206 positions, the described second virtual transparency conducting layer 401 arranges with layer with described transparency conducting layer, and the described second virtual transparency conducting layer 401 is electrically connected to described public electrode connecting line 206.In the present embodiment, preferably, the described second virtual transparency conducting layer 401 comprises that shape is complementary with the shape of each described public electrode connecting line 206 respectively, and with a plurality of second virtual electrically conducting transparent line of described public electrode connecting line 206 in different layers, that is to say, the shape of the second virtual transparency conducting layer 401, size and public electrode connecting line 206 are in full accord.
Due to public electrode connecting line 206 and the second virtual electrically conducting transparent line in different layers, below, in explanation array base palte provided by the utility model, the described second virtual transparency conducting layer 401 realizes with described public electrode connecting line 206 a kind of preferred implementation be electrically connected to.
In this preferred embodiment, the second virtual transparency conducting layer 401 and described control signal connecting line 105 are realized being electrically connected in the second binding zone that is covered with described grid and covers brilliant thin-film package plate 103.Usually, be covered with described data cover brilliant thin-film package plate 203 second the binding region division the second conductive electrode layer and the second medium layer that can be connected with data drive circuit 204 arranged, described second medium layer is provided with the second via hole, and the end of wherein said public electrode connecting line 206 normally realizes being electrically connected to by the second via hole on the second medium layer and the second conductive electrode.In the present embodiment, preferably, the end of the second virtual electrically conducting transparent line directly is connected and gets final product with the second conductive electrode layer by the second via hole, can realize thus being electrically connected between the described second virtual electrically conducting transparent line and described public electrode connecting line 206, so that the described second virtual electrically conducting transparent line is identical with the current potential of described public electrode connecting line 206.Should be understood that, in actual applications, the described second virtual electrically conducting transparent line realizes that with described public electrode connecting line 206 mode be electrically connected to is not limited to this, can also, by via hole being set on such as insulation course and realizing being formed at other each dielectric layers between the described second virtual electrically conducting transparent line and described public electrode connecting line 206, at this, will not enumerate.
In addition, also it should be noted that, in the preferred embodiment more than provided, printed circuit board (PCB) 205 is arranged at the data electrode side of array base palte, and in actual applications, printed circuit board (PCB) 205 also may be arranged at the gate electrode side of array base palte or be arranged at the data electrode side and grid line 100 electrode sides simultaneously.Be arranged at the array base palte of gate electrode side for printed circuit board (PCB) 205, its neighboring area B does not likely need to arrange control signal connecting line 105, and now in gate electrode side, the described first virtual transparent electrode layer is arranged at the zone that grid line lead-in wire 101 is not set and gets final product.
The new also purpose of this practicality is to provide a kind of display device that comprises arraying bread board provided by the utility model.Described display device can be: any product or parts with Presentation Function such as display panels, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook.Obviously, display panel provided by the utility model and display device also have the beneficial effect that array base palte provided by the utility model brings.
It is more than preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (8)
1. an array base palte, comprise viewing area and the neighboring area that is positioned at periphery, described viewing area, described viewing area at least is provided with transparency conducting layer, grid line and data line, and first's areal distribution of described neighboring area has many grid lines lead-in wires that are connected with described grid line, it is characterized in that
Second portion region division at the described grid line lead-in wire of not arranging of described neighboring area has the first virtual transparency conducting layer, and the described first virtual transparency conducting layer and the same layer setting of described transparency conducting layer.
2. array base palte according to claim 1, is characterized in that,
At least one side of described array base palte is provided with printed circuit board (PCB);
Every described grid line end that goes between connects described grid line, the other end is connected with gate driver circuit in the first binding zone that grid covers brilliant thin-film package plate that is covered with of described array base palte, and not arranging on the second portion zone that described grid line goes between of described neighboring area is distributed with the many control signal connecting lines for described printed circuit board (PCB) is electrically connected to described gate driver circuit;
The described first virtual transparency conducting layer is arranged at the position corresponding with described control signal connecting line, and the described first virtual transparency conducting layer is electrically connected to described control signal connecting line.
3. array base palte according to claim 2, is characterized in that,
The described first virtual transparency conducting layer comprises that shape is complementary with the shape of each described control signal connecting line respectively, and with a plurality of first virtual electrically conducting transparent line of described control signal connecting line in different layers.
4. array base palte according to claim 3, is characterized in that,
Described array base palte be covered with grid cover brilliant thin-film package plate first the binding region division the first conductive electrode layer and the first medium layer that can be connected with gate driver circuit arranged, described first medium layer is provided with the first via hole, and wherein said control signal connecting line and the described first virtual electrically conducting transparent line are electrically connected to described the first conductive electrode layer by the first via hole on described first medium layer respectively.
5. array base palte according to claim 1, is characterized in that,
At least one side of described array base palte is provided with printed circuit board (PCB);
The second portion zone that described grid line lead-in wire is not set of described neighboring area also is distributed with many single data lead-in wires, every described data lead one end connects described data line, the other end covers the second binding zone of brilliant thin-film package plate and is connected with data drive circuit in the data that are covered with of described array base palte, described data drive circuit has two at least, and the second portion zone of described neighboring area also is distributed with for the many public electrode connecting lines by being electrically connected between adjacent two described data drive circuits;
Position corresponding with described public electrode connecting line on described neighboring area is provided with the second virtual transparency conducting layer, the described second virtual transparency conducting layer and described transparency conducting layer arrange with layer, and the described second virtual transparency conducting layer is electrically connected to described public electrode connecting line.
6. array base palte according to claim 5, is characterized in that,
The described second virtual transparency conducting layer comprises that shape is complementary with the shape of each described public electrode connecting line respectively, and with a plurality of second virtual electrically conducting transparent line of described public electrode connecting line in different layers.
7. array base palte according to claim 6, is characterized in that,
Described array base palte be covered with grid cover brilliant thin-film package plate first the binding region division the second conductive electrode layer and the second medium layer that can be connected with data drive circuit arranged, described second medium layer is provided with the second via hole, and described public electrode connecting line and the described second virtual electrically conducting transparent line are electrically connected to described the second conductive electrode layer by the second via hole on described second medium layer respectively.
8. a display device, is characterized in that, comprises array base palte as described as claim 1 to 6 any one.
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| CN 201320490654 CN203365869U (en) | 2013-08-12 | 2013-08-12 | Array substrate and display device |
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| CN 201320490654 CN203365869U (en) | 2013-08-12 | 2013-08-12 | Array substrate and display device |
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| CN110187574B (en) * | 2019-06-10 | 2022-04-15 | 北海惠科光电技术有限公司 | Array substrate and display panel |
| CN110473464A (en) * | 2019-07-30 | 2019-11-19 | 武汉华星光电技术有限公司 | Display panel |
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