CN110187574B - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

Info

Publication number
CN110187574B
CN110187574B CN201910497006.7A CN201910497006A CN110187574B CN 110187574 B CN110187574 B CN 110187574B CN 201910497006 A CN201910497006 A CN 201910497006A CN 110187574 B CN110187574 B CN 110187574B
Authority
CN
China
Prior art keywords
area
fan
layer
display area
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910497006.7A
Other languages
Chinese (zh)
Other versions
CN110187574A (en
Inventor
杨春辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beihai HKC Optoelectronics Technology Co Ltd
Chuzhou HKC Optoelectronics Technology Co Ltd
Original Assignee
Beihai HKC Optoelectronics Technology Co Ltd
Chuzhou HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beihai HKC Optoelectronics Technology Co Ltd, Chuzhou HKC Optoelectronics Technology Co Ltd filed Critical Beihai HKC Optoelectronics Technology Co Ltd
Priority to CN201910497006.7A priority Critical patent/CN110187574B/en
Publication of CN110187574A publication Critical patent/CN110187574A/en
Application granted granted Critical
Publication of CN110187574B publication Critical patent/CN110187574B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate

Abstract

The application relates to an array substrate and a display panel. The array substrate includes: and the at least two driving units are bound to the non-display area and used for providing driving signals for the display area. The plurality of substrate wires are positioned in the non-display area, and the same substrate wire comprises a first layer of wire and a second layer of wire which are arranged oppositely; the first layer of wiring and the second layer of wiring are both positioned between the driving units and are used for realizing signal transmission between the driving units. The fan-out wires are positioned in the non-display area, and the same fan-out wire comprises a fan-out signal wire and a fan-out virtual wire; the fan-out signal line is arranged on the same layer as one of the first layer signal line or the second layer signal line and is connected with the display area and used for transmitting the signal of the driving unit to the display area; the fan-out virtual line is arranged in the glue coating area, arranged at the same layer with the other one of the first layer signal line or the second layer signal line and arranged opposite to the fan-out signal line. The application can effectively improve the thickness uniformity of the display panel.

Description

Array substrate and display panel
Technical Field
The present application relates to the field of display technologies, and in particular, to an array substrate and a display panel.
Background
With the development of display technology, people have higher and higher requirements on display quality. The display panel generally includes an array substrate. The array substrate is provided with a display area and a non-display area. The non-display area is used for bonding and packaging the frame glue. Meanwhile, fan-out wiring and substrate wiring are arranged in the non-display area. The fan-out routing is used for transmitting signals of the driving units to the display area, and the substrate routing is used for realizing signal transmission among the driving units.
To reduce impedance, the number of layers of the substrate traces is typically large, but the fan-out traces are typically a single layer. Therefore, the thickness of the display panel formed by the frame glue packaging is uneven, and the display quality is reduced.
Disclosure of Invention
In view of the above, it is desirable to provide an array substrate and a display panel capable of improving the thickness uniformity of the display panel and further improving the display quality.
An array substrate is provided with a display area and a non-display area surrounding the display area, wherein the non-display area comprises a glue coating area used for coating frame glue, and the array substrate comprises:
at least two driving units bound to the non-display area and used for providing driving signals for the display area;
the plurality of substrate wires are positioned in the non-display area, and the same substrate wire comprises a first layer of wire and a second layer of wire which are arranged oppositely; the first layer of wiring and the second layer of wiring are both positioned between the driving units and are used for realizing signal transmission between the driving units;
the fan-out wires are positioned in the non-display area, and the same fan-out wire comprises a fan-out signal wire and a fan-out virtual wire; the fan-out signal line is arranged on the same layer as one of the first layer signal line or the second layer signal line and connected with the display area, and is used for transmitting the signal of the driving unit to the display area; the fan-out virtual line is arranged in the glue coating area, arranged at the same layer with the other one of the first layer signal line or the second layer signal line and arranged opposite to the fan-out signal line.
In one embodiment, the non-display area further comprises a balance area surrounding the display area, the balance area comprises the glue-coated area, and the fan-out virtual line extends from one side of the balance area to the other side of the balance area.
In one embodiment, the balance area further comprises a gluing error area, and the gluing error area is connected with the gluing area and is positioned on two sides of the gluing area.
In one embodiment, the distance from the side of the gluing error area far away from the balance area to the side of the gluing error area close to the balance area is 100um to 600 um.
In one embodiment, the balancing area further comprises an expansion area connecting the glue application error areas.
In one embodiment, in the balancing area, the line width of the fan-out virtual line is greater than or equal to the line width of the fan-out signal line opposite to the fan-out virtual line.
In one embodiment, the non-display area includes a routing area and a binding area surrounding the display area, the routing area is located between the display area and the binding area, the driving unit is bound to the binding area, and the balancing area is located in the routing area.
In one embodiment, the array substrate further includes a substrate and an insulating layer, the first layer of traces is located on the substrate, the insulating layer covers the first layer of traces, and the second layer of traces is located on the insulating layer.
An array substrate, having a display area and a non-display area surrounding the display area, the non-display area further comprising a routing area and a binding area surrounding the display area, the routing area being located between the display area and the binding area and comprising a balance area, the balance area comprising a glue coating area for coating frame glue, the array substrate comprising:
at least two driving units bound to the binding region and used for providing driving signals for the display region;
the plurality of substrate wires are positioned in the non-display area, and the same substrate wire comprises a first layer of wire and a second layer of wire which are arranged oppositely; the first layer of wiring and the second layer of wiring are both positioned between the driving units and are used for realizing signal transmission between the driving units;
the fan-out wires are positioned in the non-display area, and the same fan-out wire comprises a fan-out signal wire and a fan-out virtual wire; the fan-out signal line is arranged on the same layer as one of the first layer signal line or the second layer signal line and connected with the display area, and is used for transmitting the signal of the driving unit to the display area; the fan-out dummy line extends from one side of the balance area to the other side of the balance area, is arranged at the same layer as the other one of the first layer signal line or the second layer signal line, and is arranged opposite to the fan-out signal line.
A display panel comprises a color film substrate, border adhesive and any one of the array substrates, wherein the color film substrate and the array substrate are assembled in a bonding mode through the border adhesive.
The fan-out virtual lines are arranged in the gluing area of the array substrate. Therefore, the fan-out routing in the glue area not only comprises the fan-out signal lines, but also comprises fan-out virtual lines arranged opposite to the fan-out signal lines. And the fan-out signal line and one of the first layer signal line or the second layer signal line are arranged in the same layer, and the fan-out virtual line is arranged in the glue coating area, arranged in the same layer with the other of the first layer signal line or the second layer signal line and arranged opposite to the fan-out signal line. Therefore, the sum of the thicknesses of the fan-out signal lines and the fan-out dummy lines is equal to the sum of the thicknesses of the first-layer signal lines and the second-layer signal lines. Therefore, at least part of the fan-out wires in the glue coating area have the same thickness as the substrate wires. Therefore, the thickness uniformity of the formed display panel is effectively improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a display panel in one embodiment;
FIG. 2 is a schematic plan view of an embodiment of an array substrate;
FIG. 3 is a cross-sectional view of a substrate trace and a fan-out trace in a glue area in an embodiment;
FIG. 4 is a schematic plan view of a fan-out trace in one embodiment;
FIG. 5 is an enlarged plan view of three fan-out traces in one embodiment;
FIG. 6 is a cross-sectional view of a substrate trace and a fan-out trace in a glue area in another embodiment;
FIG. 7 is an enlarged plan view of three fan-out traces in another embodiment;
fig. 8 is an enlarged plan view of three fan-out traces and sealant in an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The array substrate provided by the application can be applied to a liquid crystal display panel but is not limited to the liquid crystal display panel.
In one embodiment, as shown in fig. 1, a display panel is provided, which includes a color film substrate 100, a sealant 200, and an array substrate 300. The color film substrate 100 and the array substrate 300 are assembled by bonding with the sealant 200.
The display panel of the present embodiment may be a liquid crystal display panel. At this time, the liquid crystal display panel may further include a liquid crystal layer 400 formed by liquid crystal molecules 410 between the color film substrate 100 and the array substrate 300. The display panel may be manufactured by first forming the color filter substrate 100 and the array substrate 300. And then the color film substrate 100 is bonded with the array substrate 300 through the frame adhesive 200.
Color resists of various colors (e.g., red, green, and blue) may be formed on the color film substrate 100, so that the display panel can perform color display.
The sealant 200 bonds the color film substrate 100 and the array substrate 300 together, and serves to seal the display panel and prevent the liquid crystal molecules 410 from overflowing and water vapor from entering. In order to maintain the thickness of the peripheral box of the display panel, a certain proportion of spacers are added in the sealant 200. These spacers may be glass fibers, silicon spheres, plastic spheres, and the like.
Referring to fig. 2, the array substrate 300 has a display area 300a and a non-display area 300b surrounding the display area 300 a. The non-display area 300b includes a glue-coated area 300 c. The glue coating area 300c is used for coating the frame glue 200. The display area 300a may include a plurality of scan lines 310 parallel to each other and a plurality of data lines 320 parallel to each other. The plurality of scan lines 310 and the plurality of data lines 320 are arranged in a crossing manner to define a plurality of sub-pixel regions.
Meanwhile, the array substrate 300 includes at least two driving units 330, a plurality of substrate traces 340 and a plurality of fan-out traces 350.
Each driving unit 330 is bound to the non-display area 300b to provide a driving signal for the display area 300 a. Specifically, the driving unit 330 may be a Chip On Film (COF) provided with a driving chip, which may include at least one source driver 331 and at least one gate driver 332. The source driver 331 is used for providing data signals to the data lines 320, and the gate driver 332 is used for providing scan signals to the scan lines 310.
Each substrate trace 340 and each fan-out trace 350 are located in the non-display area 300b (for clarity, the substrate trace 340 and the fan-out trace 350 are not shown in fig. 2). Referring to fig. 3, the same substrate trace 340 includes a first layer of trace 341 and a second layer of trace 342 disposed oppositely. The first layer of traces 341 and the second layer of traces 342 are located between the driving units 330, and are used for implementing signal transmission between the driving units 330. For example, referring to fig. 2, when the first gate driver 332 on the left side of the display panel operates, the first source driver 331 on the left side of the display panel transmits signals to the first gate driver through the substrate traces 340, and then the chips on the gate driver 332 start to operate. Or, the two gate drivers 332 on the same side of the display panel are also connected by the substrate trace 340, so as to implement signal transmission.
Meanwhile, referring to fig. 3 to 5, the same fan-out trace 350 is disposed in the embodiment to include a fan-out signal line 351 and a fan-out dummy line 352. The fan-out signal line 351 is connected to the display area 300a and is used for transmitting the signal of the driving unit 330 to the display area 300a, specifically to the scan line 310 and the data line 320 of the display area 300 a. The fan-out dummy line 352 is disposed at the glue area 300c, and is disposed opposite to the fan-out signal line 351.
Here, the fan-out dummy line 352 is disposed in the glue area 300c, and may penetrate through the glue area 300c as shown in fig. 5, or may be disposed inside the glue area 300c without penetrating through the glue area 300c, which is not limited in the present application. Moreover, the fan-out virtual line 352 of the same fan-out trace 350 may be a continuous trace or a discontinuous trace, that is, it may be divided into a plurality of segments. Nor is the application limited thereto.
The fan-out signal line 351 is provided at the same level as the first-layer signal line 341, and the fan-out dummy line 352 is provided at the same level as the second-layer signal line 342 (see fig. 3). Alternatively, the fan-out signal line 351 is provided in the same layer as the second layer signal line 342, and the fan-out dummy line 352 is provided in the same layer as the first layer signal line 341 (see fig. 6). Therefore, the sum of the thicknesses of the fan-out signal line 351 and the fan-out dummy line 352 is equal to the sum of the thicknesses of the first layer signal line 341 and the second layer signal line 342.
In this embodiment, fan-out dummy lines 352 are provided within the glue area 300 c. Therefore, the fan-out trace 350 in the glue area 300c includes not only the fan-out signal line 351 but also a fan-out dummy line 352 disposed opposite to the fan-out signal line 351. Also, the sum of the thicknesses of the fan-out signal line 351 and the fan-out dummy line 352 is equal to the sum of the thicknesses of the first layer signal line 341 and the second layer signal line 342. Therefore, at least a portion of the fan-out traces 350 in the glue area 300c have the same thickness as the substrate traces 340.
Therefore, when the color film substrate 100 and the array substrate 300 of the display panel of the embodiment are bonded and assembled by the sealant 200, the sealant 200 can be coated on the substrate trace 340 and the fan-out trace 350 with the same thickness, so as to improve the thickness uniformity of the formed display panel.
In one embodiment, referring to fig. 2, the non-display area 300b further includes a balance area 300d surrounding the display area 300 a. The balancing section 300d includes a glue application section 300 c. Referring to fig. 5, the fan-out dummy line 352 extends from one side of the balance area 300d to the other side of the balance area 300 d. At this time, the fan-out dummy lines 352 are routed continuously and penetrate the glue coated area 300 c. Therefore, the thickness uniformity of the formed display panel can be improved.
In one embodiment, with continued reference to fig. 5, the balance area 300d also includes a glue error area 300 e. The glue application error area 300e is connected to the glue application area 300c and located on both sides of the glue application area 300 c. In the actual coating process of the frame adhesive 200, due to various reasons (e.g., the operational capability of the operator, the coating precision difference of the coating machine itself, or the pressing process influence after the coating), the frame adhesive 200 may finally fall into the coating error area 300e on one side or both sides of the coating area 300 c.
The balance setting area 300d of the present embodiment further includes glue application error areas 300e located on both sides of the glue application area 300 c. At this time, since the fan-out dummy line 352 extends from one side of the balance area 300d to the other side of the balance area 300d, even if the sealant 200 finally falls into the sealant error area 300e on one side or both sides of the sealant area 300c, the sealant can stand on the substrate trace 340 and the fan-out trace 350 with the same thickness, thereby further ensuring the thickness uniformity of the formed display panel. Of course, in other embodiments, the balancing section 300d may comprise only the glue-coated section 300 c. The application is not limited thereto.
Specifically, the distance d1 from the side of the glue application error region 300e away from the balance region 300d to the side of the glue application error region 300e close to the balance region 300d may be set to 100um to 600 um. Of course, the application is not limited thereto, and the length of the glue error area 300e can be determined according to the process capability, machine capability, etc. of each factory.
In one embodiment, referring to FIG. 7, the balancing area 300d also includes an expansion area 300f, with the fanout virtual line 352 extending from one side of the balancing area 300d to the other side of the balancing area 300 d. The expansion zone 300f connects the glue application error zone 300 e. The expansion region 300f is disposed such that the relationship between the actual region of the sealant 200 and the balance region 300d in the finally formed display panel is closer to that shown in fig. 8. At this time, the sealant 200 is located inside the balance area 300d, and the distances d2 and d3 from the two side boundaries of the balance area 300d are both greater than 0, so as to further ensure that the thickness of the substrate trace 340 under the sealant 200 is the same as that of the fan-out trace 350, i.e., further ensure the uniformity of the thickness of the formed display panel.
In one embodiment, in the balance area 300d, the line width of the fan-out dummy line 352 is greater than or equal to the line width of its opposing fan-out signal line 351. At this time, the fan-out signal line 351 in the balanced area 300d is completely covered by the fan-out dummy line 352, so that the thickness of the substrate trace 340 in the balanced area 300d is preferably the same as that of the fan-out trace 350.
Of course, the embodiment of the present application is not limited thereto, and the line width of the fan-out dummy line 352 may also be smaller than the line width of the opposite fan-out signal line 351. At this time, the substrate trace 340 and the fan-out trace 350 in the balancing area 300d still have the same thickness, so that the uniformity of the thickness of the display panel can be improved to a certain extent.
In the embodiment of the present application, referring to fig. 2, the non-display area 300b may include a routing area 300g and a binding area 300h surrounding the display area 300 a. The drive unit 330 is bound to the binding region 300 h. The routing area 300g is located between the display area 300a and the binding area 300 h.
Specifically, in the display panel, the outer boundary of the routing area 300g of the array substrate 300 coincides with the boundary of the color filter substrate 100. The sealant 200 is used for bonding the array substrate 300 and the color film substrate 100. Therefore, the balance area 300d is disposed in the routing area 300g to satisfy the purpose of making the thickness of the display panel uniform, and the structure of the bonding area 300h is not changed at this time, thereby increasing the compatibility with the existing bonding process.
In addition, in the embodiment of the present application, referring to fig. 3 and fig. 6, the array substrate 300 may further include a substrate 360 and an insulating layer 370. When the fan-out signal line 351 and the first layer signal line 341 are disposed on the same layer, and the fan-out dummy line 352 and the second layer signal line 342 are disposed on the same layer, the first layer routing line 341 and the fan-out signal line 351 are disposed on the substrate 360 and formed on the same layer as the scan line 310. The insulating layer 370 covers the first layer of traces 341, the fan-out signal lines 351, and the scan lines 310. The second layer routing 342 and the fan-out dummy line 352 are disposed on the insulating layer 370 and formed on the same layer as the data line 320.
When the fan-out signal line 351 and the second layer signal line 342 are disposed at the same layer and the fan-out dummy line 352 and the first layer signal line 341 are disposed at the same layer, the first layer routing line 341 and the fan-out dummy line 352 are disposed on the substrate 360 and formed at the same layer as the scan line 310. The insulating layer 370 covers the first layer of traces 341, the fan-out dummy lines 352, and the scan lines 310. The second layer routing 342 and the fan-out signal line 351 are disposed on the insulating layer 370 and formed at the same layer as the data line 320.
In one embodiment, referring to fig. 2 and 5 (or fig. 2 and 7), the array substrate 300 has a display area 300a and a non-display area 300b surrounding the display area 300 a. The non-display area 300b further includes a routing area 300g and a binding area 300h surrounding the display area 300 a. The routing area 300g is located between the display area 300a and the binding area 300h and includes a balance area 300 d. The balance area 300d includes a glue coating area 300c for coating the sealant 200.
The array substrate 300 includes at least two driving units 330, a plurality of substrate traces 340, and a plurality of fan-out traces 350. Each of the driving units 330 is bound to the binding region 300h for providing a driving signal to the display region 300 a.
Each substrate trace 340 and each fan-out trace 350 are located in the non-display area 300 b. The same substrate trace 340 includes a first layer trace 341 and a second layer trace 342 disposed opposite to each other. The first layer of traces 341 and the second layer of traces 342 are located between the driving units 330, and are used for implementing signal transmission between the driving units 330.
Meanwhile, the same fan-out trace 350 is provided in the present embodiment to include a fan-out signal line 351 and a fan-out dummy line 352. The fan-out signal line 351 is connected to the display area 300a for transmitting a signal of the driving unit 330 to the display area 300 a. The fan-out dummy line 352 extends from one side of the balance area 300d to the other side of the balance area 300d, and is disposed opposite to the fan-out signal line 351.
The fan-out signal line 351 is provided at the same level as the first-layer signal line 341, and the fan-out dummy line 352 is provided at the same level as the second-layer signal line 342. Alternatively, the fan-out signal line 351 is disposed on the same level as the second-layer signal line 342, and the fan-out dummy line 352 is disposed on the same level as the first-layer signal line 341.
The fan-out dummy line 352 of the present embodiment extends from one side to the other side of the balance area 300d including the glue area 300c, and is disposed opposite to the fan-out signal line 351. Therefore, the sealant 200 is coated on the substrate trace 340 and the fan-out trace 350 having the same thickness, thereby effectively improving the thickness uniformity of the display panel.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. An array substrate, has a display area and surrounds the non-display area of display area, the non-display area is including the rubber coating area that is used for coating frame gum, its characterized in that, array substrate includes:
at least two driving units bound to the non-display area and used for providing driving signals for the display area;
the plurality of substrate wires are positioned in the non-display area, and the same substrate wire comprises a first layer of wire and a second layer of wire which are arranged oppositely; the first layer of wiring and the second layer of wiring are both positioned between the driving units and are used for realizing signal transmission between the driving units;
the fan-out wires are positioned in the non-display area, and the same fan-out wire comprises a fan-out signal wire and a fan-out virtual wire; the fan-out signal line is arranged on the same layer as one of the first layer signal line or the second layer signal line and connected with the display area, and is used for transmitting the signal of the driving unit to the display area; the fan-out virtual line is arranged in the glue coating area, arranged at the same layer with the other one of the first layer signal line or the second layer signal line and arranged opposite to the fan-out signal line;
the non-display area still includes to encircle the balanced district of display area, balanced district includes the rubber coating district, balanced position in the drive unit with between the display area, and with the drive unit with the equal interval in display area sets up, the fan-out virtual line only set up in the balanced district.
2. The array substrate of claim 1, wherein the fan-out dummy line extends from one side of the balancing area to another side of the balancing area.
3. The array substrate of claim 2, wherein the balancing area further comprises a glue spreading error area, and the glue spreading error area is connected with the glue spreading area and located on two sides of the glue spreading area.
4. The array substrate of claim 3, wherein a distance from a side of the glue error area away from the balance area to a side of the glue error area close to the balance area is 100um to 600 um.
5. The array substrate of claim 3, wherein the balancing area further comprises an expansion area, and the expansion area is connected with the glue error area.
6. The array substrate of claim 2, wherein in the balancing area, the line width of the fan-out dummy line is greater than or equal to the line width of the fan-out signal line opposite to the fan-out dummy line.
7. The array substrate of claim 2, wherein the non-display area comprises a routing area and a bonding area surrounding the display area, the routing area is located between the display area and the bonding area, the driving unit is bonded to the bonding area, and the balance area is located in the routing area.
8. The array substrate of claim 1, wherein the array substrate further comprises a substrate base plate and an insulating layer, the first layer of traces is located on the substrate base plate, the insulating layer covers the first layer of traces, and the second layer of traces is located on the insulating layer.
9. An array substrate, having a display area and a non-display area surrounding the display area, wherein the non-display area further comprises a wiring area and a binding area surrounding the display area, the wiring area is located between the display area and the binding area and comprises a balance area, the balance area comprises a glue coating area for coating frame glue, the array substrate comprises:
at least two driving units bound to the binding region and used for providing driving signals for the display region;
the plurality of substrate wires are positioned in the non-display area, and the same substrate wire comprises a first layer of wire and a second layer of wire which are arranged oppositely; the first layer of wiring and the second layer of wiring are both positioned between the driving units and are used for realizing signal transmission between the driving units;
the fan-out wires are positioned in the non-display area, and the same fan-out wire comprises a fan-out signal wire and a fan-out virtual wire; the fan-out signal line is arranged on the same layer as one of the first layer signal line or the second layer signal line and connected with the display area, and is used for transmitting the signal of the driving unit to the display area; the fan-out virtual line extends from one side of the balance area to the other side of the balance area, is arranged at the same layer with the other one of the first layer signal line or the second layer signal line and is opposite to the fan-out signal line;
the fan-out virtual line is only arranged in the balance area.
10. A display panel, comprising a color film substrate, a sealant and the array substrate of any one of claims 1 to 9, wherein the color film substrate and the array substrate are assembled by bonding the sealant.
CN201910497006.7A 2019-06-10 2019-06-10 Array substrate and display panel Active CN110187574B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910497006.7A CN110187574B (en) 2019-06-10 2019-06-10 Array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910497006.7A CN110187574B (en) 2019-06-10 2019-06-10 Array substrate and display panel

Publications (2)

Publication Number Publication Date
CN110187574A CN110187574A (en) 2019-08-30
CN110187574B true CN110187574B (en) 2022-04-15

Family

ID=67721117

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910497006.7A Active CN110187574B (en) 2019-06-10 2019-06-10 Array substrate and display panel

Country Status (1)

Country Link
CN (1) CN110187574B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112596295A (en) * 2020-12-29 2021-04-02 惠科股份有限公司 Color film substrate, manufacturing method of color film substrate and display panel
CN113870713B (en) * 2021-09-29 2023-11-07 成都京东方光电科技有限公司 Display panel and display device

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101424828A (en) * 2007-11-02 2009-05-06 上海广电Nec液晶显示器有限公司 LCD panel
CN102902084A (en) * 2011-07-28 2013-01-30 瀚宇彩晶股份有限公司 Structure of fan-out signal wire area and display panel
CN103293808A (en) * 2013-05-28 2013-09-11 深圳市华星光电技术有限公司 Display device and manufacturing method thereof
CN103383512A (en) * 2012-05-01 2013-11-06 乐金显示有限公司 Liquid crystal display device and method of fabricating the same
CN203365869U (en) * 2013-08-12 2013-12-25 京东方科技集团股份有限公司 Array substrate and display device
CN103472641A (en) * 2013-08-30 2013-12-25 京东方科技集团股份有限公司 Array substrate and production method thereof, liquid crystal display panel and display device
CN104699349A (en) * 2015-04-01 2015-06-10 上海天马微电子有限公司 Array substrate, array substrate manufacturing method and display panel
CN207924331U (en) * 2018-02-26 2018-09-28 惠科股份有限公司 A kind of display device
CN109240000A (en) * 2018-11-14 2019-01-18 惠科股份有限公司 A kind of Fanout line structure and display device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101424828A (en) * 2007-11-02 2009-05-06 上海广电Nec液晶显示器有限公司 LCD panel
CN102902084A (en) * 2011-07-28 2013-01-30 瀚宇彩晶股份有限公司 Structure of fan-out signal wire area and display panel
CN103383512A (en) * 2012-05-01 2013-11-06 乐金显示有限公司 Liquid crystal display device and method of fabricating the same
CN103293808A (en) * 2013-05-28 2013-09-11 深圳市华星光电技术有限公司 Display device and manufacturing method thereof
CN203365869U (en) * 2013-08-12 2013-12-25 京东方科技集团股份有限公司 Array substrate and display device
CN103472641A (en) * 2013-08-30 2013-12-25 京东方科技集团股份有限公司 Array substrate and production method thereof, liquid crystal display panel and display device
CN104699349A (en) * 2015-04-01 2015-06-10 上海天马微电子有限公司 Array substrate, array substrate manufacturing method and display panel
CN207924331U (en) * 2018-02-26 2018-09-28 惠科股份有限公司 A kind of display device
CN109240000A (en) * 2018-11-14 2019-01-18 惠科股份有限公司 A kind of Fanout line structure and display device

Also Published As

Publication number Publication date
CN110187574A (en) 2019-08-30

Similar Documents

Publication Publication Date Title
CN110109275B (en) Array substrate and display panel
CN108762562B (en) Display substrate, display panel, touch display device and manufacturing method thereof
JP6312072B2 (en) Liquid crystal display
CN110187574B (en) Array substrate and display panel
JP5507812B2 (en) Display panel and display substrate manufacturing method
WO2012017617A1 (en) Liquid crystal display device and manufacturing method for same
KR20050033293A (en) The liquid crystal display device and the method for fabricating the same
JP2016071083A (en) Display device and drive circuit
CN102879941B (en) Liquid crystal disply device and its preparation method
CN110488526A (en) Display module and assemble method
WO2021164059A1 (en) Liquid crystal display panel and preparation method therefor
CN112150914A (en) Display module and display device
CN109307961A (en) Display panel circuit structure
CN106292111A (en) A kind of array base palte and display panels
KR20170028473A (en) Composition for alignment layer, array substrate for display device comprising the same
CN109633989A (en) Display panel
CN208689324U (en) Liquid crystal display panel and liquid crystal display device
CN104297979B (en) Display panel mother board, display panel, manufacturing method of display panel and display device
CN105892129A (en) Liquid crystal display substrate and cutting method thereof
KR102474318B1 (en) Display apparatus and method of manufacturing the same
KR20130027189A (en) Liquid crystal display and method for manufacturing the same
WO2023206627A1 (en) Display panel and electronic equipment
JP2016184148A (en) Liquid crystal display panel, manufacturing method for the same, and display device
CN209149276U (en) Touching display screen
KR20180047556A (en) Display Device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant