CN102708771A - Array substrate, manufacturing method and display unit thereof - Google Patents
Array substrate, manufacturing method and display unit thereof Download PDFInfo
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- CN102708771A CN102708771A CN2012101495125A CN201210149512A CN102708771A CN 102708771 A CN102708771 A CN 102708771A CN 2012101495125 A CN2012101495125 A CN 2012101495125A CN 201210149512 A CN201210149512 A CN 201210149512A CN 102708771 A CN102708771 A CN 102708771A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The invention discloses an array substrate, a manufacturing method and a display unit thereof, relates to the design field of display units, and is used for achieving testing of signals of any data line in the display unit. The array substrate comprises a display area and a non-display area, and the non-display area comprises at least one data line lead pattern unit; a plurality of data line leads are arranged in each of the at least one data line lead pattern unit, the data line lead comprises a first connecting portion which is used for being electrically connected with a chip, at least one test line is further arranged in each of the at least one data line lead pattern unit, each of the at least one test line is crosswise arranged with all data line leads in a same one data line lead pattern unit, and insulation layers are arranged among the test lines and the data line leads; wherein the test line comprises a second connecting portion which is used for being electrically connected with the chip, and is connected with test points of a printed circuit board through the chip. The array substrate, the manufacturing method and the display unit thereof are used for designing and manufacturing array substrates.
Description
Technical field
The present invention relates to the design field of display device, relate in particular to a kind of array base palte and manufacturing approach thereof, display device.
Background technology
As shown in Figure 1, the display panel structure of TFT-LCD (TFT-LCD) comprises at present: to the array base palte 11 and color membrane substrates 12 of box shaping, and the liquid crystal between two substrates.Because the data line on the array base palte all need be connected driving circuit with grid line,, connect the required space of driving circuit so that stay so array base palte 11 is more bigger than color membrane substrates 12.Above-mentioned two substrates is through the fluid sealant adhesion, and liquid crystal is filled in the inboard of fluid sealant, is used for display image, so can fluid sealant area inside on the array base palte be called the viewing area, other zones are called non-display area.Describe for clear, the data line that will be positioned at non-display area is called data cable lead wire, and the grid line that will be positioned at non-display area is called the grid line lead-in wire.Further describe to data cable lead wire below.
With reference to enlarged drawing shown in Figure 2; At non-display area; One group of compact arranged data cable lead wire region is called a data line lead pattern unit; And the data cable lead wire 31 in each data cable lead wire pattern unit all needs a chip 13 and PCB (Printed Circuit Board, printed circuit board (PCB)) 14 to be electrically connected; Wherein, this chip bearing has IC (integrated circuit, integrated circuit), and the normal chip that uses is COF (Chip On Film, a thin film chip).
Be to realize the test to data line signal, method in common is to utilize the design of the cabling on the chip at present, each chip both sides of the edge corresponding data lines is electrically connected with test point on the pcb board 14, with the test of realization to data line signal.Obviously, said method only is that individual other data line has been realized test function, and so just the performance test to later stage failure analysis and panel brings inconvenience.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacturing approach thereof, display device, in order to realizing the test to arbitrary data line signal in the display device, thereby improve the work efficiency of later stage failure analysis and panel performance test.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, the invention provides a kind of array base palte, comprising: viewing area and non-display area, said non-display area comprise at least one data cable lead wire pattern unit; Be provided with many data cable lead wires in each said data cable lead wire pattern unit; Said data cable lead wire comprises first connecting portion; This first connecting portion is used for being electrically connected with chip; Also be provided with at least one p-wire in each said data cable lead wire pattern unit, every p-wire is positioned at same data cable lead wire pattern unit with it all data cable lead wires are arranged in a crossed manner, and are provided with insulation course between said p-wire and the said data cable lead wire; Wherein, said p-wire comprises second connecting portion, and this second connecting portion is used for being electrically connected with said chip, and connects the test point of printed circuit board (PCB) through said chip.
On the other hand, the present invention also provides a kind of manufacturing approach of array base palte, comprising:
On underlay substrate, make the grid line metallic film, and form the grid line metal layer pattern through composition technology, said grid line metal layer pattern comprises: grid line, grid line lead-in wire and at least one p-wire that is positioned at each data cable lead wire pattern unit; Said p-wire comprises second connecting portion, and this second connecting portion is used for being electrically connected with chip, and connects the test point of printed circuit board (PCB) through said chip;
Continue to form gate insulation layer, active layer, data line metal layer pattern; Said data line metal layer pattern comprises: data line, data cable lead wire, and wherein, said data cable lead wire comprises first connecting portion, this first connecting portion is used for being electrically connected with chip;
Make passivation layer, and form via hole in the position of said first connecting portion and said second connecting portion at least through composition technology;
Make first transparent conductive film, and second contact site that forms first transparency electrode, first contact site that links to each other with said first connecting portion, links to each other with said second connecting portion through composition technology.
On the one hand, the present invention also provides a kind of display device, comprising: color membrane substrates and above-mentioned array base palte, chip, printed circuit board (PCB) again;
Said chip is electrically connected with first connecting portion and second connecting portion of said array base palte, and second connecting portion of said chip is electrically connected with the test point of said printed circuit board (PCB).
A kind of array base palte that the embodiment of the invention provides and manufacturing approach thereof, display device; In each said data cable lead wire pattern unit, be provided with at least one p-wire; And every p-wire is positioned at same data cable lead wire pattern unit with it all data cable lead wires are arranged in a crossed manner; Like this when need be when wherein the signal of a data line be tested, the data cable lead wire and the p-wire of this data line coupled together, accomplish the test back and break off and getting final product; Thereby can realize test, and then improve the work efficiency of later stage failure analysis and panel performance test arbitrary data line signal in the display device.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of display panel in the prior art;
Fig. 2 is the local enlarged diagram of Fig. 1;
Fig. 3 is the structural representation of a kind of array base palte provided by the invention;
Fig. 4 is a kind of local enlarged diagram of Fig. 3;
Fig. 5 is the another kind of local enlarged diagram of Fig. 3;
Fig. 6 is another local enlarged diagram of Fig. 3;
Fig. 7 is the local enlarged diagram of another kind of array base palte provided by the invention;
Fig. 8-Figure 12 is the sectional view in the manufacturing approach process of array base palte shown in Figure 4.
Reference numeral:
The 11-array base palte, 12-color membrane substrates, 13-chip, 14-PCB plate;
The 21-viewing area, 22-non-display area, 221-data cable lead wire pattern unit, 222-grid line lead pattern unit;
31-data cable lead wire, 311-first connecting portion, 32-grid line lead-in wire, 33-p-wire, 331-second connecting portion;
41-first contact site, 43-second contact site;
The 51-gate insulation layer, the 52-passivation layer.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Like Fig. 3-shown in Figure 7, the embodiment of the invention provides a kind of array base palte, comprising: viewing area 21 and non-display area 22, and said non-display area 22 comprises at least one data cable lead wire pattern unit 221; Be provided with many data cable lead wires 31 in each said data cable lead wire pattern unit 221, said data cable lead wire 31 comprises first connecting portion 311, and this first connecting portion 311 is used for being electrically connected with chip.Certainly, non-display area also comprises at least one grid line lead pattern unit 222, is provided with many grid line lead-in wires 32 in each grid line lead pattern unit 222.
In all embodiment of the present invention, the viewing area is meant that array base palte is in the fluid sealant area inside to box the time, and this zone is used for filling liquid crystal with display image, and other zones are called non-display area.Describe for convenient; Data line still is called data line viewing area that part of, at that part of data cable lead wire that then is called of non-display area; Equally, grid line still be called grid line viewing area that part of, at that part of grid line lead-in wire that then is called of non-display area.In non-display area, one group of compact arranged data cable lead wire region is called a data line lead pattern unit, and one group of compact arranged grid line lead-in wire region is called a grid line lead pattern unit.
In embodiments of the present invention, mainly in data cable lead wire pattern unit 221, improve.Also be provided with at least one p-wire 33 in each said data cable lead wire pattern unit 221; Every p-wire 33 is positioned at all data cable lead wires 31 of same data cable lead wire pattern unit with it arranged in a crossed manner, and be provided with insulation course between said p-wire 33 and the said data cable lead wire 31; Wherein, said p-wire 33 comprises second connecting portion 331, and this second connecting portion 331 is used for being electrically connected with said chip, and connects the test point of printed circuit board (PCB) through said chip.
Need to prove that insulation course is meant the layer structure with insulating effect.
Fig. 3-Fig. 6 is an example to be provided with a p-wire, and Fig. 7 is an example so that two p-wires to be set.Because n (n >=1) bar p-wire 33 is set, just can test the signal of n bar data line simultaneously, that is to say that the p-wire of setting is many more, the data line signal that can test simultaneously just can be many more.But, consider the restriction in data cable lead wire pattern unit space, one or two p-wires preferably are set.
The array base palte that the embodiment of the invention provides; In each said data cable lead wire pattern unit, be provided with at least one p-wire; And every p-wire is positioned at same data cable lead wire pattern unit with it all data cable lead wires are arranged in a crossed manner; Like this when need be when wherein the signal of a data line be tested, the data cable lead wire and the p-wire of this data line coupled together, accomplish the test back and break off and getting final product; Thereby can realize test, and then improve the work efficiency of later stage failure analysis and panel performance test arbitrary data line signal in the display device.
Further, second connecting portion 331 of said p-wire 33 is positioned at an end of this p-wire 33.Can under the situation that does not change the data cable lead wire distribution, set up p-wire like this.
Further; In same data cable lead wire pattern unit; The crossover location of p-wire 33 and data cable lead wire 31 can be with reference to figure 4, Fig. 7 outside at first connecting portion 311 of this data cable lead wire 31; Also can overlap with first connecting portion 311 of data cable lead wire 31 with reference to figure 5, also can be with reference to the inboard of figure 6 at first connecting portion 311 of data cable lead wire 31.In embodiments of the present invention, to a data cable lead wire 31, be that the boundary is divided into both sides with first connecting portion 311, wherein will be called the outside of first connecting portion 311 near a side at array base palte edge, opposite side is called the inboard of first connecting portion 311.
With reference to figure 5, in same data cable lead wire pattern unit, the crossover location of p-wire 33 and data cable lead wire 31 overlaps with first connecting portion 311 of data cable lead wire.When needs are tested data line signal, from as far as near order (i.e. from left to right order the diagram), successively the signal of each data cable lead wire 31 is tested according to distance second connecting portion 331.For the signal testing of a data cable lead wire 31 wherein; Be specially; At first adopt laser technology that p-wire 33 is connected with the crossover location (being posetionof weld) of data cable lead wire 31 to be tested at both, so that can the signal of data cable lead wire 31 to be tested be incorporated into the test point of pcb board; After accomplishing test, the data cable lead wire 31 and the p-wire between next bar data cable lead wire 31 to be tested 33 that need utilize laser technology will accomplish test cut off.
With reference to figure 6, in the same data cable lead wire pattern unit, the crossover location of p-wire 33 and data cable lead wire 31 is in the inboard of first connecting portion 311 of data cable lead wire.When needs are tested data line signal,, repeat no more with reference to above-mentioned method of testing.
Preferably, in same data cable lead wire pattern unit, the crossover location of p-wire 33 and data cable lead wire 31 is positioned at the outside of first connecting portion 311 of this data cable lead wire with reference to figure 4, Fig. 7.In the time need testing to the arbitrary data line signal in this data cable lead wire pattern unit; Then adopt laser technology that p-wire 33 is connected with the crossover location (being posetionof weld) of data cable lead wire 31 to be tested at both; After accomplishing test, need utilize laser technology that the data cable lead wire between this crossover location and first connecting portion 311 31 is switched and get final product.This scheme need not to carry out according to permanent order the test of data line signal, and is more flexible.
Further, the grid line in said p-wire and the said viewing area is provided with layer.So-called layer together is provided with at least two kinds of patterns, is meant at least two kinds of pattern setting with the structure on the thin film, and is concrete, is on the thin film that same material is processed, to form said at least two kinds of patterns through composition technology.So just change the formed pattern of composition technology, and need not to increase making step.
Preferably, said p-wire is parallel with the grid line in the viewing area.
Because general grid line, data cable lead wire are all covered by at least one layer insulating, so data cable lead wire, all need pass insulation course with grid line with the p-wire of layer setting, so that can connect chip; So in embodiments of the present invention; Preferably; Said first connecting portion 311 connects first contact site 41 through via hole, and said first connecting portion 311 is used for being electrically connected with chip and comprises: said first connecting portion 311 is used for being electrically connected with chip through said first contact site 41; Said second connecting portion 331 connects second contact site 43 through via hole, and said second connecting portion 331 is used for being electrically connected with said chip and comprises: said second connecting portion 331 is used for being electrically connected with said chip through said second contact site 43.
Wherein, the material of first contact site 41 and second contact site 43 is conductive material.
Further preferred, said first contact site 41, said second contact site 43 are provided with layer with top transparent electrode in the said viewing area.Need to prove that top transparent electrode is meant that array base palte is away from the transparency electrode of underlay substrate, promptly according to making the transparency electrode that order completes at last.Concrete, for the array base palte that only is provided with a kind of transparency electrode, the array base palte of TN (Twist Nematic, twisted-nematic) type LCD for example, it comprises pixel electrode, and at this moment, this transparency electrode is top transparent electrode.For the array base palte that is provided with two kinds of transparency electrodes (pixel electrode and public electrode), the array base palte of FFS (Fringe Field Switching, fringe field switching) type LCD for example, at this moment, top transparent electrode then is the transparency electrode away from underlay substrate.
The embodiment of the invention also provides a kind of manufacturing approach of array base palte, and needing explanation is that the accompanying drawing of this manufacturing approach is an example with the cut-open view at the C-C tangent plane place of Fig. 4.Said manufacturing approach comprises:
S101, as shown in Figure 8; On underlay substrate, make the grid line metallic film; And through composition technology formation grid line metal layer pattern, said grid line metal layer pattern comprises: grid line, grid line lead-in wire and at least one p-wire that is positioned at each data cable lead wire pattern unit; Said p-wire comprises second connecting portion 331, and this second connecting portion 331 is used for being electrically connected with chip, and connects the test point of printed circuit board (PCB) through said chip;
S102, as shown in Figure 9 continues to form gate insulation layer 51, active layer;
S103, shown in figure 10 forms the data line metal layer pattern; Said data line metal layer pattern comprises: data line, data cable lead wire, and wherein, said data cable lead wire comprises first connecting portion 311, this first connecting portion 311 is used for being electrically connected with chip;
S104, shown in figure 11 makes passivation layer 52, and forms via hole in the position of said first connecting portion 311 and said second connecting portion 331 at least through composition technology;
S104, shown in figure 12 makes first transparent conductive film, and forms first transparency electrode, first contact site 41 that links to each other with said first connecting portion 311, second contact site 43 that links to each other with said second connecting portion 331 through composition technology.
Need to prove, only embodied the structure at each A-A tangent plane place in each accompanying drawing, although other parts fail in diagram, to embody, those skilled in the art can know the structure of confirming whole array base palte according to foregoing description.
Above-mentioned is the manufacturing approach of the array base palte of TN type LCD; And comprise the array base palte of two kinds of transparency electrodes; The array base palte of FFS type LCD for example, its manufacturing approach promptly at least also comprises between step S102 and S103 between said active layer of above-mentioned formation and said data line metal layer pattern:
S105, form second transparent conductive film, and form second transparency electrode through composition technology.
The embodiment of the invention also provides a kind of display device, comprising: color membrane substrates and above-mentioned any array base palte chip, printed circuit board (PCB);
Said chip is electrically connected with first connecting portion and second connecting portion of said array base palte, and second connecting portion of said chip is electrically connected with the test point of said printed circuit board (PCB).
Array base palte of processing according to above-mentioned manufacturing approach and the display device that comprises this array base palte when need be when wherein the signal of a data line is tested, couple together the data cable lead wire and the p-wire of this data line, accomplish the test back and break off and getting final product; Thereby can realize test, and then improve the work efficiency of later stage failure analysis and panel performance test arbitrary data line signal in the display device.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technician who is familiar with the present technique field is in the technical scope that the present invention discloses; The variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of said claim.
Claims (10)
1. array base palte, comprising: viewing area and non-display area, said non-display area comprise at least one data cable lead wire pattern unit; Be provided with many data cable lead wires in each said data cable lead wire pattern unit, said data cable lead wire comprises first connecting portion, and this first connecting portion is used for being electrically connected with chip, it is characterized in that,
Also be provided with at least one p-wire in each said data cable lead wire pattern unit; Every p-wire is positioned at same data cable lead wire pattern unit with it all data cable lead wires are arranged in a crossed manner, and are provided with insulation course between said p-wire and the said data cable lead wire; Wherein, said p-wire comprises second connecting portion, and this second connecting portion is used for being electrically connected with said chip, and connects the test point of printed circuit board (PCB) through said chip.
2. array base palte according to claim 1 is characterized in that, in same data cable lead wire pattern unit, the crossover location of p-wire and data cable lead wire is positioned at the outside of first connecting portion of this data cable lead wire.
3. array base palte according to claim 2 is characterized in that, second connecting portion of said p-wire is in an end of this p-wire.
4. according to each described array base palte of claim 1-3, it is characterized in that the grid line in said p-wire and the said viewing area is provided with layer.
5. array base palte according to claim 4 is characterized in that said p-wire is parallel with said grid line.
6. array base palte according to claim 5; It is characterized in that; Said first connecting portion connects first contact site through via hole, and said first connecting portion is used for being electrically connected with chip and comprises: said first connecting portion is used for being electrically connected with chip through said first contact site;
Said second connecting portion connects second contact site through via hole, and said second connecting portion is used for being electrically connected with said chip and comprises: said second connecting portion is used for being electrically connected with said chip through said second contact site.
7. array base palte according to claim 6 is characterized in that, the top transparent electrode in said first contact site, said second contact site and the said viewing area is provided with layer.
8. the manufacturing approach of an array base palte is characterized in that, comprising:
On underlay substrate, make the grid line metallic film, and form the grid line metal layer pattern through composition technology, said grid line metal layer pattern comprises: grid line, grid line lead-in wire and at least one p-wire that is positioned at each data cable lead wire pattern unit; Said p-wire comprises second connecting portion, and this second connecting portion is used for being electrically connected with chip, and connects the test point of printed circuit board (PCB) through said chip;
Continue to form gate insulation layer, active layer, data line metal layer pattern; Said data line metal layer pattern comprises: data line, data cable lead wire, and wherein, said data cable lead wire comprises first connecting portion, this first connecting portion is used for being electrically connected with chip;
Make passivation layer, and form via hole in the position of said first connecting portion and said second connecting portion at least through composition technology;
Make first transparent conductive film, and second contact site that forms first transparency electrode, first contact site that links to each other with said first connecting portion, links to each other with said second connecting portion through composition technology.
9. manufacturing approach according to claim 8 is characterized in that, is forming between said active layer and the said data line metal layer pattern, at least also comprises:
Form second transparent conductive film, and form second transparency electrode through composition technology.
10. a display device is characterized in that, comprising: each described array base palte of color membrane substrates and claim 1-7, chip, printed circuit board (PCB);
Said chip is electrically connected with first connecting portion and second connecting portion of said array base palte, and second connecting portion of said chip is electrically connected with the test point of said printed circuit board (PCB).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210149512.5A CN102708771B (en) | 2012-05-14 | 2012-05-14 | Array substrate, manufacturing method and display unit thereof |
| PCT/CN2012/084396 WO2013170594A1 (en) | 2012-05-14 | 2012-11-09 | Array substrate, manufacturing method and display unit thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210149512.5A CN102708771B (en) | 2012-05-14 | 2012-05-14 | Array substrate, manufacturing method and display unit thereof |
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| CN102708771A true CN102708771A (en) | 2012-10-03 |
| CN102708771B CN102708771B (en) | 2015-04-15 |
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| CN103280177A (en) * | 2012-12-05 | 2013-09-04 | 上海中航光电子有限公司 | Grid driver and detecting method thereof |
| WO2013170594A1 (en) * | 2012-05-14 | 2013-11-21 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display unit thereof |
| CN104133333A (en) * | 2014-07-22 | 2014-11-05 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method |
| CN104777637A (en) * | 2015-05-08 | 2015-07-15 | 上海中航光电子有限公司 | Array substrate and touch-control display device and testing method thereof |
| CN106409192A (en) * | 2015-07-29 | 2017-02-15 | 南京瀚宇彩欣科技有限责任公司 | Display panel circuit module and test method thereof |
| CN109195321A (en) * | 2018-11-12 | 2019-01-11 | 惠科股份有限公司 | Flexible circuit board, display panel and display device |
| CN109239999A (en) * | 2018-11-12 | 2019-01-18 | 惠科股份有限公司 | Flexible circuit board, display panel and display device |
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| WO2022262028A1 (en) * | 2021-06-15 | 2022-12-22 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display apparatus |
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| CN106409192A (en) * | 2015-07-29 | 2017-02-15 | 南京瀚宇彩欣科技有限责任公司 | Display panel circuit module and test method thereof |
| CN109195321A (en) * | 2018-11-12 | 2019-01-11 | 惠科股份有限公司 | Flexible circuit board, display panel and display device |
| CN109239999A (en) * | 2018-11-12 | 2019-01-18 | 惠科股份有限公司 | Flexible circuit board, display panel and display device |
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| WO2022062481A1 (en) * | 2020-09-24 | 2022-03-31 | 广州国显科技有限公司 | Drive circuit carrier and display device |
| WO2022262028A1 (en) * | 2021-06-15 | 2022-12-22 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013170594A1 (en) | 2013-11-21 |
| CN102708771B (en) | 2015-04-15 |
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