CN104362153B - Array base palte and preparation method thereof, display device - Google Patents
Array base palte and preparation method thereof, display device Download PDFInfo
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- CN104362153B CN104362153B CN201410475455.9A CN201410475455A CN104362153B CN 104362153 B CN104362153 B CN 104362153B CN 201410475455 A CN201410475455 A CN 201410475455A CN 104362153 B CN104362153 B CN 104362153B
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Abstract
The present invention relates to display technology field, a kind of array base palte and preparation method thereof, display device are disclosed.The lead of array base palte includes transparency conducting layer and at least two metal levels below transparency conducting layer.Wherein, transparency conducting layer and one of metal level are electrically connected with, and are formed with insulating barrier between adjacent two metal levels, and are electrically connected with so that lead has at least two-layer conductive channel.And the end of at least one metal level of setting is coated by insulating barrier, it is avoided to be contacted with environment, effectively reduce lead to be corroded and the bad risk that electrically conducts occur, the design that the end of multilayer conductive channel and at least one metal level is coated by insulating barrier can greatly improve product yield.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display device.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, referred to as
TFT-LCD) there is small volume, the features such as low in energy consumption, radiationless, manufacturing cost is relatively low, in current flat-panel monitor city
Field occupies leading position.The agent structure of TFT-LCD is the array base palte and color membrane substrates to box, in array base palte and color film
Liquid crystal molecule is filled between substrate.The grid line and data wire of transverse and longitudinal intersection are formed with array base palte, multiple pixels are limited
Unit, each pixel cell includes thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) and pixel electrode, thin
Passivation layer is coated with film transistor.Drain electrode and the pixel electrode electric connection of TFT, source electrode and electrode data line is electrically connected with,
Gate electrode and grid line are electrically connected with.The pixel voltage transmitted on data wire is exported to pixel electrode, pixel by thin film transistor (TFT)
Electrode coordinates with public electrode, forms the driving electric field for driving liquid crystal molecule deflection, realizes the display of specific grey-scale.
The non-display area of TFT-LCD includes lead areas, and the lead areas includes a plurality of leads, and the lead is used for
Connection driving chip, the signal for needed for grid line and data wire are provided.
Follow-up test for convenience, in actual process, the end of lead is closing connection, as shown in figure 1, with to institute
Some grid lines or data wire apply identical signal, convenient electrology characteristic to thin film transistor (TFT) etc. to be tested.Testing
Cheng Hou, then along straight line L cutting substrates so that lead it is separated.
However, can cause that the end of lead is directly exposed in environment after cutting substrate.Due to manufacturing the ring of display device
Border is not strict dry environment, and steam present in environment or other materials can cause the corrosion of lead, greatly reduce
Product yield.
The content of the invention
The present invention provides a kind of array base palte and preparation method thereof, display device, and the end for being used to solve pin leads is sudden and violent
Dew in the environment, can be corroded by steam or other materials, greatly reduce the problem of product yield.
In order to solve the above technical problems, the present invention provides array base palte, including lead areas, the lead areas includes many
Bar lead, the lead includes the first transparency conducting layer, and first transparency conducting layer is used to be electrically connected with chip pin, institute
Stating lead also includes：
At least two metal levels, positioned at first transparency conducting layer lower section, first transparency conducting layer and wherein
Individual metal level is electrically connected with；
Wherein, insulating barrier is formed between two adjacent metal levels, and two adjacent metal levels are electrically connected with, at least
The end of one metal level is coated by insulating barrier.
Array base palte as described above, it is preferred that the lead includes two metal levels；
The end of one of metal level is coated by insulating barrier.
Array base palte as described above, it is preferred that the lead also includes：
Second transparency conducting layer, positioned at described two metal levels lower section；
First transparency conducting layer coats the side of described two metal levels, and electrical with second transparency conducting layer
Connection.
Array base palte as described above, it is preferred that the array base palte also includes viewing area, the viewing area bag
Include：
Thin film transistor (TFT), the gate electrode of the thin film transistor (TFT) is formed by grid metal, and source electrode and drain electrode are by source and drain gold
Category is formed；
Pixel electrode, is formed by transparent conductive material；
Two metal levels of the lead are respectively barrier metal layer and Source and drain metal level.
Array base palte as described above, it is preferred that the first transparency conducting layer of the lead is with pixel electrode by same
Transparent conductive film layer is formed；
The barrier metal layer of the lead is formed with the gate electrode of thin film transistor (TFT) by same grid metal film layer；
The Source and drain metal level of the lead is with the source electrode of thin film transistor (TFT) and drain electrode by same source and drain metallic diaphragm shape
Into.
Array base palte as described above, it is preferred that the viewing area also includes：
Public electrode, is formed by transparent conductive material；
Second transparency conducting layer of the lead is formed with the public electrode by same transparent conductive film layer, wherein, institute
Pixel electrode is stated for gap electrode, the public electrode is plate electrode.
Array base palte as described above, it is preferred that the thin film transistor (TFT) is bottom gate thin film transistor；
The Source and drain metal level of the lead is located between the first transparency conducting layer and barrier metal layer, first electrically conducting transparent
The first insulating barrier is formed between layer and Source and drain metal level, the second insulation is formed between the Source and drain metal level and barrier metal layer
Layer；
The first via is formed with first insulating barrier, exposes Source and drain metal level；It is formed with second insulating barrier
Second via, exposes barrier metal layer；
It is in electrical contact with Source and drain metal level that first transparency conducting layer fills first via；The Source and drain metal level
Fill second via in electrical contact with barrier metal layer；
Second transparency conducting layer is located at barrier metal layer lower section, and directly in electrical contact with barrier metal layer, described first is saturating
Bright conductive layer is coated on the side of Source and drain metal level and barrier metal layer, in electrical contact with the second transparency conducting layer.
The present invention also provides a kind of display device, and it includes array base palte, and the array base palte uses battle array as described above
Row substrate.
The present invention also provides a kind of preparation method of array base palte as described above, and the array base palte includes lead district
Domain, the preparation method includes：
A plurality of leads is formed on a underlay substrate, the lead is located at the lead areas；
The step of forming the lead includes：
The first transparency conducting layer is formed on the underlay substrate, first transparency conducting layer is used for and chip pin electricity
Property connection, it is characterised in that formed the lead the step of also include：
In at least two metal level formed below of first transparency conducting layer, first transparency conducting layer with wherein
One metal level is electrically connected with；
Wherein, insulating barrier is formed between two adjacent metal levels, and two adjacent metal levels are electrically connected with, at least
The end of one metal level is coated by insulating barrier.
Preparation method as described above, it is preferred that the lead includes two metal levels；
The end of one of metal level is coated by insulating barrier.
Array base palte as described above, it is preferred that the step of forming the lead also includes：
In second transparency conducting layer formed below of described two metal levels；
First transparency conducting layer coats the side of described two metal levels, electrically connects with second transparency conducting layer
Connect.
Array base palte as described above, it is preferred that the array base palte also includes viewing area, and the preparation method is also
Including：
Thin film transistor (TFT) is formed on the underlay substrate, the gate electrode of the thin film transistor (TFT) is formed by grid metal, source
Electrode and drain electrode are formed by source and drain metal；
Pixel electrode is formed on the underlay substrate, the pixel electrode is formed by transparent conductive material；
The thin film transistor (TFT) and pixel electrode are located at the viewing area, and two metal levels of the lead are respectively grid
Metal level and Source and drain metal level.
Array base palte as described above, it is preferred that the step of forming the lead includes：
The first transparent conductive film layer is formed on the underlay substrate, work is patterned to first transparent conductive film layer
Skill forms first transparency conducting layer and pixel electrode of the lead simultaneously；
Grid metal film layer is formed on the underlay substrate, technique is patterned to the grid metal film layer while forming institute
State the barrier metal layer of lead and the gate electrode of thin film transistor (TFT)；
Source and drain metallic diaphragm is formed on the underlay substrate, the source and drain metallic diaphragm is patterned described in technique and is drawn
The Source and drain metal level of line and the source electrode of thin film transistor (TFT), drain electrode.
Array base palte as described above, it is preferred that the step of forming the lead also includes：
The second transparent conductive film layer is formed on the underlay substrate, work is patterned to second transparent conductive film layer
Skill forms second transparency conducting layer and public electrode of the lead simultaneously, wherein, the pixel electrode is gap electrode, described
Public electrode is plate electrode.
Array base palte as described above, it is preferred that the thin film transistor (TFT) is bottom gate thin film transistor；
The preparation method includes：
The second transparent conductive film layer is formed on the underlay substrate, work is patterned to second transparent conductive film layer
Skill forms second transparency conducting layer and tabular public electrode of the lead；
Formation grid metal film layer on the underlay substrate of the second transparency conducting layer of the lead is being formed with, to grid gold
Category film layer is patterned technique and forms the barrier metal layer of the lead and the gate electrode of thin film transistor (TFT)；
The second insulating barrier is formed on the underlay substrate of the barrier metal layer of the lead being formed with, to second insulating barrier
It is patterned technique and forms the second via, exposes barrier metal layer；
Formation source and drain metallic diaphragm on the underlay substrate of second insulating barrier is being formed with, to the source and drain metallic diaphragm
Be patterned the Source and drain metal level of lead described in technique, and thin film transistor (TFT) source electrode and drain electrode；
The first insulating barrier is formed on the underlay substrate of the Source and drain metal level of the lead being formed with, is insulated to described first
Layer is patterned technique and forms the first via, exposes Source and drain metal level；
The first transparent conductive film layer is formed being formed with the underlay substrate of first insulating barrier, it is transparent to described first
Conductive film layer is patterned the first transparency conducting layer and slit pixel electrode that technique forms the lead.
Above-mentioned technical proposal of the invention has the beneficial effect that：
In above-mentioned technical proposal, the lead of array base palte include transparency conducting layer and below transparency conducting layer at least
Two metal levels.Wherein, transparency conducting layer and one of metal level are electrically connected with, and are formed between adjacent two metal levels
There is insulating barrier, and be electrically connected with so that lead has at least two-layer conductive channel.And the end quilt of at least one metal level is set
Insulating barrier is coated, it is to avoid it is contacted with environment, and effectively reduction lead is corroded and the bad risk that electrically conducts occurs, multilayer conducting
The design that the end of passage and at least one metal level is coated by insulating barrier, can greatly improve product yield.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
Other accompanying drawings are obtained with according to these accompanying drawings.
Fig. 1 represents the structural representation of pin leads on thin-film transistor array base-plate in the embodiment of the present invention；
Fig. 2 represents sectional views of the Fig. 1 along A-A；
Fig. 3 represents sectional views of the Fig. 1 along B-B.
Specific embodiment
Array base palte for TFT-LCD, its non-display area includes lead areas, and driving chip is by lead areas
Signal of the lead for needed for grid line and data wire provide display.In the prior art, the lead on array base palte is by transparency conducting layer
Formed, can simultaneously be formed by same transparent conductive film layer with the pixel electrode on array base palte or public electrode.Specifically, working as
Public electrode is formed in when on color membrane substrates, and the lead is formed simultaneously with pixel electrode by same transparency conducting layer.When public
Electrode is formed in when on array base palte, and the lead can simultaneously be formed with public electrode by same transparency conducting layer.
But, transparent conductive material is the transparent metal oxides such as tin indium oxide, indium zinc oxide, and conductance is larger, if
When whole piece lead is formed by transparent conductive material, the delay of signal transmission can be caused.Solution of the prior art is：Battle array
The lead of row substrate includes transparency conducting layer and metal level, and the metal level is barrier metal layer or Source and drain metal level, using only saturating
Bright conductive layer forms a bit of pattern, is electrically connected with for the pin with driving chip, and make insulating barrier via so that described
A bit of transparency conducting layer is electrically connected with the metal level of lead, so as to reduce the transmission resistance of lead.
In actual fabrication technique, follow-up test for convenience, one end that the lead of formation is located at non-display area is
Closing connection, i.e. one end that the barrier metal layer or Source and drain metal level of lead are located at non-display area is closing connection, is being surveyed
After the completion of examination, then cutting substrate so that lead it is separated.
However, can cause that barrier metal layer or the end of Source and drain metal level are directly exposed in environment after cutting substrate.Due to
The environment for manufacturing display device is not strict dry environment, and steam present in environment or other materials can cause lead
Corrosion, greatly reduces product yield.
The present invention is aiming at above-mentioned technical problem, there is provided a kind of array base palte and preparation method thereof, display device, passes through
The lead set on array base palte includes transparency conducting layer and at least two metal levels below transparency conducting layer.Wherein,
Transparency conducting layer and one of metal level are electrically connected with, and are formed with insulating barrier between adjacent two metal levels, and electrically
Connection so that lead has at least two-layer conductive channel.And the end of at least one metal level of setting is coated by insulating barrier, it is to avoid
It is contacted with environment, and effectively reduction lead is corroded and the bad risk that electrically conducts occurs.Multilayer conductive channel and at least one
The design that the end of metal level is coated by insulating barrier, can greatly improve product yield.
Below in conjunction with drawings and Examples, specific embodiment of the invention is described in further detail.Following reality
Example is applied for illustrating the present invention, but is not limited to the scope of the present invention.
Embodiment one
A kind of array base palte, including viewing area and non-display area, the non-display area are provided in the embodiment of the present invention
Domain includes lead areas, and the lead areas includes a plurality of leads, and one end and the driving chip of the lead are electrically connected with, another
End is electrically connected with specific distribution, the signal needed for for providing display for the distribution.
The lead includes the first transparency conducting layer and two metal levels below first transparency conducting layer, institute
The first transparency conducting layer is stated for being electrically connected with chip pin.First transparency conducting layer is also electric with one of metal level
Property insulating barrier is formed between connection, and adjacent two metal levels, two adjacent metal levels are electrically connected with, so that drawing
Line has at least two-layer conductive channel.And the end of at least one metal level of setting is coated by insulating barrier, it is to avoid it connects with environment
Touch, effectively reduction lead is corroded and the bad risk that electrically conducts occurs.The end of multilayer conductive channel and at least one metal level
The design that portion is coated by insulating barrier, can greatly improve product yield.
The resistivity of the resistivity less than the first transparency conducting layer of the metal level of lead is preferably provided, to reduce transmission electricity
Resistance.
Technical scheme can effectively reduce lead and be corroded there is the bad risk that electrically conducts, meanwhile, it is many
Layer electrically conducts the design of passage, substantially increases product yield.
For thin-film transistor array base-plate, its viewing area is formed with the grid line and data wire of transverse and longitudinal intersection, for limiting
Fixed multiple pixel cell.Each pixel cell includes thin film transistor (TFT) and pixel electrode.The grid of the grid line and thin film transistor (TFT)
Electrode is formed by grid metal (alloys of the metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and these metals), institute
State data wire, source electrode and drain electrode by source and drain metal (metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and this
The alloy of a little metals) formed, the pixel electrode is formed by transparent conductive material (transparent metal oxide such as ITO, IZO).Its
In, gate electrode and the grid line of thin film transistor (TFT) are electrically connected with, and the signal transmitted on grid line is used to open or close thin film transistor (TFT).
Source electrode and electrode data line is electrically connected with, drain electrode are electrically connected with pixel electrode, and the pixel voltage transmitted on data wire is by thin
Film transistor is exported to pixel electrode.Pixel electrode coordinates with public electrode, forms the driving electric field for driving liquid crystal molecule deflection,
Realize the display of specific grey-scale.
Then the lead of thin-film transistor array base-plate specifically with grid line or electrode data line is electrically connected with, for being grid line or data
Line provides the signal needed for showing.
In order to reduce production cost, the array base palte in the present embodiment, the first transparency conducting layer of lead can be with thereon
Pixel electrode or public electrode are formed by same transparent conductive film layer.
Preferably, the lead includes two metal levels, and specially barrier metal layer and Source and drain metal level can realize two-layer
Conductive channel.Wherein, the barrier metal layer and Source and drain metal level of lead be located at the first transparency conducting layer lower section, and barrier metal layer or
The end of Source and drain metal level is coated by insulating barrier.For example：The end of the barrier metal layer of lead is coated by insulating barrier, then in actual system
Make in technique, the Source and drain metal level of the lead of formation closes connection in one end of non-display area, to facilitate follow-up test work
In skill, identical signal is applied to grid line or data wire, electrology characteristic of thin film transistor (TFT) etc. is tested.Completed in test
Afterwards, then cutting substrate so that the Source and drain metal level of lead it is separated, realize the disconnection between lead.
In order to simplify the manufacture craft of array base palte, the barrier metal layer of lead is with the gate electrode of thin film transistor (TFT) by same grid
Metallic diaphragm is formed, and the Source and drain metal level of lead is with the source electrode of thin film transistor (TFT) and drain electrode by same source and drain metallic diaphragm shape
Into.Meanwhile, the first transparency conducting layer of lead can be formed with pixel electrode by same transparent conductive film layer, without logical
Cross single technique and form lead.Specifically, the grid line of array base palte, data wire can extend to non-display area, formation is drawn
The barrier metal layer and Source and drain metal level of line, lead and grid line or number are realized without making single electric connection structure
According to the electric connection of line.
In a specific embodiment, the first transparency conducting layer of lead, between barrier metal layer and Source and drain metal level
It is electrically connected with by insulating barrier via.Specifically retouched with the thin film transistor (TFT) of array base palte as bottom gate thin film transistor below
State：
The Source and drain metal level of lead be located between the first transparency conducting layer and barrier metal layer, first transparency conducting layer and
The first insulating barrier is formed between Source and drain metal level, the second insulating barrier is formed between the Source and drain metal level and barrier metal layer.
The first via is formed in first insulating barrier, exposes Source and drain metal level, the second mistake is formed with second insulating barrier
Hole, exposes barrier metal layer.The first transparency conducting layer filling, first via is in electrical contact with Source and drain metal level, the source
It is in electrical contact with barrier metal layer that leakage metal level fills second via.
Also include the second transparency conducting layer, the Source and drain metal level position of the lead it is possible to further set the lead
Between the barrier metal layer and the second transparency conducting layer.First transparency conducting layer coats barrier metal layer and Source and drain metal level
Side, and with second transparency conducting layer be electrically connected with such that it is able to form four layers of conductive channel, further improve product
Yield.
With reference to shown in Fig. 1-Fig. 3, the lead of bottom gate thin film transistor array base palte is specifically included in the embodiment of the present invention：
Second transparency conducting layer 21, is formed by transparent conductive film layer, when public electrode is formed on array base palte, second
Transparency conducting layer 21 specifically can simultaneously be formed by same transparent conductive film layer with public electrode by a patterning processes；
It is formed in the gate electrode and grid of the barrier metal layer 12 on the second transparency conducting layer 21, barrier metal layer 12 and array base palte
Line is formed simultaneously by same grid metal film layer；
The second insulating barrier 13 in barrier metal layer 12 is covered in, multiple second vias 17 is formed with the second insulating barrier 13,
Expose barrier metal layer 12, wherein, the position of the second via 17 is not fixed, can flexible positioning as needed.And grid metal
The end of layer 12 is coated by the second insulating barrier 13；
The Source and drain metal level 11 on the second insulating barrier 13 is formed in, the second via 17 is filled, is electrically connected with barrier metal layer 12
Touch, wherein, the data wire of Source and drain metal level 11 and array base palte, source electrode and drain electrode are by same source and drain metallic diaphragm shape simultaneously
Into its end exposes in the environment；
The first insulating barrier 14 in Source and drain metal level 11 is covered in, multiple first vias are formed with the first insulating barrier 14
16, expose Source and drain metal level 11, wherein, the first via 16 is corresponding with the position of the first transparency conducting layer 20；
The first transparency conducting layer 20 on the first insulating barrier 14 is formed in, by the first via 16 and the electricity of Source and drain metal level 11
Property contact, wherein, the first transparency conducting layer 20 is formed simultaneously with pixel electrode by same transparent conductive film layer, and first transparent leads
Electric layer 20 is coated on the side of Source and drain metal level 11 and barrier metal layer 12, and is electrically connected with the second transparency conducting layer 21.
Embodiment two
A kind of display device is also provided in the embodiment of the present invention, it includes array base palte, and the array base palte is using implementation
Array base palte in example one, improves product yield.
Embodiment three
Based on same inventive concept, the making side of the array base palte in a kind of embodiment one is also provided in the embodiment of the present invention
Method, the array base palte includes lead areas and viewing area, and the lead areas includes a plurality of leads, and driving chip passes through institute
State signal of the lead for needed for the distribution of viewing area provides display.
The preparation method includes：
A plurality of leads is formed on a underlay substrate, the lead is located at the lead areas, and the underlay substrate is
Bright substrate, can be glass substrate, quartz base plate or organic resin substrate.
The step of forming the lead includes：
The first transparency conducting layer is formed on the underlay substrate, first transparency conducting layer is used for and chip pin electricity
Property connection；
In at least two metal level formed below of first transparency conducting layer, first transparency conducting layer with wherein
One metal level is electrically connected with；
Wherein, insulating barrier is formed between two adjacent metal levels, and two adjacent metal levels are electrically connected with, at least
The end of one metal level is coated by insulating barrier.
The lead formed by above-mentioned steps has at least two-layer conductive channel, and the end of at least one metal level is not straight
Connect it is exposed in the environment so that it avoids the directly contact with environment in the fabrication process, can effectively reduce lead quilt
There is the bad risk that electrically conducts in corrosion, and improves product yield.
For thin-film transistor array base-plate, the preparation method also includes：
Thin film transistor (TFT) is formed on the underlay substrate, the gate electrode of the thin film transistor (TFT) is formed by grid metal, source
Electrode and drain electrode are formed by source and drain metal；
Pixel electrode is formed on the underlay substrate, the pixel electrode is formed by transparent conductive material；
The thin film transistor (TFT) and pixel electrode are located at the viewing area.
In order to reduce production cost, the array base palte in the present embodiment, thereon first transparency conducting layer and pixel of lead
Electrode or public electrode are formed simultaneously by same transparent conductive film layer.For example：First transparency conducting layer and pixel electrode of lead
The step of being formed simultaneously by same transparent conductive film layer is specially：
Transparent conductive film layer is formed on the underlay substrate, technique is patterned to the transparent conductive film layer, while
Form the first transparency conducting layer of lead and the pattern of pixel electrode.
Preferably, the lead includes two metal levels, and specially barrier metal layer and Source and drain metal level can realize two-layer
Conductive channel.Wherein, the barrier metal layer and Source and drain metal level of lead be located at the first transparency conducting layer lower section, and barrier metal layer or
The end of Source and drain metal level is coated by insulating barrier.For example：The end of the barrier metal layer of lead is coated by insulating barrier, then in actual system
Make in technique, the Source and drain metal level of the lead of formation closes connection in one end of non-display area, to facilitate follow-up test work
In skill, identical signal is applied to grid line or data wire, electrology characteristic of thin film transistor (TFT) etc. is tested.Completed in test
Afterwards, then cutting substrate so that the Source and drain metal level of lead it is separated, realize the disconnection between lead.
Then the preparation method of array base palte is specifically included in the present embodiment：
The first transparent conductive film layer is formed on the underlay substrate, work is patterned to first transparent conductive film layer
Skill forms first transparency conducting layer and pixel electrode of the lead simultaneously；
Grid metal film layer is formed on the underlay substrate, technique is patterned to the grid metal film layer while forming institute
State the barrier metal layer of lead and the gate electrode of thin film transistor (TFT)；
Source and drain metallic diaphragm is formed on the underlay substrate, the source and drain metallic diaphragm is patterned described in technique and is drawn
The Source and drain metal level of line and the source electrode of thin film transistor (TFT), drain electrode.
In above-mentioned steps, lead is formed simultaneously in the manufacture craft of thin film transistor (TFT) and pixel electrode, simplify array
The manufacture craft of substrate.
In a specific embodiment, the first transparency conducting layer of the lead, barrier metal layer and Source and drain metal level
Between be electrically connected with by insulating barrier via.Have with the thin film transistor (TFT) of array base palte as bottom gate thin film transistor below
How body description realizes the first transparency conducting layer, electrically connecting between barrier metal layer and Source and drain metal level by insulating barrier via
Connect：
Grid metal film layer is formed on a underlay substrate, the grid that technique forms the lead are patterned to grid metal film layer
The gate electrode of metal level and thin film transistor (TFT)；
The second insulating barrier is formed in the barrier metal layer of the lead and the gate electrode of thin film transistor (TFT), to the second insulating barrier
It is patterned technique and forms the second via, exposes the barrier metal layer；
Source and drain metallic diaphragm is formed on second insulating barrier, technique is patterned to source and drain metallic diaphragm and is formed described
The Source and drain metal level of lead and the source electrode of thin film transistor (TFT) and drain electrode, the Source and drain metal level fill second mistake
Hole, it is in electrical contact with barrier metal layer；
The first insulating barrier is formed in the Source and drain metal level of the lead and the source electrode of thin film transistor (TFT) and drain electrode,
Technique is patterned to the first insulating barrier and forms the first via, expose the Source and drain metal level；
The first transparent conductive film layer is formed on first insulating barrier, first transparent conductive film layer is patterned
Technique forms first transparency conducting layer and pixel electrode of the lead, and first transparency conducting layer fills first mistake
Hole, it is in electrical contact with Source and drain metal level.
It is that the first transparency conducting layer, barrier metal layer and the Source and drain metal level for being capable of achieving lead pass through insulation by above-mentioned steps
Layer via is electrically connected with.
Also include the second transparency conducting layer it is possible to further set the lead, positioned at the lower section of the metal level of lead.
Specifically, for bottom gate thin film transistor, the Source and drain metal level of the lead is located at the barrier metal layer and second and transparent leads
Between electric layer, the side of the first transparency conducting layer of lead cladding Source and drain metal level and barrier metal layer, and with described second
Transparency conducting layer is electrically connected with such that it is able to form four layers of conductive channel, it is further provided product yield.
When public electrode is formed on array base palte, the second transparency conducting layer of the lead can be with array base palte
Public electrode is formed by same transparent conductive film layer, specially：
The second transparent conductive film layer is formed on the underlay substrate, work is patterned to second transparent conductive film layer
Skill forms second transparency conducting layer and public electrode of the lead simultaneously, wherein, the pixel electrode of array base palte is slit electricity
Pole, positioned at outermost layer, the public electrode is plate electrode.
With reference to shown in Fig. 1-Fig. 3, the preparation method of bottom gate thin film transistor array base palte is specific in the embodiment of the present invention
Including：
Step S1, one underlay substrate (not shown) of offer, form the second nesa coating on the underlay substrate
Layer, technique is patterned to second transparent conductive film layer, forms the second electrically conducting transparent line 21 and tabular common electrical of lead
Pole.
Wherein, the underlay substrate can be glass substrate, quartz base plate or organic resin substrate.
Specifically, used on the underlay substrate magnetron sputtering, thermal evaporation or other film build method deposit thickness forThe second transparent conductive film layer, the second transparent conductive film layer can be ITO or IZO.In the second nesa coating
One layer of photoresist is applied on layer；Photoresist is exposed using mask plate, is developed, photoresist is formed photoresist not reserved area
Domain and photoresist reservation region, wherein, the second transparency conducting layer 21 and tabular that photoresist reservation region corresponds to lead are public
Electrode region, reservation region does not correspond to other regions to photoresist；Photoresist is etched away completely by etching technics not protect
Second transparent conductive film layer in region is stayed, remaining photoresist is peeled off, the second transparency conducting layer 21 and tabular for forming lead are public
Common electrode.
Step S2, the formation grid metal film layer on the underlay substrate for completing step S1, structure is carried out to the grid metal film layer
The gate electrode (not shown) of figure technique, the barrier metal layer 12 of formation lead, and grid line and thin film transistor (TFT).
Specifically, a layer thickness can be deposited on the underlay substrate for completing step S1 using the method for sputtering or thermal evaporation
ForGrid metal film layer, grid metal film layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W
Deng metal and the alloy of these metals, grid metal film layer can be single layer structure or sandwich construction, sandwich construction such as Cu
Mo, Ti Cu Ti, Mo Al Mo etc..One layer of photoresist is coated in grid metal film layer, photoresist is exposed using mask plate
Light, development makes photoresist form photoresist not reservation region and photoresist reservation region, wherein, photoresist reservation region correspondence
Region where the barrier metal layer 12 and grid line of lead and the gate electrode of thin film transistor (TFT), reservation region is not corresponding for photoresist
In other regions；Etch away the grid metal film layer of photoresist not reservation region completely by etching technics, peel off remaining photoetching
The gate electrode of glue, the barrier metal layer 12 of formation lead, and grid line and thin film transistor (TFT).
Step S3, on the underlay substrate for completing step S2 the second insulating barrier 13 is formed, structure is carried out to the second insulating barrier 13
Figure technique forms the second via 17, exposes the barrier metal layer 12 of lead.
Specifically, chemical vapor deposition (PECVD) method can be strengthened with using plasma, in the substrate by step S2
Deposit thickness is about on substrateThe second insulating barrier 13, wherein, the material of the second insulating barrier 13 can select oxygen
Compound, nitride or nitrogen oxides, the second insulating barrier 13 can be individual layer, double-deck or sandwich construction.Specifically, the second insulation
Layer 13 can be SiNx, SiOx or Si (ON) x.
One layer of photoresist is applied on the second insulating barrier 13；Photoresist is exposed using mask plate, is developed, make photoetching
Glue forms photoresist not reservation region and photoresist reservation region, wherein, reservation region does not correspond to the second via 17 to photoresist
Region, photoresist reservation region corresponds to other regions；Etch away photoresist not reservation region completely by etching technics
The second insulating barrier, formed the second via 17, expose the barrier metal layer 12 of lead.Peel off remaining photoresist.
Step S4, the formation source and drain metallic diaphragm on the underlay substrate for completing step S3, structure is carried out to source and drain metallic diaphragm
Figure technique, forms the Source and drain metal level 11, data wire of lead and the source electrode and drain electrode of thin film transistor (TFT), wherein, source and drain
Metal level 11 fills the second via 17, in electrical contact with barrier metal layer 12.
Specifically, magnetron sputtering, thermal evaporation or other film build methods can be used on by the underlay substrate of step S3
Deposition a layer thickness is aboutSource and drain metallic diaphragm, source and drain metallic diaphragm can be Cu, Al, Ag, Mo, Cr,
The alloy of the metals such as Nd, Ni, Mn, Ti, Ta, W and these metals.Source and drain metallic diaphragm can be single layer structure or multilayer knot
Structure, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc..
One layer of photoresist is coated on source and drain metallic diaphragm, photoresist is exposed using mask plate, developed, make photoetching
Glue forms photoresist not reservation region and photoresist reservation region, wherein, photoresist reservation region corresponds to the source and drain gold of lead
Region where the source electrode and drain electrode of category layer 11, data wire and thin film transistor (TFT), reservation region does not correspond to photoresist
Other regions；Etch away the source and drain metallic diaphragm of photoresist not reservation region completely by etching technics, peel off remaining photoetching
Glue, forms the Source and drain metal level 11, data wire of lead and the source electrode and drain electrode of thin film transistor (TFT).
Step S5, on the underlay substrate for completing step S4 the first insulating barrier 14 is formed, structure is carried out to the first insulating barrier 14
Figure technique forms the first via 16, exposes the Source and drain metal level 11 of lead.
Specifically, magnetron sputtering, thermal evaporation, PECVD or other film forming sides are used on by the underlay substrate of step S4
Method deposit thickness isThe first insulating barrier 14, wherein, the material of the first insulating barrier 14 can from oxide,
Nitride or nitrogen oxides, specifically, the first insulating barrier 14 can be SiNx, SiOx or Si (ON) x.First insulating barrier 14 can be with
It is single layer structure, or the double-layer structure constituted using silicon nitride and silica.
One layer of photoresist is applied on the first insulating barrier 14；Photoresist is exposed using mask plate, is developed, make photoetching
Glue forms photoresist not reservation region and photoresist reservation region, wherein, reservation region does not correspond to the first via 16 to photoresist
Region, photoresist reservation region corresponds to other regions；Etch away photoresist not reservation region completely by etching technics
Passivation layer, formed the first via 16, expose the Source and drain metal level 11 of lead.Peel off remaining photoresist.
Step S6, on the underlay substrate for completing step S5 the first transparent conductive film layer is formed, it is transparent to described first to lead
Electrolemma layer is patterned the first transparency conducting layer 20 and slit pixel electrode that technique forms lead, wherein, the first of lead
Transparency conducting layer 20 fills the first via 16, in electrical contact with Source and drain metal level 11.
Specifically, using magnetron sputtering, thermal evaporation or other film build methods deposition on by the underlay substrate of step S5
Thickness isThe first transparent conductive film layer, the first transparent conductive film layer can be ITO or IZO.It is transparent first
One layer of photoresist is applied on conductive film layer；Photoresist is exposed using mask plate, is developed, photoresist is formed photoresist not
Reservation region and photoresist reservation region, wherein, photoresist reservation region correspond to lead the first transparency conducting layer 20 and
Region where slit pixel electrode, reservation region does not correspond to other regions to photoresist；Etched away completely by etching technics
First transparent conductive film layer of photoresist not reservation region, peels off remaining photoresist, forms the first transparency conducting layer of lead
20 and slit pixel electrode, the first transparency conducting layer 20 fills the first via 16, in electrical contact with Source and drain metal level 11.
So far the making of array base palte in the embodiment of the present invention is completed.
Technical scheme, the lead of array base palte include transparency conducting layer and below transparency conducting layer extremely
Few two metal levels.Wherein, transparency conducting layer and one of metal level are electrically connected with, and shape between adjacent two metal levels
Into there is insulating barrier, and it is electrically connected with so that lead has at least two-layer conductive channel.And the end of at least one metal level is set
Coated by insulating barrier, it is to avoid it is contacted with environment, effectively reduction lead is corroded and the bad risk that electrically conducts occurs, and multilayer is led
The design that the end of circulation passage and at least one metal level is coated by insulating barrier, can greatly improve product yield.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, on the premise of the technology of the present invention principle is not departed from, some improvement and replacement can also be made, these improve and replace
Also should be regarded as protection scope of the present invention.
Claims (15)
1. a kind of array base palte, including lead areas, the lead areas includes a plurality of leads, and the lead includes that first is transparent
Conductive layer, first transparency conducting layer is used to be electrically connected with chip pin, it is characterised in that the lead also includes：
At least two metal levels, positioned at first transparency conducting layer lower section, first transparency conducting layer and one of gold
Category layer is electrically connected with；
Wherein, the second insulating barrier is formed between two adjacent metal levels, and two adjacent metal levels are electrically connected with, at least
One end of metal level is coated by the second insulating barrier, has between first transparency conducting layer and the metal level being disposed below
There is the first insulating barrier, first transparency conducting layer is electrically connected with the metal level being disposed below.
2. array base palte according to claim 1, it is characterised in that the lead includes two metal levels；
The end of one of metal level is coated by insulating barrier.
3. array base palte according to claim 2, it is characterised in that the lead also includes：
Second transparency conducting layer, positioned at described two metal levels lower section；
First transparency conducting layer coats the side of described two metal levels, and electrically connects with second transparency conducting layer
Connect.
4. array base palte according to claim 3, it is characterised in that the array base palte also includes viewing area, described
Viewing area includes：
Thin film transistor (TFT), the gate electrode of the thin film transistor (TFT) is formed by grid metal, and source electrode and drain electrode are by source and drain metal shape
Into；
Pixel electrode, is formed by transparent conductive material；
Two metal levels of the lead are respectively barrier metal layer and Source and drain metal level.
5. array base palte according to claim 4, it is characterised in that the first transparency conducting layer of the lead and pixel electricity
Pole is formed by same transparent conductive film layer；
The barrier metal layer of the lead is formed with the gate electrode of thin film transistor (TFT) by same grid metal film layer；
The Source and drain metal level of the lead is formed with the source electrode of thin film transistor (TFT) and drain electrode by same source and drain metallic diaphragm.
6. array base palte according to claim 4, it is characterised in that the viewing area also includes：
Public electrode, is formed by transparent conductive material；
Second transparency conducting layer of the lead is formed with the public electrode by same transparent conductive film layer, wherein, the picture
Plain electrode is gap electrode, and the public electrode is plate electrode.
7. array base palte according to claim 6, it is characterised in that the thin film transistor (TFT) is bottom gate thin film crystal
Pipe；
The Source and drain metal level of the lead be located between the first transparency conducting layer and barrier metal layer, first transparency conducting layer and
The first insulating barrier is formed between Source and drain metal level, the second insulating barrier is formed between the Source and drain metal level and barrier metal layer；
The first via is formed with first insulating barrier, exposes Source and drain metal level；Second is formed with second insulating barrier
Via, exposes barrier metal layer；
It is in electrical contact with Source and drain metal level that first transparency conducting layer fills first via；The Source and drain metal level filling
Second via is in electrical contact with barrier metal layer；
Second transparency conducting layer is located at barrier metal layer lower section, and directly in electrical contact with barrier metal layer, described first transparent leads
Electric layer is coated on the side of Source and drain metal level and barrier metal layer, in electrical contact with the second transparency conducting layer.
8. a kind of display device, including array base palte, it is characterised in that the array base palte uses claim any one of 1-7
Described array base palte.
9. a kind of preparation method of the array base palte described in any one of claim 1-7, the array base palte includes lead areas,
The preparation method includes：
A plurality of leads is formed on a underlay substrate, the lead is located at the lead areas；
The step of forming the lead includes：
The first transparency conducting layer is formed on the underlay substrate, first transparency conducting layer is used to electrically connect with chip pin
Connect, it is characterised in that the step of forming the lead also includes：
In at least two metal level formed below of first transparency conducting layer, first transparency conducting layer and one of them
Metal level is electrically connected with；
Wherein, the second insulating barrier is formed between two adjacent metal levels, and two adjacent metal levels are electrically connected with, at least
One end of metal level is coated by the second insulating barrier, has between first transparency conducting layer and the metal level being disposed below
There is the first insulating barrier, first transparency conducting layer is electrically connected with the metal level being disposed below.
10. preparation method according to claim 9, it is characterised in that the lead includes two metal levels；
The end of one of metal level is coated by insulating barrier.
11. preparation methods according to claim 10, it is characterised in that the step of forming the lead also includes：
In second transparency conducting layer formed below of described two metal levels；
First transparency conducting layer coats the side of described two metal levels, is electrically connected with second transparency conducting layer.
12. preparation methods according to claim 11, it is characterised in that the array base palte also includes viewing area, institute
Stating preparation method also includes：
Thin film transistor (TFT) is formed on the underlay substrate, the gate electrode of the thin film transistor (TFT) is formed by grid metal, source electrode
Formed by source and drain metal with drain electrode；
Pixel electrode is formed on the underlay substrate, the pixel electrode is formed by transparent conductive material；
The thin film transistor (TFT) and pixel electrode are located at the viewing area, and two metal levels of the lead are respectively grid metal
Layer and Source and drain metal level.
13. preparation methods according to claim 12, it is characterised in that the step of forming the lead includes：
The first transparent conductive film layer is formed on the underlay substrate, it is same to be patterned technique to first transparent conductive film layer
When form first transparency conducting layer and pixel electrode of the lead；
Grid metal film layer is formed on the underlay substrate, the grid metal film layer is patterned described in technique formation simultaneously and drawn
The barrier metal layer of line and the gate electrode of thin film transistor (TFT)；
Source and drain metallic diaphragm is formed on the underlay substrate, lead described in technique is patterned to the source and drain metallic diaphragm
The source electrode of Source and drain metal level and thin film transistor (TFT), drain electrode.
14. preparation methods according to claim 12, it is characterised in that the step of forming the lead also includes：
The second transparent conductive film layer is formed on the underlay substrate, it is same to be patterned technique to second transparent conductive film layer
When form second transparency conducting layer and public electrode of the lead, wherein, the pixel electrode is gap electrode, described public
Electrode is plate electrode.
15. preparation methods according to claim 14, it is characterised in that the thin film transistor (TFT) is bottom gate thin film crystal
Pipe；
The preparation method includes：
The second transparent conductive film layer is formed on the underlay substrate, technique shape is patterned to second transparent conductive film layer
Into second transparency conducting layer and tabular public electrode of the lead；
Formation grid metal film layer on the underlay substrate of the second transparency conducting layer of the lead is being formed with, to the grid metal film
Layer is patterned technique and forms the barrier metal layer of the lead and the gate electrode of thin film transistor (TFT)；
The second insulating barrier is formed on the underlay substrate of the barrier metal layer of the lead being formed with, second insulating barrier is carried out
Patterning processes form the second via, expose barrier metal layer；
Formation source and drain metallic diaphragm on the underlay substrate of second insulating barrier is being formed with, the source and drain metallic diaphragm is being carried out
The Source and drain metal level of lead described in patterning processes, and thin film transistor (TFT) source electrode and drain electrode；
The first insulating barrier is formed on the underlay substrate of the Source and drain metal level of the lead being formed with, first insulating barrier is entered
Row patterning processes form the first via, expose Source and drain metal level；
The first transparent conductive film layer is formed being formed with the underlay substrate of first insulating barrier, to first electrically conducting transparent
Film layer is patterned the first transparency conducting layer and slit pixel electrode that technique forms the lead.
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| CN108761887B (en) * | 2018-04-28 | 2020-03-27 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN208999706U (en) | 2018-08-27 | 2019-06-18 | 惠科股份有限公司 | A kind of display panel and display device |
| CN112002700A (en) * | 2020-08-05 | 2020-11-27 | 深圳市华星光电半导体显示技术有限公司 | Display panel, display device and display system |
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| CN103439844A (en) * | 2013-08-30 | 2013-12-11 | 京东方科技集团股份有限公司 | Array substrate, display device and method for manufacturing array substrate |
| CN103681692A (en) * | 2013-11-29 | 2014-03-26 | 北京京东方光电科技有限公司 | Array substrate, production method thereof and display device |
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| CN103681692A (en) * | 2013-11-29 | 2014-03-26 | 北京京东方光电科技有限公司 | Array substrate, production method thereof and display device |
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