CN104393001B - Thin-film transistor array base-plate and preparation method thereof, display device - Google Patents
Thin-film transistor array base-plate and preparation method thereof, display device Download PDFInfo
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- CN104393001B CN104393001B CN201410578332.8A CN201410578332A CN104393001B CN 104393001 B CN104393001 B CN 104393001B CN 201410578332 A CN201410578332 A CN 201410578332A CN 104393001 B CN104393001 B CN 104393001B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to display technology field, a kind of thin-film transistor array base-plate and preparation method thereof, display device are disclosed.The metallic conduction layer surface of the non-display area of the array base palte is covered with oxidation-resisting structure; to prevent the metal conducting layer to be oxidized; so as to be exposed in the environment when the metal conducting layer; if and now formation is only positioned at the film pattern of viewing area; the oxidation-resisting structure can protect the metal conducting layer not oxidized; reduce the transmission resistance of the metal conducting layer; the metal conducting layer and the electrical contact characteristic for the conductive layer being subsequently formed are improved, so as to improve the quality of array base palte.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of thin-film transistor array base-plate and preparation method thereof,
Display device.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, referred to as
TFT-LCD) there is small volume, the features such as low in energy consumption, radiationless, manufacturing cost is relatively low, in current flat-panel monitor city
Field occupies leading position.TFT-LCD array substrate is one of TFT-LCD important component.Wherein, array base palte includes display
Region and the non-display area positioned at viewing area periphery, the grid line and data wire of transverse and longitudinal intersection, limit are formed with viewing area
Fixed multiple pixel cells, each pixel cell includes thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) and pixel
Electrode, TFT drain electrode and pixel electrode are electrically connected with, and source electrode and data line electrical connection, gate electrode and grid line electrically connect
Connect.The pixel voltage transmitted on thin film transistor (TFT), data wire is opened by grid line to transmit to pixel electricity by thin film transistor (TFT)
Pole, for driving liquid crystal molecule to deflect, realizes the display of specific grey-scale.And non-display area includes PAD region and GOA regions,
GOA regions are the regions of integrated gate switch circuit, and the signal wire of the gate switch circuit is by forming the letter on array base palte
The conductive layer of number line (including grid line, data wire equisignal line) is formed, and can save grid integrated drive electronics.PAD region is
For crimp region, positioned at one of array base palte while or it is adjacent two while on, be by the grid line on array base palte, data wire etc.
Signal wire crimps the region of connection, including grid line PAD region, data wire PAD region etc. with the pin of external drive circuit plate.
The signal wire of PAD region is also formed by the conductive layer for forming the signal wire on array base palte, and the superiors are to leak cruelly on surface
Transparency conducting layer is formed, and is crimped for the pin with driving chip, as shown in Figure 1.
At present, the main flow resolution ratio of in the market indicator screen has evolved to FHD (more than 400 PPI), QHD (480 with
Upper PPI) into trend.With PPI increase, resolution ratio becomes big, and characteristic size diminishes, metallic signal lines in array substrate
RC delays require more and more higher, and in order to obtain good conductive characteristic, the metallic signal lines of array base palte are generally used
Metal alloy layer, such as Ti-Al-Ti.
The array base palte of high PPI displays mainly uses LTPS techniques, with reference to shown in Fig. 2, traditional LTPS tft array
Substrate basic technology is：2 → polysilicon active layer of cushion (not shown) → gate insulation layer 3 → barrier metal layer, 4 → interlayer
The transparency conducting layer 7 of 5 → Source and drain metal level of insulating barrier, 6 → flatness layer (ACR, figure not shown in) → first, be for driving electric field
The array base palte of transverse electric field, in addition to form the second transparency conducting layer 8.Wherein, the ACR layer is only distributed in array base palte
Viewing area, in the manufacture craft for forming ACR layer, the Source and drain metal level of GOA regions and PAD region signal wire is directly leaked cruelly
In environment, when ACR solidifies, it is easy to be oxidized, by strong influence GOA regions and the resistance of PAD region Source and drain metal level
And Source and drain metal level and the performance in electrical contact of the transparency conducting layer of subsequent technique formation.
The content of the invention
The present invention provides a kind of thin-film transistor array base-plate and preparation method thereof, display device, to solve when non-aobvious
Show the metal conducting layer exposure in region in the environment, and if now formed and be only positioned at the film pattern of viewing area, gold can be caused
Belong to the problem of conductive layer is oxidized.
In order to solve the above technical problems, the present invention provides a kind of thin-film transistor array base-plate, including viewing area and position
Non-display area in viewing area periphery, the thin-film transistor array base-plate includes the metal positioned at the non-display area
Conductive layer, and the first oxidation-resisting structure of the metallic conduction layer surface is covered, to protect the metal conducting layer not by oxygen
Change.
The present invention also provides a kind of display device, including thin-film transistor array base-plate as described above.
The present invention also provides a kind of preparation method of thin-film transistor array base-plate, the thin-film transistor array base-plate bag
Viewing area and the non-display area positioned at viewing area periphery are included, the preparation method includes：
Form the metal conducting layer positioned at the non-display area；
The first oxidation-resisting structure of the covering metallic conduction layer surface is formed, to protect the metal conducting layer not by oxygen
Change..
The above-mentioned technical proposal of the present invention has the beneficial effect that：
In above-mentioned technical proposal, the metallic conduction layer surface of the non-display area of array base palte covered with oxidation-resisting structure,
To prevent the metal conducting layer to be oxidized, so that when the metal conducting layer exposes in the environment, and if now being formed only
Film pattern positioned at viewing area, the oxidation-resisting structure can protect the metal conducting layer not oxidized, reduce institute
The transmission resistance of metal conducting layer is stated, the metal conducting layer and the electrical contact characteristic for the conductive layer being subsequently formed is improved,
So as to improve the quality of array base palte.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 represents the structural representation of array base palte；
Fig. 2 represents sectional views of the Fig. 1 along A-A in the prior art；
Fig. 3 represents sectional views of the Fig. 1 along A-A in the embodiment of the present invention；
Fig. 4-Fig. 7, Fig. 9 and Figure 10 represent the manufacturing process schematic diagram of array base palte in the embodiment of the present invention；
Fig. 8 represents Fig. 7 top view.
Embodiment
Thin-film transistor array base-plate includes viewing area and the non-display area positioned at viewing area periphery, non-display
Region is formed with the conductive layer of transmission signal, and the signal needed for for providing display for viewing area, the conductive layer includes gold
Belong to conductive layer.To simplify manufacture craft, the conductive layer of non-display area and the conductive layer of viewing area pass through same material film
Patterning processes formed.
When forming the film pattern for being only located at viewing area formation, such as：The flatness layer of liquid crystal display device, if now non-
In the environment, there is the problem of being easily oxidized in the metal conducting layer for the metal conducting layer exposure of viewing area.
In order to solve the above-mentioned technical problem, the present invention provides a kind of thin-film transistor array base-plate extremely preparation method, leads to
The oxidation-resisting structure for forming covering positioned at the metallic conduction layer surface of non-display area is crossed, the metal conducting layer can be protected not
It is oxidized, reduces the transmission resistance of the metal conducting layer, improve the metal conducting layer and the conductive layer being subsequently formed
Electrical contact characteristic, so as to improve the quality of array base palte.
Below in conjunction with drawings and examples, the embodiment to the present invention is described in further detail.Following reality
Applying example is used to illustrate the present invention, but is not limited to the scope of the present invention.
A kind of preparation method of thin-film transistor array base-plate, the thin film transistor (TFT) array are provided in the embodiment of the present invention
Substrate includes viewing area and the non-display area positioned at viewing area periphery, and the preparation method includes：
Form the metal conducting layer positioned at the non-display area；
The first oxidation-resisting structure of the covering metallic conduction layer surface is formed, to protect the metal conducting layer not by oxygen
Change.
By above-mentioned technical proposal, the metal conducting layer of non-display area can be protected not oxidized, reduce the gold
Belong to the transmission resistance of conductive layer, improve the metal conducting layer and the electrical contact characteristic for the conductive layer being subsequently formed, so that
Improve the quality of array base palte.
Correspondingly, a kind of thin-film transistor array base-plate is also provided in the embodiment of the present invention, it includes viewing area and position
Non-display area in viewing area periphery.The thin-film transistor array base-plate includes the metal positioned at the non-display area
Conductive layer, and the first oxidation-resisting structure of the metallic conduction layer surface is covered, first oxidation-resisting structure is used to protect
The metal conducting layer is not oxidized.
Preferably, after the step of forming the oxidation-resisting structure of the covering metallic conduction layer surface, only position is re-formed
Film pattern in viewing area, so as to be only located at being formed in the manufacture craft of the film pattern of viewing area, positioned at non-aobvious
Show that the metallic conduction layer surface in region, covered with oxidation-resisting structure, can protect the metal conducting layer not oxidized.
In order to simplify the manufacture craft of array base palte, the conducting layer figure of non-display area and the conductive layer figure of viewing area
Shape is formed simultaneously by the patterning processes to same material film.
Multiple pixel cells are formed with the viewing area of thin-film transistor array base-plate, each pixel cell includes film
Transistor, the thin film transistor (TFT) includes gate electrode, gate insulation layer, active layer pattern, source electrode and drain electrode.Wherein, grid line
With gate electrode by same grid metal (metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and these metals
Alloy) patterning processes of film are formed, data wire, source electrode and drain electrode by same source and drain metal (Cu, Al, Ag, Mo,
The alloy of the metals such as Cr, Nd, Ni, Mn, Ti, Ta, W and these metals) patterning processes of film are formed.
Then, the metal conducting layer in the embodiment of the present invention positioned at non-display area includes barrier metal layer and Source and drain metal level.
For liquid crystal display device, the pixel cell of thin-film transistor array base-plate also (is led including pixel electrode by transparent
Conductive film is formed).In order to ensure the reliability of non-display area signal transmission, the conductive layer of non-display area also includes being located at institute
The transparency conducting layer on the first oxidation-resisting structure is stated, the transparency conducting layer can pass through in first oxidation-resisting structure
One via and metal conducting layer are in electrical contact.That is, the signal wire of non-display area includes metal conducting layer and positioned at metallic conduction
Transparency conducting layer above layer.
Then, the preparation method of thin-film transistor array base-plate also includes in the embodiment of the present invention：
Transparency conducting layer is formed on first oxidation-resisting structure；
The first via is formed in first oxidation-resisting structure, the transparency conducting layer passes through first via and institute
State metal conducting layer in electrical contact.
Further, can set non-display area signal wire include grid metal conductive layer, Source and drain metal level and thoroughly
Bright conductive layer.
In the embodiment of the present invention, the step of forming the first oxidation-resisting structure for covering metal conducting layer patterned surface includes：
Oxidation barrier film is formed on the metal conducting layer；
Photoresist is coated on the oxidation barrier film, photoresist is exposed using halftoning or gray tone mask plate
Light, forming photoresist, region and the reservation region of photoresist half is not fully retained in reservation region, photoresist, and the photoresist half retains
Region correspondence described the is fully retained in the region where via in region correspondence first oxidation-resisting structure, the photoresist
One oxidation-resisting structure removes the region where the part of the first via, and reservation region does not correspond to other regions to the photoresist；
Etch away the oxidation barrier film of the photoresist not reservation region；
The photoresist of the reservation region of photoresist half is removed by cineration technics；
Etching oxidation barrier film certain thickness, positioned at the reservation region of photoresist half；
Remove remaining photoresist.
By above-mentioned steps the first oxidation-resisting structure and the first anti-oxidant knot can be formed simultaneously by a patterning processes
The figure of the first via region in structure, first via specifically corresponds to the reservation region of photoresist half.
Further, the step of the first oxidation-resisting structure for forming covering metal conducting layer patterned surface, also includes：
After the step of being only located at the film pattern of viewing area is formed, etch away the reservation region of photoresist half and remain
Remaining oxidation barrier film, the first via formed in first oxidation-resisting structure and first oxidation-resisting structure, due to
It is only located at being formed in the manufacture craft of the film pattern of viewing area, metallic conduction layer pattern overlying is stamped the first anti-oxidant knot
Structure, can effectively protect it from being oxidized.Meanwhile, can only be formed in the first oxidation-resisting structure by etching technics first
Via, eliminates the patterning processes for making the first via, simplifies manufacturing process.
Thin film transistor (TFT) (Thin Film Transistor, TFT) can be divided into polysilicon according to the difference of active layer material
Arrangement shape of (Poly-Si, P-Si) TFT and non-crystalline silicon (a-Si) TFT, the P-Si molecular structure in a crystal grain (Grain)
State is neat and directive, therefore electron mobility is faster 200-300 times than arranging mixed and disorderly non-crystalline silicon.P-Si making
Technique is mainly comprising high temperature polysilicon (HTPS) and low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) two
Plant technique.The array base palte of high resolution display mainly uses LTPS techniques.
For liquid crystal display device, it is preferable that non-display area also includes transparency conducting layer, electrically connects with metal conducting layer
Connect, to ensure the transmitting of electrical signal.In a detailed embodiment, thin-film transistor array base-plate is LTPS arrays
Substrate, including thin film transistor (TFT) and pixel electrode positioned at viewing area, and in the making work of thin film transistor (TFT) and pixel electrode
In skill, while forming the conductive layer of non-display area, specifically include：
Drain metallic film is formed, technique is patterned to the drain metallic film, the source electricity of thin film transistor (TFT) is formed
Pole and drain electrode, and positioned at the Source and drain metal level of non-display area；
Transparent conductive film is formed, technique is patterned to the transparent conductive film, pixel electrode is formed and positioned at non-
The transparency conducting layer of viewing area, the transparency conducting layer and Source and drain metal level are electrically connected with.
Due to after the source electrode and drain electrode of thin film transistor (TFT) is formed, the flatness layer for being only located at viewing area can be formed.
In the manufacture craft (including the coating of acrylic material, exposure imaging and solidification) for making flatness layer, the source of non-display area
Leak metal level exposure in the environment, when flatness layer solidifies, be easily oxidized.By technical scheme, can effectively it protect
The Source and drain metal level of non-display area is not oxidized, and specific scheme is：
The source electrode and drain electrode of thin film transistor (TFT) are formed on a substrate, and positioned at the source and drain metal of non-display area
Layer；
Form the first oxidation-resisting structure of the covering Source and drain metal level；
Flatness layer is formed being formed with the substrate of first oxidation-resisting structure, the flatness layer is only located at film crystal
The viewing area of pipe array base palte.
Pixel electrode and the transparency conducting layer positioned at non-display area are formed being formed with the substrate of the flatness layer, institute
State transparency conducting layer and Source and drain metal level is electrically connected with.
In the patterning processes for forming the transparency conducting layer, because the transparency conducting layer is low-temperature transparent conductive layer,
Easily remained when transparent conductive film is etched, (be specially the side of viewing area especially in the big position of film layer segment difference
Boundary position, because flatness layer is only located at viewing area).In the prior art, because Source and drain metal level is exposed outside, residual it is transparent
Conductive film causes adjacent Source and drain metal level to link together, and forms short circuit.And by using technical scheme, i.e.,
Make in etching technics exist residual transparent conductive film, due in Source and drain metal level covered with first oxidation-resisting structure,
Adjacent Source and drain metal level connection short circuit is not resulted in, highdensity line arrangement is advantageously implemented yet.
In the manufacture craft of LTPS array base paltes, pixel electrode passes through the via and thin film transistor (TFT) in the flatness layer
Drain electrode it is in electrical contact, because the manufacture craft of flatness layer is：The coating of acrylic material, exposure imaging and solidification, i.e.
Curing process is just carried out after the via for exposing drain electrode is formed in the flatness layer, so can also there is the electric leakage of thin film transistor (TFT)
The problem of being easily oxidized.
Based on above-mentioned technical proposal, the first of the Source and drain metal level for forming covering non-display area in the embodiment of the present invention
While oxidation-resisting structure, the second oxidation-resisting structure of the drain electrode surface of cover film transistor is formed, to protect the leakage
Electrode is not oxidized, i.e. second oxidation-resisting structure and the first oxidation-resisting structure are identical material.
Further, while forming the first via in first oxidation-resisting structure, in the described second anti-oxidant knot
The second via is formed in structure, the pixel electrode is in electrical contact by the drain electrode of second via and thin film transistor (TFT).
With reference to shown in Fig. 3, Fig. 4-Figure 10, below using liquid crystal display device and driving transverse electric field as transverse electric field
Exemplified by LTPS array base paltes, carry out the specific preparation method introduced in the embodiment of the present invention, comprise the following steps：
Step S1, one underlay substrate 1 of offer, such as：The transparency carriers such as glass substrate, quartz base plate, organic resin substrate, and
Cushion 2 is formed on underlay substrate 1, the active layer pattern of thin film transistor (TFT) is formed on the buffer layer 2, then in active layer figure
Gate insulation layer 3 is formed in case.
Wherein, the material of active layer can be silicon semiconductor, or metal-oxide semiconductor (MOS).Cushion 2 and grid
The material of insulating barrier 3 can select oxide, nitride or nitrogen oxides, can be individual layer, double-deck or sandwich construction.Specifically
Ground, gate insulation layer 3 can be SiNx, SiOx or Si (ON) x.
Step S2, by the patterning processes to same grid metal film complete step S1 underlay substrate 1 on simultaneously shape
Into the barrier metal layer 4 positioned at non-display area, and the gate electrode and grid line positioned at viewing area；
Specifically, a thickness can be deposited on the underlay substrate 1 for completing step S1 using the method for sputtering or thermal evaporation
Spend and beGrid metal film, barrier metal layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W etc.
The alloy of metal and these metals, barrier metal layer can be single layer structure or sandwich construction, sandwich construction such as Cu Mo,
Ti Cu Ti, Mo Al Mo etc..
One layer of photoresist is coated in grid metal film, photoresist is exposed using mask plate, develops, makes photoresist
Photoresist not reservation region and photoresist reservation region are formed, wherein, photoresist reservation region corresponds to barrier metal layer 4, grid line
With the region of gate electrode, reservation region does not correspond to other regions to photoresist；Photoetching is etched away by etching technics completely
The grid metal film of glue not reservation region, peels off remaining photoresist, forms barrier metal layer 4, grid line and gate electrode.
Step S3, the formation interlayer insulating film 5 on the underlay substrate 1 for completing step S2, it is exhausted in interlayer by patterning processes
Via is formed in edge layer 5, exposes barrier metal layer 4；
Wherein, the material of interlayer insulating film 5 can select oxide, nitride or nitrogen oxides, can be individual layer, bilayer
Or sandwich construction.Specifically, interlayer insulating film 5 can be SiNx, SiOx or Si (ON) x.
Step S4, the formation on the underlay substrate 1 for completing step S3 by the patterning processes to same drain metallic film
Positioned at the Source and drain metal level 6 of non-display area, and the source electrode, drain electrode and data line positioned at viewing area；
Wherein, Source and drain metal level 6 is in electrical contact by the via in interlayer insulating film 5 and barrier metal layer 4.
Specifically, magnetron sputtering, thermal evaporation or other film build methods can be used on the underlay substrate 1 for completing step S3
Depositing a layer thickness is aboutDrain metallic film, drain metallic film can be Cu, Al, Ag, Mo, Cr,
The alloy of the metals such as Nd, Ni, Mn, Ti, Ta, W and these metals.Source and drain metal level can be single layer structure or multilayer knot
Structure, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc..
Step S5, the formation oxidation barrier film 10 on the underlay substrate 1 for completing step S4, structure is carried out to oxidation barrier film 10
Figure technique formation oxidation-resisting structure 12；
Wherein, the material of oxidation barrier film 10 can select oxide, nitride or nitrogen oxides, can for individual layer,
Double-deck or sandwich construction.Specifically, oxidation barrier film 10 can be SiNx, SiOx or Si (ON) x.
It is possible, firstly, to which using plasma, which strengthens chemical vapor deposition (PECVD) method, completes step S4 substrate base
Oxidation barrier film 10 is formed on plate 1；
Afterwards, photoresist 11 is formed on oxidation barrier film 10；
Afterwards, photoresist 11 is exposed by gray tone or intermediate tone mask plate 20, as shown in figure 4, wherein, mask
Plate 20 includes semi-transparent region 13, light tight region 14 and full transmission region 15.Photoresist 11 after exposure includes photoresist half
Region 24 and photoresist not reservation region is fully retained in reservation region 23, photoresist, with reference to shown in Fig. 5.Wherein, photoresist half is protected
The region where the first via in the first oxidation-resisting structure 12 of correspondence of region 23 is stayed, the correspondence of region 24 the is fully retained in photoresist
One oxidation-resisting structure 12 removes the region where the part of the first via, and reservation region does not correspond to other regions to photoresist；
Afterwards, the oxidation barrier film 10 of photoresist not reservation region is etched away；
Afterwards, the photoresist of the reservation region 23 of photoresist half is removed by cineration technics, and region is fully retained to photoresist
24 photoresist has certain thinning；
Then, oxidation barrier film 10 certain thickness, positioned at the reservation region 23 of photoresist half is etched；
Finally, remaining photoresist is peeled off, as shown in Figure 6.
So far, the first oxidation-resisting structure 12 and first for forming the Source and drain metal level 6 of covering non-display area is anti-oxidant
The figure of the first via region in structure 12, wherein, the first via correspondence reservation region 23 of photoresist half.
During above-mentioned manufacture craft, while also being formed and the first oxidation-resisting structure on the drain electrode of thin film transistor (TFT)
12 shape identical the second oxidation-resisting structure (not shown)s, are covered in the surface of drain electrode, because in follow-up flatness layer
In manufacture craft, drain electrode exposure is also easily oxidized in the environment.
Step S6, on the underlay substrate 1 for completing step S5 form flatness layer, the material of shown flatness layer is acrylic material
Material, is only located at the viewing area of array base palte.In the manufacture craft of flatness layer, the source and drain gold of the non-display area of array base palte
Belong to the surface of layer 6 covered with oxidation barrier film, will not be oxidized；
Meanwhile, the drain electrode surface of thin film transistor (TFT) is again covered with oxidation barrier film, will not be oxidized
Wherein, the manufacture craft of flatness layer is：
Viewing area on the underlay substrate 1 for completing step S5 coats acrylic material, forms acrylic film；
The acrylic film of formation is exposed by mask plate, developed, acrylic reservation region and acrylic is formed
Reservation region, the region of acrylic not where a part at least corresponding drain electrode of reservation region, do not expose covering drain electrode table
The part of the thinner thickness of second oxidation-resisting structure in face, other regions of acrylic reservation region correspondence；
The acrylic film of acrylic reservation region is solidified, the flatness layer for being only located at viewing area is formed, it is described
The via of the part for the thinner thickness for exposing the second oxidation-resisting structure is provided with flatness layer, wherein, the described second anti-oxidant knot
Structure is covered in the surface of drain electrode.
Step S7, after step S6 is completed, etch away the oxidation barrier film of thinner thickness, form the first oxidation-resisting structure
12, the first via 30 is provided with the first oxidation-resisting structure 12, as shown in Figure 7；
Fig. 8 show Fig. 7 top view, it is seen then that the middle part of the first oxidation-resisting structure 12 of formation has the first via 30,
Expose following Source and drain metal level 6.
In this step, while etching away the portion of the thinner thickness for the second oxidation-resisting structure for being covered in drain electrode surface
Point, the second via is formed, exposes drain electrode, can make it that the pixel electrode and drain electrode that are subsequently formed are in electrical contact, is turned on.
Step S8, by the patterning processes to same first nesa coating complete step S7 underlay substrate 1 on shape
Into the first transparency conducting layer 7 positioned at non-display area, and the pixel electrode positioned at viewing area, as shown in Figure 9；
Specifically, using magnetron sputtering, thermal evaporation or other film build methods deposition on the underlay substrate 1 by step S7
Thickness isTransparent conductive film, transparent conductive film can be ITO or IZO.Applied on transparent conductive film
Apply one layer of photoresist；Photoresist is exposed using mask plate, developed, makes photoresist formation photoresist not reservation region and light
Photoresist reservation region, wherein, photoresist reservation region corresponds to the first transparency conducting layer 7 and pixel electrode region, photoetching
Reservation region does not correspond to other regions to glue；The electrically conducting transparent for etching away photoresist not reservation region completely by etching technics is thin
Film, peels off remaining photoresist, forms the first transparency conducting layer 7 and pixel electrode.
Wherein, the first transparency conducting layer 7 is electrical by the first via and Source and drain metal level 6 in the first oxidation-resisting structure 12
Connection.
And in viewing area, pixel electrode is brilliant by the second via through flatness layer and the second oxidation-resisting structure and film
The drain electrode of body pipe is in electrical contact.
Step S9, the formation passivation layer 8 on the underlay substrate 1 for completing step S8, and technique is patterned to passivation layer 8,
Passivation layer via hole 31 is formed, as shown in Figure 10；
In the viewing area of array base palte, the active layer of at least cover film transistor of passivation layer 8, for ensureing that film is brilliant
The electrology characteristic of body pipe.
Step S10, the formation on the underlay substrate 1 for completing step S9 by the patterning processes to same transparent conductive film
Positioned at the second transparency conducting layer 9 of non-display area, and the public electrode positioned at viewing area, as shown in Figure 3.
The LTPS array base paltes formed by above-mentioned steps are specifically included：
Underlay substrate 1, is transparency carrier, such as：Glass substrate, quartz base plate, organic resin substrate；
Form the cushion 2 on underlay substrate 1；
Form gate insulation layer 3 on the buffer layer 2；
Formed on gate insulation layer 3 and positioned at the barrier metal layer 4 of non-display area, formed on gate insulation layer 3 and be located at
The gate electrode and grid line of viewing area, barrier metal layer 4, the gate electrode and grid line pass through the composition work to same grid metal film
Skill is formed；
Form the interlayer insulating film 5 in barrier metal layer 4, the gate electrode and grid line；
Formed on interlayer insulating film 5 and positioned at the Source and drain metal level 6 of non-display area, formed on interlayer insulating film 5
And positioned at the source electrode, drain electrode and data line of viewing area, Source and drain metal level 6, the source electrode, drain electrode and data line are led to
Cross and the patterning processes of same drain metallic film are formed, Source and drain metal level 6 passes through the via and grid metal in interlayer insulating film 5
Layer 4 is in electrical contact；
The first oxidation-resisting structure 12 on the surface of Source and drain metal level 6 is covered in, second be covered on drain electrode surface resists
Oxidation structure；
Form the flatness layer in the source electrode, drain electrode and data line；
Formed on the first oxidation-resisting structure 12 and flatness layer and positioned at the first transparency conducting layer 7 of non-display area, shape
Into on the first oxidation-resisting structure 12 and flatness layer and positioned at the pixel electrode of viewing area, the first transparency conducting layer 7 and pixel
Electrode is formed by the patterning processes to same transparent conductive film, and the first transparency conducting layer 7 passes through the first oxidation-resisting structure 12
In the first via and Source and drain metal level 6 it is in electrical contact, pixel electrode pass through the second via in the second oxidation-resisting structure with leakage
Electrode is in electrical contact；
Form the passivation layer 8 on the first transparency conducting layer 7 and pixel electrode；
Formed on passivation layer 8 and positioned at the second transparency conducting layer 9 of non-display area, formed on passivation layer 8 and position
Public electrode in viewing area, the second transparency conducting layer 9 and public electrode pass through the composition work to same transparent conductive film
Skill is formed, and the second transparency conducting layer 9 is in electrical contact by the via in passivation layer 8 and the first transparency conducting layer 7.
The driving electric field of above-mentioned LTPS array base paltes is transverse electric field, and the signal wire of non-display area includes what is be electrically connected with
Barrier metal layer 4, Source and drain metal level 5, the first transparency conducting layer 7 and the second transparency conducting layer 9, with higher reliability.
For the array base palte that driving electric field is longitudinal electric field, its do not include being formed passivation layer on the pixel electrode and
Public electrode over the passivation layer is formed, the manufacture craft of passivation layer and public electrode is eliminated.
A kind of display device is also provided in the embodiment of the present invention, it includes thin-film transistor array base-plate as described above.
Wherein, the display device can be liquid crystal display device, or active organic LED display dress
Put.
For active organic LED display device, the manufacture craft of its thin film transistor (TFT) is same as described above, can be with
Pass through first oxidation-resisting structure on the Source and drain metal level surface of same technique formation covering non-display area, the source and drain metal
Layer can also be electrically connected with by the first via in first oxidation-resisting structure and the conductive layer being subsequently formed.And for having
The manufacture craft of machine light emitting diode refers to prior art, will not be described in detail herein.
In technical scheme, the metallic conduction layer surface of the non-display area of array base palte is covered with anti-oxidant knot
Structure, to prevent the metal conducting layer to be oxidized, so that when the metal conducting layer exposes in the environment, and if now being formed
The film pattern of viewing area is only positioned at, the oxidation-resisting structure can protect the metal conducting layer not oxidized, reduce
The transmission resistance of the metal conducting layer, the electrical contact for the conductive layer for improving the metal conducting layer and being subsequently formed is special
Property, meanwhile, also help non-display area and realize highdensity line arrangement, improve the quality of array base palte.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and replacement can also be made, these improve and replaced
Also it should be regarded as protection scope of the present invention.
Claims (19)
1. a kind of thin-film transistor array base-plate, including viewing area and the non-display area positioned at viewing area periphery, described
Thin-film transistor array base-plate includes the metal conducting layer positioned at the non-display area, it is characterised in that the film crystal
Pipe array base palte also includes：
The first oxidation-resisting structure of the metallic conduction layer surface is covered, to protect the metal conducting layer not oxidized；It is described
First oxidation-resisting structure is formed with the metal conducting layer by a patterning processes, and first oxidation-resisting structure is described thin
Orthographic projection on the underlay substrate of film transistor array base palte, positioned at positive throwing of the metal conducting layer on the underlay substrate
In shadow.
2. thin-film transistor array base-plate according to claim 1, it is characterised in that the thin-film transistor array base-plate
Also include：
It is only located at the film pattern of viewing area.
3. thin-film transistor array base-plate according to claim 2, it is characterised in that the thin-film transistor array base-plate
Also include：
Transparency conducting layer on first oxidation-resisting structure；
The first via is provided with first oxidation-resisting structure, the transparency conducting layer passes through first via and the gold
Belong to conductive layer in electrical contact.
4. thin-film transistor array base-plate according to claim 3, it is characterised in that the thin-film transistor array base-plate
For LTPS array base paltes, the thin-film transistor array base-plate includes the thin film transistor (TFT) and pixel electrode positioned at viewing area,
The film pattern for being only located at viewing area is flatness layer；
The metal conducting layer is Source and drain metal level.
5. thin-film transistor array base-plate according to claim 4, it is characterised in that the material of the Source and drain metal level is
Ti/Al/Ti alloys.
6. thin-film transistor array base-plate according to claim 4, it is characterised in that the source and drain gold of the non-display area
Belong to source electrode, the extremely identical material of leaking electricity of layer and thin film transistor (TFT)；
The transparency conducting layer of the non-display area is identical material with pixel electrode.
7. thin-film transistor array base-plate according to claim 4, it is characterised in that the thin-film transistor array base-plate
Also include：
The second oxidation-resisting structure of the drain electrode surface of the thin film transistor (TFT) is covered, to protect the drain electrode not oxidized；
Second oxidation-resisting structure and the first oxidation-resisting structure are identical material.
8. thin-film transistor array base-plate according to claim 7, it is characterised in that set in second oxidation-resisting structure
The second via is equipped with, the pixel electrode is in electrical contact by the drain electrode of second via and thin film transistor (TFT).
9. thin-film transistor array base-plate according to claim 7, it is characterised in that first oxidation-resisting structure and
The material of two oxidation-resisting structures is SiNx, SiOx or Si (ON) x.
10. a kind of display device, including the thin-film transistor array base-plate described in claim any one of 1-9.
11. a kind of preparation method of thin-film transistor array base-plate, the thin-film transistor array base-plate include viewing area and
Non-display area positioned at viewing area periphery, the preparation method includes：
Form the metal conducting layer positioned at the non-display area, it is characterised in that the making also includes：
The first oxidation-resisting structure of the covering metallic conduction layer surface is formed, to protect the metal conducting layer not oxidized；
First oxidation-resisting structure is formed with the metal conducting layer by a patterning processes；
Orthographic projection of first oxidation-resisting structure on the underlay substrate of the thin-film transistor array base-plate, positioned at the gold
Belong to conductive layer in the orthographic projection on the underlay substrate.
12. the preparation method according to being strongly required 11, it is characterised in that form the of the covering metallic conduction layer surface
After the step of one oxidation-resisting structure, the preparation method also includes：
Form the film pattern for being only located at viewing area.
13. the preparation method according to being strongly required 12, it is characterised in that the preparation method also includes：
Transparency conducting layer is formed on first oxidation-resisting structure；
The first via is formed in first oxidation-resisting structure；
The transparency conducting layer is in electrical contact by first via and the metal conducting layer.
14. preparation method according to claim 13, it is characterised in that the step of forming first oxidation-resisting structure is wrapped
Include：
Oxidation barrier film is formed on the metal conducting layer；
Photoresist is coated on the oxidation barrier film, photoresist is exposed using halftoning or gray tone mask plate, shape
Into photoresist, region and the reservation region of photoresist half, the reservation region of photoresist half is not fully retained in reservation region, photoresist
Region correspondence described the is fully retained in the region where the first via in correspondence first oxidation-resisting structure, the photoresist
One oxidation-resisting structure removes the region where the part of the first via, and reservation region does not correspond to other regions to the photoresist；
Etch away the oxidation barrier film of the photoresist not reservation region；
The photoresist of the reservation region of photoresist half is removed by cineration technics；
Etching oxidation barrier film certain thickness, positioned at the reservation region of photoresist half；
Remove remaining photoresist.
15. preparation method according to claim 14, it is characterised in that the step of forming first oxidation-resisting structure is also
Including：
After the step of being only located at the film pattern of viewing area is formed, etch away the correspondence reservation region of photoresist half and remain
Remaining oxidation barrier film, the first via formed in first oxidation-resisting structure and first oxidation-resisting structure.
16. preparation method according to claim 15, it is characterised in that the thin-film transistor array base-plate is LTPS gusts
Row substrate, the thin-film transistor array base-plate includes the thin film transistor (TFT) and pixel electrode positioned at viewing area, the only position
Film pattern in viewing area is flatness layer；
The metal conducting layer is Source and drain metal level.
17. preparation method according to claim 16, it is characterised in that forming the same of first oxidation-resisting structure
When, the second oxidation-resisting structure of the drain electrode surface of cover film transistor is formed, to protect the drain electrode not oxidized.
18. preparation method according to claim 17, it is characterised in that form first in first oxidation-resisting structure
While via, form the second via in second oxidation-resisting structure, the pixel electrode by second via with
The drain electrode of thin film transistor (TFT) is in electrical contact.
19. preparation method according to claim 16, it is characterised in that
The preparation method also includes：
Form drain metallic film, be patterned technique to the drain metallic film, formed thin film transistor (TFT) source electrode and
Drain electrode, and positioned at the Source and drain metal level of non-display area；
Transparent conductive film is formed, technique is patterned to the transparent conductive film, pixel electrode is formed, and positioned at non-aobvious
Show the transparency conducting layer in region, the transparency conducting layer is electrically connected with Source and drain metal level, the pixel electrode and source electricity
Pole is electrically connected with.
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| CN201410578332.8A CN104393001B (en) | 2014-10-24 | 2014-10-24 | Thin-film transistor array base-plate and preparation method thereof, display device |
| PCT/CN2015/072142 WO2016061940A1 (en) | 2014-10-24 | 2015-02-03 | Thin film transistor array substrate and manufacturing method therefor, and display device |
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| CN105762112A (en) | 2016-04-28 | 2016-07-13 | 京东方科技集团股份有限公司 | Thin film transistor array substrate and preparation method thereof and display device |
| CN106648210B (en) * | 2016-10-19 | 2023-11-28 | 合肥鑫晟光电科技有限公司 | Display panel, preparation method thereof and display device |
| CN107180837A (en) * | 2017-05-17 | 2017-09-19 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN107179644B (en) * | 2017-05-19 | 2021-11-09 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN107622974A (en) * | 2017-08-28 | 2018-01-23 | 武汉华星光电半导体显示技术有限公司 | The preparation method of TFT substrate and the preparation method of TFT display devices |
| CN107579040B (en) * | 2017-09-07 | 2020-04-21 | 京东方科技集团股份有限公司 | Mask, array substrate and manufacturing method thereof |
| CN107731882A (en) * | 2017-11-07 | 2018-02-23 | 深圳市华星光电半导体显示技术有限公司 | A kind of organic thin film transistor array substrate and preparation method thereof, display device |
| CN111384087A (en) * | 2018-12-28 | 2020-07-07 | 武汉华星光电半导体显示技术有限公司 | Organic light emitting diode display panel |
| CN110931525B (en) * | 2019-11-22 | 2023-01-10 | 京东方科技集团股份有限公司 | OLED array substrate, preparation method thereof and display device |
| CN113497090B (en) * | 2020-03-20 | 2023-09-22 | 合肥鑫晟光电科技有限公司 | Display substrate, manufacturing method thereof and display panel |
| CN114026631B (en) * | 2020-05-13 | 2023-12-22 | 京东方科技集团股份有限公司 | Driving substrate, manufacturing method thereof and display device |
| CN111564457B (en) * | 2020-05-28 | 2022-08-05 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN112687548B (en) * | 2020-12-25 | 2024-05-24 | 光华临港工程应用技术研发(上海)有限公司 | Preparation method and structure of transferable flexible interconnection structure |
| CN112885850B (en) * | 2021-01-29 | 2024-04-05 | 合肥京东方卓印科技有限公司 | Display panel and display device |
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