CN103413788A - Method for preparing non-planar metal nanocrystalline multi-bit memory device - Google Patents
Method for preparing non-planar metal nanocrystalline multi-bit memory device Download PDFInfo
- Publication number
- CN103413788A CN103413788A CN2013103834710A CN201310383471A CN103413788A CN 103413788 A CN103413788 A CN 103413788A CN 2013103834710 A CN2013103834710 A CN 2013103834710A CN 201310383471 A CN201310383471 A CN 201310383471A CN 103413788 A CN103413788 A CN 103413788A
- Authority
- CN
- China
- Prior art keywords
- memory device
- plane surface
- bit memory
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for preparing a non-planar metal nanocrystalline multi-bit memory device, and relates to a metal nanocrystalline memorizer. The method includes the steps: (1) a groove array is etched on a Si substrate through an electron beam lithography method to form a non-planar step-shaped structure, (2) after the etched Si substrate is cleaned in a standard mode, a dense SiO2 thin layer is formed on the non-planar Si substrate in a dry method oxidation method through oxidation to serve as an electron tunneling layer of the memory device, (3) an Au layer is formed on the non-planar Si substrate in a sputtering mode, the surface of the non-planar Si substrate obtained in the step (2) is covered with the SiO2 thin layer, and the Au layer is agglomerated by means of the fast thermal annealing method to form Au nano particles, (4) a high-k medium layer is formed on the Au nano particles obtained in the step (3) by means of the electron beam evaporation process in a deposition mode, and finally an upper electrode and a lower electrode are evaporated to obtain the non-planar metal nanocrystalline multi-bit memory device. Only one step of the etching technology is needed, the process is simple, and repeatability is good.
Description
Technical field
The present invention relates to a kind of metallic nano crystal memory, especially relate to a kind of preparation method of on-plane surface metallic nano crystal multi-bit memory device.
Background technology
Conductor memory is a microelectronic important branch, and it has stores and the function of processing information, be widely used in various microelectronic devices, as: the portable type electronic products such as notebook, mobile phone, flash memories, panel computer.Along with popularizing of Portable intelligent electronic product, grow with each passing day to the demand of mass data storage in market.In contemporary semiconductor memory field, non-volatility memorizer (NVM) is being played the part of more and more important role.So-called nonvolatile memory, refer in the situation that lose externally fed and still can keep the memory of its data of storing.From 1967 Bell Laboratory (Bell Lab) D.Kahng and S.M.Sze propose based on floating gate structure (FG, Floating Gate) since non-volatile semiconductor memory, the concept of floating gate structure just becomes development main line ([1] D.Kahng and S.M.Sze of more than 40 year afterwards semiconductor non-volatile memory, A floating gate and its application to memory devices, Bell Systems Technical Journal.46,1288,1967), and be widely used in the middle of in-line memory.The memory of this structure has very large advantage on cost, storage density, power consumption and thermal stability, and the continuous fast lifting of performance.
Along with nonvolatile memory enters the 20nm process node, traditional memory based on many product Si floating gate structure runs into a lot of restrictions on structural behaviour, nonvolatile memory for traditional floating gate structure, further dwindle its size and will bring serious challenge to memory technology, because the processing technology of device is no longer simple size scaled down, own warp is to a limit.But the floating-gate memory contractility is obstructed and is mainly reflected in following two aspects ([2] K.Kim, Technology for sub～50nm DRAM and NAND flash manufacturing, IEDM Tech.Dig.323～326,2005; [3] C.Y.Lu, K.Y.Hsieh and R.Liu, Future challenges of flash memory technologies, Microelectron.Eng.86,283～286,2009; [4] A.Sikora, F.P.Pesl, W.linger, et al..Technologies and reliability of modem embedded flash cells, Microelectron.Reliab.46,1980～2005,2006): first, the reduced thickness of tunnel oxide is own through reaching capacity, tunnel oxide can't continue attenuate according to the principle of scaled down, continue the leakage current that attenuate will increase device, when the thickness of tunnel oxide was less than 7nm, the floating boom of stored charge can't guarantee the call data storage of 10 years to the charge leakage of substrate; The second, along with size reduction, the paste syzygy number between floating boom and control gate constantly descends, and the distance in array between store electricity unit is more and more less, and crosstalking between the broken floating boom of adjacent many product is more and more serious.The logic error caused thus makes device size be difficult to be advanced to below 20nm.Next someone has proposed the concept of multilayered memory.
Charge trap-type memory technology of new generation (CTM:Charge Trapping Memory) ([5] F.Masuoka based on the trap storage principle of multi-layer nano structure, M.Assano, H.Iwahashi, A new Flash EEPROM cell using triple polysilieon technology, Technical Digest on the IEEE International Electron Deviees Meeting, 464, 1984), has the minute quantity electronic operation, device size is little, low in energy consumption, can realize multilevel storage, easily and the advantage such as CMOS process compatible, the CTM memory that particularly has the multilevel storage state can be at same area, the growth at double of similar technology lower acquisition storage density of generation, fundamentally solved the bottleneck that further size that current floating-gate memory faces is dwindled, the important directions that is considered to memory technology development of future generation.Yet, for the brilliant memory of multi-layer nano, due to the nanocrystal on upper strata from raceway groove away from, the direct tunnelling of electric charge is returned substrate difficulty relatively; Simultaneously, due to coulomb blockade effect and energy level quantization effect, between levels was nanocrystalline, the tunnelling of electric charge was suppressed, had caused operating voltage larger.
Summary of the invention
The object of the invention is to introduce the step-like channel layer structure of on-plane surface, Stepped control oxide layer grid voltage technology, realize the multidigit metallic nano crystal memory, and a kind of preparation method of on-plane surface metallic nano crystal multi-bit memory device is provided.
The present invention includes following steps:
1) by electronic beam photetching process, etch groove array on the Si substrate, form the step-like structure of on-plane surface;
2) by the Si substrate after etching after standard cleaning, adopt the dry oxidation method, the SiO of oxidation one deck densification on nonplanar Si substrate
2Thin layer is as the electron tunneling layer of memory;
3) by step 2) surface coverage that obtains has SiO
2Sputter Au layer on the on-plane surface Si substrate of thin layer, adopt quick thermal annealing method that the Au layer is reunited and form the Au nano particle;
4) adopt electron beam evaporation process deposition high K medium layer on the Au nano particle that step 3) obtains, last evaporation top electrode and bottom electrode, obtain on-plane surface metallic nano crystal multi-bit memory device.
In step 1), described electronic beam photetching process can adopt gas electron beam mask aligner to carry out electron beam lithography; Described Si substrate can be selected disc Si substrate, and the diameter of disc Si substrate can be 10cm, and thickness can be 500 μ m; Described groove array can adopt strip groove array or cross groove array etc.; The Cycle Length of described groove array can be 100～200nm, and the height of groove can be 50～70nm.
In step 2) in, described dry oxidation method can adopt the thermal annealing stove, is filled with oxygen as reacting gas, and oxidizing temperature is 900 ℃, annealing time 30s; Described SiO
2The thickness of thin layer can be 3～5nm.
In step 3), the thickness of described Au layer can be 15nm; The condition of described quick thermal annealing method can be: 600 ℃ of annealing temperatures, and annealing time 60s, protective gas are nitrogen; The size of described Au nano particle can be 20～30nm.
In step 4), described high K medium layer can adopt HfO
2Material, described top electrode can adopt the Al electrode, and bottom electrode can adopt the Al electrode.
The problem existed in order to solve prior art, the present invention proposes to introduce the step-like channel layer structure of on-plane surface, and Stepped control oxide layer grid voltage technology realizes the multidigit metallic nano crystal memory.The invention provides the Optimal Structure Designing of a kind of on-plane surface multidigit metallic nano crystal memory spare.Nonplanar metal nanoparticle is on different table tops, and the control oxide layer on upper strata presents step-like distribution, and groove is different from the equivalent oxide thickness at table top place, thus the difference that has caused internal electric field to distribute.For different operating voltages, electric charge can be stored in the diverse location of table top, increases memory window, forms the multidigit storage.
The present invention is to advance the step-like channel layer structure of on-plane surface, and Stepped control oxide layer grid voltage technology realizes the multidigit metallic nano crystal memory, and the present invention only needs a step lithographic technique, process simple, reproducible, can produce exemplary role to traditional related industry.
The accompanying drawing explanation
Fig. 1 is the step-like oxide layer metallic nano crystal multi-bit memory schematic diagram that has of the present invention.In Fig. 1, mark 1 is 300nm Al electrode, and 2 is step-like control oxide layer, and 3 is nanometer Au electron capture layer, and 4 is SiO
2Tunnel oxide, 5 is P type Si substrate; (a) without grid voltage V grid or be less than thin layer and catch voltage Vt1 initial condition; (b) when grid voltage V grid are greater than thin layer, catch voltage Vt1, catch voltage Vt2(Vt2 and be less than thick-layer the V grid Vt1), electric charge can tunnelling enter the metallic nano crystal that thin control oxide layer is wrapped up; Along with grid voltage increases, the first flat band voltage drift or window memory increase, until the thin-oxide district is saturated; (c) along with grid voltage increases to the V grid>Vt2>Vt1, the electric charge tunnelling enters by the metal nano crystal layer of thick control oxide layer parcel, until the second saturation region appearance, by control-grid voltage, realizes the multidigit storage of electric charge.
Fig. 2 is on-plane surface metallic nano crystal memory structural representation.In Fig. 2, mark 1 is 300nm Al positive electrode, and 2 is step-like control oxide layer, and 3 is nanometer Au electron capture layer, and 4 is SiO
2Tunnel oxide, 5 is P type Si substrate, 6 is 300nm Al electrode bottom electrode.
Embodiment
The present invention obtains the step-like channel layer structure of on-plane surface with electron beam lithography, adopts nonplanar metal nanoparticle as charge storage layer, realizes the multidigit metallic nano crystal memory with Stepped control oxide layer grid voltage technology.
1) electron beam lithography etches bar shaped or cross groove structure on the Si substrate, and the groove cycle is 100～200nm, and table surface height is 50～70nm.
2) the Si substrate is adopted to standard cleaning, obtain the Si surface of surface cleaning.
In step 2) in, described Si chip size is 4 inches, thickness is 500 μ m; Described cleaning process is as described below:
(1) at first with III liquid, clean (H
2SO
4: H
2O
2=4: 1), preparation III liquid, then be placed on the Si sheet in quartz boat in quartz curette, on electric furnace, boils 10min(and first use heating by electric cooker 3min, then closes electric furnace and heat 2min by remaining temperature, then close after opening heating by electric cooker 2min).The quartz curette that taking-up Si sheet is put into bath rushes hot deionized water 10 times, the cold deionized water of backlash 5 times.
(2) take out the Si sheet and put into HF: H
2O=1: soak 4min in 20 solution.Then take out the Si sheet and rush hot deionized water 15 times, the cold deionized water of backlash 15 times.
(3) then with I liquid, clean (NH
4OH: H
2O
2: H
2O=1: 1: 4), first pour deionized water into, water is heated to 85 ℃, after pour NH into
4OH and H
2O
2, after 1min, put into the Si sheet, on electric furnace, heat 5min, after close with remaining temperature heating 5min.The quartz curette that taking-up Si sheet is put into bath rushes hot deionized water 10 times, the cold deionized water of backlash 5 times.
(4) take out the Si sheet and put into HF: H
2O=1: soak 2min in 20 solution.Then take out the Si sheet and rush hot deionized water 15 times, the cold deionized water of backlash 15 times.
(5) with II liquid, clean (HCl: H
2O
2: H
2O=1: 1: 4), first pour deionized water into and be heated to 85 ℃, after pour HCl and H into
2O
2, after 1min, put into the Si sheet, after 2min, open heating by electric cooker 3min, after close electric furnace and heat 5min by remaining temperature.The quartz curette that taking-up Si sheet is put into bath rushes hot deionized water 15 times, the cold deionized water of backlash 15 times.
(6) nitrogen dries up standby.
3) adopt dry oxidation technology, the thick fine and close SiO of oxidation 3～5nm on nonplanar Si substrate
2Tunnel layer; Adopt domestic quick anneal oven, the oxygen of take is carrier gas, and annealing temperature is 900 ℃, and annealing time is 30s.
4) surface coverage step 3) obtained has SiO
2On the on-plane surface Si substrate of thin layer, the thick Au layer of sputter 15nm, then adopt domestic quick anneal oven, and the rapid thermal annealing mode of take forms Au nano particle Au nanoparticle size and is 20～30nm.Annealing temperature is 600 ℃, and annealing time is 60s.
5) in step 4), the high K medium layer is HfO
2Material, high K medium layer thickness are 60～80nm, and the thickness of described top electrode Al material is 300nm, and the thickness of bottom electrode Al material is 300nm, by magnetron sputtering technique sputter top electrode and bottom electrode.
Fig. 1 provides has step-like oxide layer metallic nano crystal multi-bit memory schematic diagram.By introducing nonplanar structure, realized the selectivity storage of electric charge.The control oxide layer on upper strata presents step-like distribution, and groove is different from the equivalent oxide thickness at table top place, thus the difference that has caused internal electric field to distribute.For different operating voltages, charge storage, in the metal nanoparticle at varying mesa place, forms the multidigit storage.Fig. 2 provides on-plane surface metallic nano crystal memory structural representation.By changing electron beam lithography technique, can obtain the on-plane surface metal nanoparticle memory of difformity, varying mesa height, only need a step etching, operating procedure is simple.
Through above-mentioned steps, finally obtained on-plane surface multidigit metallic nano crystal memory spare structure.The foregoing is only preferred embodiments of the present invention.
Claims (10)
1. the preparation method of on-plane surface metallic nano crystal multi-bit memory device is characterized in that comprising the following steps:
1) by electronic beam photetching process, etch groove array on the Si substrate, form the step-like structure of on-plane surface;
2) by the Si substrate after etching after standard cleaning, adopt the dry oxidation method, the SiO of oxidation one deck densification on nonplanar Si substrate
2Thin layer is as the electron tunneling layer of memory;
3) by step 2) surface coverage that obtains has SiO
2Sputter Au layer on the on-plane surface Si substrate of thin layer, adopt quick thermal annealing method that the Au layer is reunited and form the Au nano particle;
4) adopt electron beam evaporation process deposition high K medium layer on the Au nano particle that step 3) obtains, last evaporation top electrode and bottom electrode, obtain on-plane surface metallic nano crystal multi-bit memory device.
2. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 1), and described electronic beam photetching process adopts gas electron beam mask aligner to carry out electron beam lithography.
3. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 1), and described Si substrate is selected disc Si substrate, and the diameter of disc Si substrate can be 10cm, and thickness can be 500 μ m.
4. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 1), and described groove array adopts strip groove array or cross groove array; The Cycle Length of described groove array can be 100～200nm, and the height of groove can be 50～70nm.
5. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 2) in, described dry oxidation method adopts the thermal annealing stove, is filled with oxygen as reacting gas, and oxidizing temperature is 900 ℃, annealing time 30s.
6. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 2) in, described SiO
2The thickness of thin layer is 3～5nm.
7. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 3), and the thickness of described Au layer is 15nm.
8. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 3), and the condition of described quick thermal annealing method is: 600 ℃ of annealing temperatures, and annealing time 60s, protective gas are nitrogen; The size of described Au nano particle can be 20～30nm.
9. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 4), and described high K medium layer adopts HfO
2Material.
10. the preparation method of on-plane surface metallic nano crystal multi-bit memory device as claimed in claim 1, is characterized in that in step 4), and described top electrode adopts the Al electrode, and bottom electrode adopts the Al electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310383471.0A CN103413788B (en) | 2013-08-29 | 2013-08-29 | The preparation method of non-planar metal nanocrystalline multi-bit memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310383471.0A CN103413788B (en) | 2013-08-29 | 2013-08-29 | The preparation method of non-planar metal nanocrystalline multi-bit memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103413788A true CN103413788A (en) | 2013-11-27 |
| CN103413788B CN103413788B (en) | 2016-03-09 |
Family
ID=49606787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310383471.0A Expired - Fee Related CN103413788B (en) | 2013-08-29 | 2013-08-29 | The preparation method of non-planar metal nanocrystalline multi-bit memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103413788B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050059213A1 (en) * | 2003-09-16 | 2005-03-17 | Steimle Robert F. | Semiconductor device with nanoclusters |
| US20070057313A1 (en) * | 2005-07-18 | 2007-03-15 | Samsung Electronics Co., Ltd. | Multi-Bit Nonvolatile Memory Devices Including Nano-Crystals and Trench, and Methods for Fabricating the Same |
| CN101154575A (en) * | 2006-04-04 | 2008-04-02 | 三星电子株式会社 | Gate structure of integrated circuit memory device having charge storing nano crystals in metal oxide dielectric film and method of forming the same |
| CN101312213A (en) * | 2007-05-24 | 2008-11-26 | 中国科学院微电子研究所 | Nanocrystalline floating gate structure non-volatility memory cell and its manufacture method |
| US20090090952A1 (en) * | 2007-10-03 | 2009-04-09 | Applied Materials, Inc. | Plasma surface treatment for si and metal nanocrystal nucleation |
| CN102168268A (en) * | 2011-03-02 | 2011-08-31 | 复旦大学 | Preparation method of metal nanocrystal |
-
2013
- 2013-08-29 CN CN201310383471.0A patent/CN103413788B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050059213A1 (en) * | 2003-09-16 | 2005-03-17 | Steimle Robert F. | Semiconductor device with nanoclusters |
| US20070057313A1 (en) * | 2005-07-18 | 2007-03-15 | Samsung Electronics Co., Ltd. | Multi-Bit Nonvolatile Memory Devices Including Nano-Crystals and Trench, and Methods for Fabricating the Same |
| CN101154575A (en) * | 2006-04-04 | 2008-04-02 | 三星电子株式会社 | Gate structure of integrated circuit memory device having charge storing nano crystals in metal oxide dielectric film and method of forming the same |
| CN101312213A (en) * | 2007-05-24 | 2008-11-26 | 中国科学院微电子研究所 | Nanocrystalline floating gate structure non-volatility memory cell and its manufacture method |
| US20090090952A1 (en) * | 2007-10-03 | 2009-04-09 | Applied Materials, Inc. | Plasma surface treatment for si and metal nanocrystal nucleation |
| CN102168268A (en) * | 2011-03-02 | 2011-08-31 | 复旦大学 | Preparation method of metal nanocrystal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103413788B (en) | 2016-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Ostraat et al. | Synthesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory devices | |
| CN104192835B (en) | Preparation method of graphene flash memory | |
| CN101692463B (en) | Capacitor structure of mixed nano-crystal memory and preparation method thereof | |
| CN101807576A (en) | Nano-crystal floating gate nonvolatile memory and manufacturing method thereof | |
| CN101452963A (en) | Metallic nanocrystalline floating gate non-volatile memory and manufacturing method thereof | |
| CN110459611B (en) | Ferroelectric field effect transistor and preparation method thereof | |
| Chang et al. | A distributed charge storage with GeO 2 nanodots | |
| CN111627920A (en) | Ferroelectric memory cell | |
| CN101383379A (en) | Nanocrystalline floating gate memory of multi-medium composite tunnel layer and manufacturing method | |
| CN104882490B (en) | A kind of preparation method of the floating-gate memory based on metal hetero quntum point | |
| CN101388397A (en) | Low-voltage erasable nano-crystal storage capacitor construction and preparation thereof | |
| CN101312212A (en) | Non-volatile memory utilizing high K medium and nanocrystalline floating gate and its manufacture method | |
| CN101807548B (en) | Process for manufacturing nano-crystal split gate type flash memory | |
| CN101399289A (en) | Nanocrystalline floating gate non-vaporability memory with double layer tunneling medium structure and manufacturing method | |
| CN103413787B (en) | Method for preparing step-shaped oxide layer Au/SiO2/Si nanometer rod memory device | |
| CN101383378A (en) | Non-volatile memory of multi-layered nano-crystal floating gate structure | |
| CN101330008A (en) | Method for making metal nanocrystalline non-volatility memory | |
| CN103413788B (en) | The preparation method of non-planar metal nanocrystalline multi-bit memory device | |
| CN101872767A (en) | Silicon nitride trap layer olive-shaped energy band gap structure and manufacturing method thereof of SONOS (Silicon Oxide Nitride Oxide Semiconductor) component | |
| CN100483744C (en) | Non-volatile floating-gate memory based on two-layer nano silicon structure and its preparing method | |
| CN103824937B (en) | A kind of high speed nanometer two ends nonvolatile memory and preparation method thereof | |
| CN102543703B (en) | Manufacturing method of nanocrystalline flash memory grid | |
| CN103872059A (en) | P-type channel flash memory and manufacturing method thereof | |
| Yang et al. | Nickel silicide nanocrystals embedded in SiO2 and HfO2 for nonvolatile memory application | |
| Irrera | Engineered barriers with hafnium oxide for nonvolatile application |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160309 Termination date: 20210829 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |