CN103413788B - The preparation method of non-planar metal nanocrystalline multi-bit memory device - Google Patents
The preparation method of non-planar metal nanocrystalline multi-bit memory device Download PDFInfo
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- CN103413788B CN103413788B CN201310383471.0A CN201310383471A CN103413788B CN 103413788 B CN103413788 B CN 103413788B CN 201310383471 A CN201310383471 A CN 201310383471A CN 103413788 B CN103413788 B CN 103413788B
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Abstract
The preparation method of non-planar metal nanocrystalline multi-bit memory device, relates to a kind of metallic nano crystal memory.1) etch groove array on a si substrate by electronic beam photetching process, form the structure of non-planar steps shape; 2) by the Si substrate after etching after standard cleaning, adopt dry oxidation method, nonplanar Si substrate be oxidized the SiO of one deck densification
2thin layer is as the electron tunneling layer of memory; 3) by step 2) surface coverage that obtains has SiO
2the on-plane surface Si substrate of thin layer sputters Au layer, adopts quick thermal annealing method that Au layer is reunited and form Au nano particle; 4) the Au nano particle adopting electron beam evaporation process to obtain in step 3) deposits high-k dielectric layer, last evaporation top electrode and bottom electrode, acquisition non-planar metal nanocrystalline multi-bit memory device.Only need a step lithographic technique, process simple, reproducible.
Description
Technical field
The present invention relates to a kind of metallic nano crystal memory, especially relate to a kind of preparation method of non-planar metal nanocrystalline multi-bit memory device.
Background technology
Conductor memory is a microelectronic important branch, and it has carries out to information the function that stores Yu process, is widely used in various microelectronic device, as: the portable type electronic products such as notebook, mobile phone, flash memories, panel computer.Along with popularizing of Portable intelligent electronic product, the demand of market to mass data storage grows with each passing day.In modern semiconductor memory area, non-volatility memorizer (NVM) plays more and more important role.So-called nonvolatile memory, refer to still to keep when losing externally fed its store the memory of data.From 1967 Bell Laboratory (BellLab) D.Kahng and S.M.Sze propose based on floating gate structure (FG, FloatingGate) since non-volatile semiconductor memory, the concept of floating gate structure just becomes development main line ([1] D.KahngandS.M.Sze of more than 40 year afterwards semiconductor non-volatile memory, Afloatinggateanditsapplicationtomemorydevices, BellSystemsTechnicalJournal.46,1288,, and be widely used in the middle of in-line memory 1967).The memory of this structure has very large advantage in cost, storage density, power consumption and thermal stability, and the continuous fast lifting of performance.
Along with nonvolatile memory enters 20nm process node, traditional memory based on many product Si floating gate structure runs into a lot of restriction in structural behaviour, for the nonvolatile memory of traditional floating gate structure, reduce its size further and will bring serious challenge to memory technology, because the processing technology of device is no longer simple size scaled down, own warp is to a limit.Floating-gate memory contractility can be obstructed and be mainly reflected in following two aspects ([2] K.Kim, Technologyforsub ~ 50nmDRAMandNANDflashmanufacturing, IEDMTech.Dig.323 ~ 326,2005; [3] C.Y.Lu, K.Y.HsiehandR.Liu, Futurechallengesofflashmemorytechnologies, Microelectron.Eng.86,283 ~ 286,2009; [4] A.Sikora, F.P.Pesl, W.linger, etal..Technologiesandreliabilityofmodemembeddedflashcell s, Microelectron.Reliab.46,1980 ~ 2005,2006): first, the reduced thickness of tunnel oxide is own through reaching capacity, tunnel oxide cannot continue thinning according to the principle of scaled down, continue thinning by the leakage current of increased device, when the thickness of tunnel oxide is less than 7nm, the floating boom of stored charge cannot ensure the call data storage of 10 years to the charge leakage of substrate; The second, along with size reduces, the paste syzygy number between floating boom and control gate constantly declines, and the distance in array between store electricity unit is more and more less, and the crosstalk that adjacent many product break between floating boom is more and more serious.The logic error caused thus makes device size be difficult to be advanced to below 20nm.Next someone proposes the concept of multilayered memory.
Based on charge trap-type memory technology (CTM:ChargeTrappingMemory) ([5] F.Masuoka of new generation of the trap storage principle of multi-layer nano structure, M.Assano, H.Iwahashi, AnewFlashEEPROMcellusingtriplepolysilieontechnology, TechnicalDigestontheIEEEInternationalElectronDevieesMeet ing, 464, 1984), there is minute quantity electronic operation, device size is little, low in energy consumption, multilevel storage can be realized, the advantages such as easy and CMOS technology is compatible, the CTM memory particularly with multilevel storage state can at same area, similar technology is for the growth at double of lower acquisition storage density, fundamentally solve the bottleneck that further size that current floating-gate memory faces reduces, be considered to the important directions of memory technology of future generation development.But for the brilliant memory of multi-layer nano, because the nanocrystal on upper strata is away from raceway groove, the direct tunnelling of electric charge returns substrate relative difficulty; Meanwhile, due to coulomb blockade effect and energy level quantum optical field, between levels is nanocrystalline, the tunnelling of electric charge is suppressed, result in operating voltage larger.
Summary of the invention
The object of the invention is to introduce non-planar steps shape channel layer structure, Stepped control oxide layer grid voltage technology, realizes multidigit metallic nano crystal memory, provides a kind of preparation method of non-planar metal nanocrystalline multi-bit memory device.
The present invention includes following steps:
1) etch groove array on a si substrate by electronic beam photetching process, form the structure of non-planar steps shape;
2) by the Si substrate after etching after standard cleaning, adopt dry oxidation method, nonplanar Si substrate be oxidized the SiO of one deck densification
2thin layer is as the electron tunneling layer of memory;
3) by step 2) surface coverage that obtains has SiO
2the on-plane surface Si substrate of thin layer sputters Au layer, adopts quick thermal annealing method that Au layer is reunited and form Au nano particle;
4) the Au nano particle adopting electron beam evaporation process to obtain in step 3) deposits high-k dielectric layer, last evaporation top electrode and bottom electrode, acquisition non-planar metal nanocrystalline multi-bit memory device.
In step 1), described electronic beam photetching process can adopt gas electron beam mask aligner to carry out electron beam lithography; Described Si substrate can select disc Si substrate, and the diameter of disc Si substrate can be 10cm, and thickness can be 500 μm; Described groove array can adopt strip groove array or cross groove array etc.; The Cycle Length of described groove array can be 100 ~ 200nm, and the height of groove can be 50 ~ 70nm.
In step 2) in, described dry oxidation method can adopt thermal annealing stove, is filled with oxygen as reacting gas, and oxidizing temperature is 900 DEG C, annealing time 30s; Described SiO
2the thickness of thin layer can be 3 ~ 5nm.
In step 3), the thickness of described Au layer can be 15nm; The condition of described quick thermal annealing method can be: annealing temperature 600 DEG C, annealing time 60s, and protective gas is nitrogen; The size of described Au nano particle can be 20 ~ 30nm.
In step 4), described high-k dielectric layer can adopt HfO
2material, described top electrode can adopt Al electrode, and bottom electrode can adopt Al electrode.
In order to solve prior art Problems existing, the present invention proposes to introduce non-planar steps shape channel layer structure, and Stepped control oxide layer grid voltage technology realizes multidigit metallic nano crystal memory.The invention provides the Optimal Structure Designing of a kind of on-plane surface multidigit metallic nano crystal memory part.Nonplanar metal nanoparticle is on different table tops, and the controlled oxidization layer on upper strata presents step-like distribution, and groove is different from the equivalent oxide thickness at table top place, thus causes the difference of internal electric field distribution.For different operating voltages, electric charge can be stored in the diverse location of table top, increases memory window, forms multidigit and stores.
The present invention is to enter non-planar steps shape channel layer structure, and Stepped control oxide layer grid voltage technology realizes multidigit metallic nano crystal memory, and the present invention only needs a step lithographic technique, process simple, reproducible, can produce exemplary role to traditional related industry.
Accompanying drawing explanation
Fig. 1 of the present inventionly has step-like oxide layer metallic nano crystal multi-bit memory schematic diagram.In FIG, mark 1 is 300nmAl electrode, and 2 is step-like controlled oxidization layer, and 3 is nanometer Au electron capture layer, and 4 is SiO
2tunnel oxide, 5 is P type Si substrate; A () is without grid voltage V grid or be less than thin layer and catch voltage Vt1 initial condition; B () catches voltage Vt1 when grid voltage V grid are greater than thin layer, and be less than thick-layer and catch voltage Vt2(Vt2>V grid >Vt1), electric charge tunnelling can enter the metallic nano crystal of thin controlled oxidization layer parcel; Along with grid voltage increases, the first flatband voltage shift or window memory increase, until thin-oxide district is saturated; C () increases to V grid >Vt2>Vt1 along with grid voltage, electric charge tunnelling enters by the metal nano crystal layer of thick controlled oxidization layer parcel, until the second saturation region occurs, by control-grid voltage, the multidigit realizing electric charge stores.
Fig. 2 is non-planar metal nanocrystalline memory construction schematic diagram.In fig. 2, mark 1 is 300nmAl positive electrode, and 2 is step-like controlled oxidization layer, and 3 is nanometer Au electron capture layer, and 4 is SiO
2tunnel oxide, 5 is P type Si substrate, and 6 is 300nmAl electrode bottom electrode.
Embodiment
The present invention obtains non-planar steps shape channel layer structure with electron beam lithography, adopts nonplanar metal nanoparticle as charge storage layer, realizes multidigit metallic nano crystal memory with Stepped control oxide layer grid voltage technology.
1) electron beam lithography etches bar shaped or cross groove structure on a si substrate, and groove period is 100 ~ 200nm, and table surface height is 50 ~ 70nm.
2) standard cleaning is adopted to Si substrate, obtain the Si surface of surface cleaning.
In step 2) in, described Si chip size is 4 inches, and thickness is 500 μm; Described cleaning process is as described below:
(1) first with No. III liquid cleaning (H
2sO
4: H
2o
2=4: 1), in quartz curette, prepare No. III liquid, then Si sheet is placed in quartz boat, electric furnace boils 10min(and first uses heating by electric cooker 3min, then close the remaining temperature heating 2min of electric furnace, then close after opening heating by electric cooker 2min).The quartz curette that taking-up Si sheet puts into bath rushes hot deionized water 10 times, the cold deionized water of backlash 5 times.
(2) take out Si sheet and put into HF: H
24min is soaked in the solution of O=1: 20.Then take out Si sheet and rush hot deionized water 15 times, the cold deionized water of backlash 15 times.
(3) then with No. I liquid cleaning (NH
4oH: H
2o
2: H
2o=1: 1: 4), first pour deionized water into, water is heated to 85 DEG C, after pour NH into
4oH and H
2o
2, put into Si sheet after 1min, electric furnace heat 5min, the remaining temperature heating 5min of rear closedown.The quartz curette that taking-up Si sheet puts into bath rushes hot deionized water 10 times, the cold deionized water of backlash 5 times.
(4) take out Si sheet and put into HF: H
22min is soaked in the solution of O=1: 20.Then take out Si sheet and rush hot deionized water 15 times, the cold deionized water of backlash 15 times.
(5) with No. II liquid cleaning (HCl: H
2o
2: H
2o=1: 1: 4), first pour deionized water into and be heated to 85 DEG C, after pour HCl and H into
2o
2, put into Si sheet after 1min, after 2min, open heating by electric cooker 3min, the remaining temperature heating 5min of rear closedown electric furnace.The quartz curette that taking-up Si sheet puts into bath rushes hot deionized water 15 times, the cold deionized water of backlash 15 times.
(6) nitrogen dries up for subsequent use.
3) adopt dry oxidation technology, nonplanar Si substrate is oxidized the thick fine and close SiO of 3 ~ 5nm
2tunnel layer; Adopting domestic quick anneal oven, take oxygen as carrier gas, and annealing temperature is 900 DEG C, and annealing time is 30s.
4) surface coverage that step 3) obtains there is SiO
2the on-plane surface Si substrate of thin layer sputters the thick Au layer of 15nm, then adopt domestic quick anneal oven, form Au nano particle Au nanoparticle size for 20 ~ 30nm in rapid thermal annealing mode.Annealing temperature is 600 DEG C, and annealing time is 60s.
5) in step 4), high-k dielectric layer is HfO
2material, high-k dielectric layer thickness is 60 ~ 80nm, and the thickness of described top electrode Al material is 300nm, and the thickness of bottom electrode Al material is 300nm, by magnetron sputtering technique sputtering top electrode and bottom electrode.
Fig. 1 provides has step-like oxide layer metallic nano crystal multi-bit memory schematic diagram.By introducing nonplanar structure, the selectivity achieving electric charge stores.The controlled oxidization layer on upper strata presents step-like distribution, and groove is different from the equivalent oxide thickness at table top place, thus causes the difference of internal electric field distribution.For different operating voltages, charge storage, in the metal nanoparticle at varying mesa place, forms multidigit and stores.Fig. 2 provides non-planar metal nanocrystalline memory construction schematic diagram.By changing electron beam lithography technique, can obtain the non-planar metal nano particle memory of difformity, varying mesa height, only need a step etching, operating procedure is simple.
Through above-mentioned steps, finally obtain on-plane surface multidigit metallic nano crystal memory part structure.The foregoing is only preferred embodiments of the present invention.
Claims (5)
1. the preparation method of non-planar metal nanocrystalline multi-bit memory device, is characterized in that comprising the following steps:
1) etch groove array on a si substrate by electronic beam photetching process, form the structure of non-planar steps shape; Described groove array adopts strip groove array or cross groove array; The Cycle Length of described groove array is 100 ~ 200nm, and the height of groove is 50 ~ 70nm; Described Si substrate selects disc Si substrate, and the diameter of disc Si substrate is 10cm, and thickness is 500 μm;
2) by the Si substrate after etching after standard cleaning, adopt dry oxidation method, nonplanar Si substrate be oxidized the SiO of one deck densification
2thin layer is as the electron tunneling layer of memory; Described SiO
2the thickness of thin layer is 3 ~ 5nm;
3) by step 2) surface coverage that obtains has SiO
2the on-plane surface Si substrate of thin layer sputters Au layer, adopts quick thermal annealing method that Au layer is reunited and form Au nano particle; The thickness of described Au layer is 15nm; The condition of described quick thermal annealing method is: annealing temperature 600 DEG C, annealing time 60s, and protective gas is nitrogen; Described Au nano particle is of a size of 20 ~ 30nm;
4) electron beam evaporation process is adopted in step 3) the Au nano particle that obtains deposits high-k dielectric layer, last evaporation top electrode and bottom electrode, obtain non-planar metal nanocrystalline multi-bit memory device.
2. the preparation method of non-planar metal nanocrystalline multi-bit memory device as claimed in claim 1, is characterized in that in step 1) in, described electronic beam photetching process adopts gas electron beam mask aligner to carry out electron beam lithography.
3. the preparation method of non-planar metal nanocrystalline multi-bit memory device as claimed in claim 1, it is characterized in that in step 2) in, described dry oxidation method adopts thermal annealing stove, is filled with oxygen as reacting gas, oxidizing temperature is 900 DEG C, annealing time 30s.
4. the preparation method of non-planar metal nanocrystalline multi-bit memory device as claimed in claim 1, is characterized in that in step 4) in, described high-k dielectric layer adopts HfO
2material.
5. the preparation method of non-planar metal nanocrystalline multi-bit memory device as claimed in claim 1, is characterized in that in step 4) in, described top electrode adopts Al electrode, and bottom electrode adopts Al electrode.
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