CN103412606A - Band gap reference voltage source - Google Patents
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- CN103412606A CN103412606A CN2013103015095A CN201310301509A CN103412606A CN 103412606 A CN103412606 A CN 103412606A CN 2013103015095 A CN2013103015095 A CN 2013103015095A CN 201310301509 A CN201310301509 A CN 201310301509A CN 103412606 A CN103412606 A CN 103412606A
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Abstract
The invention relates to the technique of simulation integrated circuits, in particular to a band gap reference voltage source. The band gap reference voltage source comprises a biasing circuit, a band gap reference core circuit, a temperature detecting circuit, a switch capacitive circuit and an operational amplifier, wherein the biasing circuit supplies currents to the band gap reference core circuit, the output end of the band gap reference core circuit is connected with the input end of the switch capacitive circuit, the temperature detecting circuit is connected to a branch circuit of the band gap reference core circuit, the synclastic input end and the reverse input end of the operational amplifier are connected with the switch capacitive circuit, and the output end of the operational amplifier is connected with one output end of the switch capacitive circuit and serves as the output end of the reference voltage source. The band gap reference voltage source has the advantages that accuracy of output voltage of the first-order compensation band gap reference voltage source is improved, large resistors are not used, the circuit structure is simple, the layout area is saved, and cost is lowered. The band gap reference voltage source is particularly suitable for reference voltage sources.
Description
Technical field
The present invention relates to the Analogous Integrated Electronic Circuits technology, relate to specifically a kind of bandgap voltage reference.
Background technology
Along with integrated circuit fabrication process develops towards deep-submicron, integrated circuit (IC) design and manufacture day by day are tending towards high precision, high density and low cost.In nearly all Analogous Integrated Electronic Circuits, reference voltage source or the reference current source circuit circuit module that all is absolutely necessary, such as circuit such as A/D, D/A change-over circuit, voltage-regulating circuit, flash memories.The reference voltage source of high precision, high PSRR, low-temperature coefficient is even more important for the performance that improves whole chip.
Traditional band gap reference voltage source circuit as shown in Figure 1, the band gap voltage reference source circuit comprises: PMOS manages M1, M2, M3, bipolar transistor PQ1, PQ2 and PQ3, resistance R 1, R2, operational amplifier OP, wherein, PMOS manages M1, M2, the source electrode of M3 all meets external power source VDD, the grid of PMOS pipe M1 and M2 is connected, the drain electrode of M1 pipe is connected with the emitter of bipolar transistor Q1, node definition is the A point, the end of the drain electrode connecting resistance R1 of PMOS pipe M2, node definition is the B point, the grid of PMOS pipe M3 connects the grid of M2, drain electrode connecting resistance R2 mono-end, the emitter of another termination bipolar transistor Q2 of resistance R 1, the emitter of another termination bipolar transistor Q3 of resistance R 2, bipolar transistor Q1, Q2, the collector of Q3 and base stage be ground connection GND all, the drain electrode of PMOS pipe M3 meets output VREF, the anode input of operational amplifier connects the B point, the negative terminal input connects the A point.
In upper band gap reference voltage source circuit, operational amplifier OP is operated in the deep negative feedback states, plays the effect of clamper, make the current potential of 2 of A, B equate, thereby the reference voltage source Output Voltage Formula is: V
ref=V
BE3+ (R
2/ R
1) V
TLnN, in formula, N is the ratio of the emitter area of gated transistors PQ1, PQ2, V
BE3Be the base-emitter voltage of bipolar transistor PQ3, have negative temperature coefficient, V
TIt is thermal voltage, have positive temperature coefficient (PTC), visible by above-mentioned formula, the band gap reference voltage source circuit here is to utilize two voltage additions that temperature coefficient is opposite, suitably select R1, R2 and the N value in above-mentioned formula, just can at certain temperature, obtain the reference voltage of zero-temperature coefficient.Traditional bandgap voltage reference compensation principle as shown in Figure 2, in whole temperature range, only has a zero temperature coefficient point that is positioned at the T0 place.
Traditional band gap reference voltage source circuit is due to impacts such as element layout do not mate, and the output valve of side circuit and design load certainly exist certain deviation, and this will affect the output accuracy of reference voltage.Due to V in traditional bandgap voltage reference
Tto temperature, be directly proportional, it is certain that its positive temperature coefficient (PTC) keeps, and V
BEthe complicated function of temperature, so in very wide temperature range, particularly during hot stage, can not full remuneration V
BE, like this, in order to improve the precision of reference voltage source output, must carry out high-order (normally second order) temperature compensation, namely introduce the new higher order term relevant with temperature, with original reference voltage stack, thereby temperature higher order term in the base-emitter voltage of bipolar transistor is offset, but increased the complexity of circuit, and resistance R1 on the sheet that in the traditional benchmark voltage source circuit, existence is very large, R2, this very large chip area that will inevitably account for, increased to a certain extent the cost of chip, introduced again simultaneously noise, the degree of accuracy of output voltage can be greatly affected, be difficult to meet the demand of benchmark supply circuit for the bandgap voltage reference precision.
Summary of the invention
Technical matters to be solved by this invention, be exactly the problem for above-mentioned traditional bandgap voltage reference, proposes a kind of bandgap voltage reference.
The present invention solves the problems of the technologies described above the technical scheme adopted: a kind of bandgap voltage reference, it is characterized in that, comprise biasing circuit, the band-gap reference core circuit, temperature sensing circuit, switched-capacitor circuit and operational amplifier, the electric current that described biasing circuit produces by the current mirror mirror image to the band-gap reference core circuit, the output terminal of described band-gap reference core circuit is connected with the input end of switched-capacitor circuit, described temperature sensing circuit is connected on a branch road of band-gap reference core circuit, the input end in the same way of described operational amplifier is connected with an output terminal of switched-capacitor circuit, reverse input end is connected with another output terminal of switched-capacitor circuit, output terminal is connected with an output terminal of switched-capacitor circuit and as the output terminal of bandgap voltage reference.
Concrete, described biasing circuit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS pipe N4, the 5th NMOS pipe N5 and the 6th NMOS pipe N6
Described band-gap reference core circuit comprises the 5th PMOS pipe P5, the 6th PMOS pipe P6, the first positive-negative-positive bipolar transistor Q1 and the second positive-negative-positive double-click transistor Q2,
Described temperature sensing circuit comprises the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 12 PMOS pipe P12, the 7th NMOS pipe N7, the 8th NMOS pipe N8, the 9th NMOS pipe N9, the tenth NMOS pipe N10, the first npn type bipolar transistor Q3 and the second npn type bipolar transistor Q4
Described switched-capacitor circuit comprises the 11 NMOS pipe N11, the 12 NMOS pipe N12, the 13 NMOS pipe N13, the 14 NMOS pipe N14, the 15 NMOS pipe N15, the 16 NMOS pipe N16, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, the first logic control signal SW1, the second logic control signal SW2 and the 3rd logic control signal SW3
Described operational amplifier comprises the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19, the 20 NMOS pipe N20, the 4th capacitor C 4 and the 5th capacitor C 5; Wherein,
The grid of the one PMOS pipe P1, the grid of the 2nd PMOS pipe P2, the grid of the 3rd PMOS pipe P3, the grid of the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the grid of the 6th PMOS pipe P6, the grid of the 7th PMOS pipe P7, the grid of the 8th PMOS pipe P8, the grid of the tenth PMOS pipe P10, the grid of the 11 PMOS pipe P11, the grid of the grid of the 13 PMOS pipe P13 and the 16 PMOS pipe P16 is connected and is connected with the drain electrode of the 3rd NMOS pipe N3 with the drain electrode of the 2nd PMOS pipe P2, the grid of the one NMOS pipe N1 is connected with the grid of the 2nd NMOS pipe N2 with the drain electrode of a PMOS pipe P1, the source electrode of a NMOS pipe N1, the drain electrode of the 2nd NMOS pipe N2 is connected with the source electrode of the 3rd NMOS pipe N3, the grid of the 3rd NMOS pipe N3, the grid of the 4th NMOS pipe N4 is connected with the drain electrode of the 3rd PMOS pipe P3, the source electrode of the 4th NMOS pipe N4, the source electrode of the 5th NMOS pipe N5 is connected with the drain electrode of the 6th NMOS pipe N6, and the grid of the grid of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected with the drain electrode of the 4th PMOS pipe P4,
The source electrode of the drain electrode of the drain electrode of the drain electrode of the 5th PMOS pipe P5, the 9th PMOS pipe P9, the 12 PMOS pipe P12, the 9th NMOS pipe N9 is connected with the emitter of the first positive-negative-positive bipolar transistor Q1, the base stage of the first positive-negative-positive bipolar transistor Q1 is connected with the base stage that the second positive-negative-positive is double-clicked transistor Q2, the drain electrode of the drain electrode of the drain electrode of the 6th PMOS pipe P6, the tenth NMOS pipe N10, the 12 NMOS pipe N12 is connected with the emitter that the second positive-negative-positive is double-clicked transistor Q2
The drain electrode of the 7th PMOS pipe P7, the base stage of the first npn type bipolar transistor Q3 is connected with the drain electrode of the 7th NMOS pipe N7, the grid of the 7th NMOS pipe N7 is connected bias voltage Vbias with the grid of the 8th NMOS pipe N8, the drain electrode of the 8th PMOS pipe P8 connects the source electrode of the 9th PMOS pipe P9, the grid of the 9th PMOS pipe P9 connects the collector of the first npn type bipolar transistor Q3, the drain electrode of the tenth PMOS pipe P10 connects the base stage of the second npn type bipolar transistor Q4 and the drain electrode of the 8th NMOS pipe N8, the collector of the second npn type bipolar transistor Q4 connects the grid of the 12 PMOS pipe P12, the source electrode of the 12 PMOS pipe P12 connects the drain electrode of the 11 PMOS pipe P11, the drain electrode of the 9th NMOS pipe N9 connects the drain electrode of an end and the 13 NMOS pipe N13 of the first capacitor C 1, the source electrode of the tenth NMOS pipe N10 connects the other end of the first capacitor C 1 and the source electrode of the 11 NMOS pipe N11,
The source electrode of the 12 NMOS pipe N12 connects the drain electrode of an end and the 15 NMOS pipe N15 of the second capacitor C 2, the drain electrode of the 11 NMOS pipe N11 connects the source electrode of the 14 NMOS pipe N14, an end of the 3rd capacitor C 3 and the grid of the 14 PMOS pipe P14, the drain electrode of the 14 NMOS pipe N14 and the other end of the 3rd capacitor C 3 are connected drain electrode and the drain electrode of the 17 NMOS pipe N17, an end of capacitor C 4 and the drain electrode of the 20 NMOS pipe N20 of the 16 PMOS pipe P16
The source electrode of the 14 PMOS pipe P14 is connected the drain electrode of the 13 PMOS pipe P13 with the source electrode of the 15 PMOS pipe P15, the source electrode of the 15 NMOS pipe N15 connects the drain electrode of the 16 NMOS pipe N16 and the grid of the 15 PMOS pipe P15, the drain electrode of the 14 PMOS pipe P14 connects the grid of the 18 NMOS pipe N18 and the grid of the 19 NMOS pipe N19, the drain electrode of the 15 PMOS pipe P15 connects the other end of the 4th capacitor C 4, the drain electrode of the 19 NMOS pipe N19 and the grid of the 20 NMOS pipe N20
The first logic control signal SW1 connects the grid of the 9th NMOS pipe N9, the grid of the tenth NMOS pipe N10, the grid of the 12 NMOS pipe N12, the grid of the 14 NMOS pipe N14 and the grid of the 16 NMOS pipe N16, the second logic control signal SW2 connects the grid of the 11 NMOS pipe N11, the grid of the 13 NMOS pipe N13 and the grid of the 15 NMOS pipe N15, the 3rd logic control signal SW3 connects the grid of the 17 NMOS pipe N17, the source electrode of the 17 NMOS pipe N17 is connected with an end of the 5th capacitor C 5 the output terminal VREF that makes voltage-reference
The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7, the 8th PMOS pipe P8, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 13 PMOS pipe P13 and the 16 PMOS pipe P16 all meets power vd D
The source electrode of the 2nd NMOS pipe N2, the source electrode of the 6th NMOS pipe N6, the source electrode of the 7th NMOS pipe N7, the source electrode of the 8th NMOS pipe N8, the source electrode of the 13 NMOS pipe N12, the source electrode of the 16 NMOS pipe N16, the source electrode of the 18 NMOS pipe N18, the source electrode of the 19 NMOS pipe N19, the source electrode of the 20 NMOS pipe N20, the collector of the first positive-negative-positive bipolar transistor Q1, the collector of the second positive-negative-positive bipolar transistor Q2, the emitter of the first npn type bipolar transistor Q3, the equal ground connection GND of the other end of the emitter of the second npn type bipolar transistor Q4 and the 5th capacitor C 5.
Beneficial effect of the present invention is, be compared to traditional bandgap voltage reference, adopt switched capacitor technique, avoided the use of large resistance on the sheet, simultaneously, temperature sensing circuit can be opened different branch roads under different temperatures, pour into electric current for a branch road of band-gap reference core circuit, thereby reach the purpose of the temperature coefficient that changes PTAT voltage, in whole temperature range, three zero temperature coefficient points have been introduced, be compared to common first compensation phase circuit, the present invention has improved the precision of the bandgap voltage reference output voltage of first compensation phase, do not use large resistance, do not use high-order temperature compensation circuit, circuit structure is simple, saved chip area, reduced cost.
The accompanying drawing explanation
Fig. 1 is traditional band gap reference voltage source circuit structural representation;
Fig. 2 is traditional first compensation phase bandgap voltage reference principle schematic;
Fig. 3 is the circuit theory schematic diagram of voltage-reference of the present invention;
Fig. 4 is the electrical block diagram of voltage-reference of the present invention;
Fig. 5 is the not overlapping control signal logical schematic of voltage-reference of the present invention;
Fig. 6 is voltage-reference compensation principle schematic diagram provided by the invention.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
The present invention proposes a kind of bandgap voltage reference of novel employing switched capacitor technique, comprise biasing circuit, the band-gap reference core circuit, temperature sensing circuit, switched-capacitor circuit and operational amplifier, the electric current that described biasing circuit produces by the current mirror mirror image to the band-gap reference core circuit, the output terminal of described band-gap reference core circuit is connected with the input end of switched-capacitor circuit, described temperature sensing circuit is connected on a branch road of band-gap reference core circuit, the input end in the same way of described operational amplifier is connected with an output terminal of switched-capacitor circuit, reverse input end is connected with another output terminal of switched-capacitor circuit, output terminal is connected with an output terminal of switched-capacitor circuit and as the output terminal of voltage-reference.
Principle schematic as shown in Figure 3, includes: the biasing circuit part, and bias current is provided for the band-gap reference core circuit, the band-gap reference core circuit includes the first current sources la, the second current source Ib, the first positive-negative-positive bipolar transistor Q1, the second positive-negative-positive bipolar transistor Q2, temperature sensing circuit, include the first K switch 1, second switch K2, the 3rd current source Ic, the 4th current source Id, switched-capacitor circuit, comprise the 3rd K switch 3, the 4th K switch 4, the 5th K switch 5, the 6th K switch 6, minion is closed K7, the 8th switch K8, the 9th K switch 9, the 11 K switch 11, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, operation amplifier circuit comprises amplifier opamp, the tenth K switch 10, the 5th capacitor C 5, concrete annexation: the first current sources la, the second current source Ib, the 3rd current source Ic, the 4th current source Id mono-termination external power source VDD, the emitter of another termination of the first current sources la the first positive-negative-positive bipolar transistor Q1, the first positive-negative-positive bipolar transistor Q1 is the diode connected mode, the first positive-negative-positive bipolar transistor Q1 base stage and the equal ground connection GND of collector, the emitter of another termination of the second current source Ib the second positive-negative-positive bipolar transistor Q2, the second positive-negative-positive bipolar transistor Q2 is the diode connected mode, the second positive-negative-positive bipolar transistor Q2 base stage and the equal ground connection GND of collector, another termination first K switch 1 one ends of the 3rd current source Ic, first K switch 1 another termination second positive-negative-positive bipolar transistor Q2 emitter, another termination second switch of the 4th current source Id K2 mono-end, the second switch K2 other end also connects the second positive-negative-positive bipolar transistor Q2 emitter simultaneously, the 3rd K switch 3 one termination the first positive-negative-positive bipolar transistor Q1 emitters, another termination first capacitor C 1 one ends, the 4th K switch 4 one termination the second positive-negative-positive bipolar transistor Q2 emitters, another termination first capacitor C 1 other end, the 5th K switch 5 one termination the first positive-negative-positive bipolar transistor Q1 emitters, another termination second capacitor C 2 one ends, the 6th K switch 6 one termination the first capacitor C 1 one ends, other end ground connection GND, minion is closed K7 mono-termination capacitor the second capacitor C 2 one ends, the input end in the same way of another termination operational amplifier opamp, the 8th switch K8 mono-termination the first capacitor C 1 one ends, the reverse input end of another termination operational amplifier opamp, the input end in the same way of the 11 K switch 11 1 termination operational amplifier opamp, other end ground connection GND, the reverse input end of the 9th K switch 9 one termination operational amplifier opamp, the output terminal of another termination operational amplifier opamp, the reverse input end of the 3rd capacitor C 3 one termination operational amplifier opamp, the output terminal of another termination operational amplifier of C3 opamp, the output terminal of the tenth K switch 10 1 termination operational amplifier opamp, another termination benchmark output terminal VREF, the 5th capacitor C 5 one termination benchmark output terminal VREF, other end ground connection GND.
Below by embodiment, describe principle of work of the present invention in detail:
Embodiment:
This example is a kind of embodiment according to above-mentioned principle of the present invention, and on the basis of Fig. 3, all switches adopt NMOSFET to realize, as shown in Figure 4, described biasing circuit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the one NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS pipe N4, the 5th NMOS pipe N5 and the 6th NMOS pipe N6, described band-gap reference core circuit comprise the 5th PMOS pipe P5, the 6th PMOS pipe P6, the first positive-negative-positive bipolar transistor Q1 and the second positive-negative-positive are double-clicked transistor Q2, and described temperature sensing circuit comprises the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 12 PMOS pipe P12, the 7th NMOS pipe N7, the 8th NMOS pipe N8, the 9th NMOS pipe N9, the tenth NMOS pipe N10, the first npn type bipolar transistor Q3 and the second npn type bipolar transistor Q4, described switched-capacitor circuit comprise the 11 NMOS pipe N11, the 12 NMOS pipe N12, the 13 NMOS pipe N13, the 14 NMOS pipe N14, the 15 NMOS pipe N15, the 16 NMOS pipe N16, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, the first logic control signal SW1, the second logic control signal SW2 and the 3rd logic control signal SW3, described operational amplifier comprise the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19, the 20 NMOS pipe N20, the 4th capacitor C 4 and the 5th capacitor C 5,
The grid of a described PMOS pipe P1, the grid of the 2nd PMOS pipe P2, the grid of the 3rd PMOS pipe P3, the grid of the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the grid of the 6th PMOS pipe P6, the grid of the 7th PMOS pipe P7, the grid of the 8th PMOS pipe P8, the grid of the tenth PMOS pipe P10, the grid of the 11 PMOS pipe P11, the grid of the grid of the 13 PMOS pipe P13 and the 16 PMOS pipe P16 is connected and is connected with the drain electrode of the 3rd NMOS pipe N3 with the drain electrode of the 2nd PMOS pipe P2, the grid of the one NMOS pipe N1 is connected with the grid of the 2nd NMOS pipe N2 with the drain electrode of a PMOS pipe P1, the source electrode of the one NMOS pipe N1, the drain electrode of the 2nd NMOS pipe N2 is connected with the source electrode of the 3rd NMOS pipe N3, the grid of the 3rd NMOS pipe N3, the grid of the 4th NMOS pipe N4 is connected with the drain electrode of the 3rd PMOS pipe P3, the source electrode of the 4th NMOS pipe N4, the source electrode of the 5th NMOS pipe N5 is connected with the drain electrode of the 6th NMOS pipe N6, the grid of the grid of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected with the drain electrode of the 4th PMOS pipe P4, the drain electrode of the 5th PMOS pipe P5, the drain electrode of the 9th PMOS pipe P9, the drain electrode of the 12 PMOS pipe P12, the source electrode of the 9th NMOS pipe N9 is connected with the emitter of the first positive-negative-positive bipolar transistor Q1, the base stage of the first positive-negative-positive bipolar transistor Q1 is connected with the base stage that the second positive-negative-positive is double-clicked transistor Q2, the drain electrode of the 6th PMOS pipe P6, the drain electrode of the tenth NMOS pipe N10, the drain electrode of the 12 NMOS pipe N12 is connected with the emitter that the second positive-negative-positive is double-clicked transistor Q2, the drain electrode of the 7th PMOS pipe P7, the base stage of the first npn type bipolar transistor Q3 is connected with the drain electrode of the 7th NMOS pipe N7, the grid of the 7th NMOS pipe N7 is connected bias voltage Vbias with the grid of the 8th NMOS pipe N8, the drain electrode of the 8th PMOS pipe P8 connects the source electrode of the 9th PMOS pipe P9, the grid of the 9th PMOS pipe P9 connects the collector of the first npn type bipolar transistor Q3, the drain electrode of the tenth PMOS pipe P10 connects the base stage of the second npn type bipolar transistor Q4 and the drain electrode of the 8th NMOS pipe N8, the collector of the second npn type bipolar transistor Q4 connects the grid of the 12 PMOS pipe P12, the source electrode of the 12 PMOS pipe P12 connects the drain electrode of the 11 PMOS pipe P11, the drain electrode of the 9th NMOS pipe N9 connects the drain electrode of an end and the 13 NMOS pipe N13 of the first capacitor C 1, the source electrode of the tenth NMOS pipe N10 connects the other end of the first capacitor C 1 and the source electrode of the 11 NMOS pipe N11, the source electrode of the 12 NMOS pipe N12 connects the drain electrode of an end and the 15 NMOS pipe N15 of the second capacitor C 2, the drain electrode of the 11 NMOS pipe N11 connects the source electrode of the 14 NMOS pipe N14, the grid of one end of the 3rd capacitor C 3 and the 14 PMOS pipe P14, the drain electrode of the 14 NMOS pipe N14 and the other end of the 3rd capacitor C 3 are connected the drain electrode of the 16 PMOS pipe P16 and the drain electrode of the 17 NMOS pipe N17, the drain electrode of one end of capacitor C 4 and the 20 NMOS pipe N20, the source electrode of the 14 PMOS pipe P14 is connected the drain electrode of the 13 PMOS pipe P13 with the source electrode of the 15 PMOS pipe P15, the source electrode of the 15 NMOS pipe N15 connects the drain electrode of the 16 NMOS pipe N16 and the grid of the 15 PMOS pipe P15, the drain electrode of the 14 PMOS pipe P14 connects the grid of the 18 NMOS pipe N18 and the grid of the 19 NMOS pipe N19, the drain electrode of the 15 PMOS pipe P15 connects the other end of the 4th capacitor C 4, the grid of the drain electrode of the 19 NMOS pipe N19 and the 20 NMOS pipe N20, the first logic control signal SW1 connects the grid of the 9th NMOS pipe N9, the grid of the tenth NMOS pipe N10, the grid of the 12 NMOS pipe N12, the grid of the grid of the 14 NMOS pipe N14 and the 16 NMOS pipe N16, the second logic control signal SW2 connects the grid of the 11 NMOS pipe N11, the grid of the grid of the 13 NMOS pipe N13 and the 15 NMOS pipe N15, the 3rd logic control signal SW3 connects the grid of the 17 NMOS pipe N17, the source electrode of the 17 NMOS pipe N17 is connected with an end of the 5th capacitor C 5 the output terminal VREF that makes voltage-reference, the source electrode of the one PMOS pipe P1, the source electrode of the 2nd PMOS pipe P2, the source electrode of the 3rd PMOS pipe P3, the source electrode of the 4th PMOS pipe P4, the source electrode of the 5th PMOS pipe P5, the source electrode of the 6th PMOS pipe P6, the source electrode of the 7th PMOS pipe P7, the source electrode of the 8th PMOS pipe P8, the source electrode of the tenth PMOS pipe P10, the source electrode of the 11 PMOS pipe P11, the source electrode of the source electrode of the 13 PMOS pipe P13 and the 16 PMOS pipe P16 all meets power vd D, the source electrode of the 2nd NMOS pipe N2, the source electrode of the 6th NMOS pipe N6, the source electrode of the 7th NMOS pipe N7, the source electrode of the 8th NMOS pipe N8, the source electrode of the 13 NMOS pipe N12, the source electrode of the 16 NMOS pipe N16, the source electrode of the 18 NMOS pipe N18, the source electrode of the 19 NMOS pipe N19, the source electrode of the 20 NMOS pipe N20, the collector of the first positive-negative-positive bipolar transistor Q1, the collector of the second positive-negative-positive bipolar transistor Q2, the emitter of the first npn type bipolar transistor Q3, the equal ground connection GND of the other end of the emitter of the second npn type bipolar transistor Q4 and the 5th capacitor C 5.
The control sequential of the first logic control signal Sw1 in this example, the second logic control signal Sw2 and the 3rd logic control signal Sw3 as shown in Figure 5, the deviation of introducing while overturning for fear of logic, Sw1, Sw2, tri-groups of control signals of Sw3 are not overlap signal.
The principle of work that this is routine and flow process are:
Biasing circuit partly produces the required electric current of back benchmark, and manage the current mirror of P6 composition by the circuit of current mirror to back by the 5th PMOS pipe P5 and the 6th PMOS, the 7th NMOS pipe N7 and the 8th NMOS pipe N8 work in linear zone, are equivalent to a linear resistance, and linear resistance is expressed as: R
ON=1/[μ
nC
OX(V
GSOne V
T)] and be less than the breadth length ratio of the 8th NMOS pipe N8, R like this in the breadth length ratio that when design set the 7th NMOS pipe N7
ON(M7)>R
ON(M8), thereby the first npn type bipolar transistor Q3 in current detection circuit and the second npn type bipolar transistor Q4 just can open under different temperatures, pour into different electric currents, V will under different temperatures the first positive-negative-positive bipolar transistor Q1 place branch road
PTATJust can change along with temperature variation, better compensate V
BEThe high-order temperature term.
Common bandgap voltage reference only has a zero temperature coefficient point in whole temperature range, in circuit of the present invention, three zero temperature coefficient points have been set, be distributed in low thermophase, the inadequate situation of compensation when moderate temperature stage and hot stage, the purpose of doing like this are to avoid in low thermophase overcompensation and at hot stage.Fig. 6 is compensation principle schematic diagram proposed by the invention, in whole temperature range, three zero temperature coefficient points is arranged, and lays respectively at T1, T2, T3 place.Under low temperature conditions, two branch roads of temperature sensing circuit are not all opened, and now only need the V of very little positive temperature coefficient (PTC)
PTATwith V
BEsuperimposed, obtain the bandgap voltage reference of less temperature coefficient, now zero temperature coefficient point is positioned at the T1 place, and reference voltage is expressed as: V
REF=V
BE2+ k*V
TlnN
l, k is scale-up factor, this formula is the same with traditional bandgap voltage reference, along with temperature raises gradually, the base-emitter voltage of the first npn type bipolar transistor Q3 and the second npn type bipolar transistor Q4 reduces, by the R of aforementioned analysis
ON(M7)>R
ON(M8), it is as can be known when the upper corresponding ohmically pressure drop of the 7th NMOS pipe N7 is greater than the cut-in voltage of the first npn type bipolar transistor Q3, ohmically pressure drop corresponding to the 8th NMOS pipe N8 also do not reach the cut-in voltage of the second npn type bipolar transistor Q4 pipe, so the first npn type bipolar transistor Q3 pipe is first opened, the second npn type bipolar transistor Q4 pipe is not opened, the 9th PMOS pipe P9 grid voltage is low level, the 9th PMOS pipe P9 opens, the 12 PMOS pipe P12 does not also open, now the first positive-negative-positive bipolar transistor Q1 place branch road can pour into the electric current by the 8th PMOS pipe P8 mirror image, now the reference voltage source expression formula is: V
REF=V
BE2+ k*V
TlnN
2, N
2can be expressed as: N
2=N
1* (W/L)
P8/ (W/L)
P5, this shows, it is large that positive temperature coefficient (PTC) becomes, and suitably sets the parameter in above-mentioned bandgap voltage reference expression formula, can obtain a zero temperature coefficient point at temperature T 2 places, when temperature further raises, the second npn type bipolar transistor Q4 also can open, and also can open thereby the 11 PMOS manages P11 place branch road, and the electric current of this branch road institute mirror image also can pour into the first positive-negative-positive bipolar transistor Q1 place branch road, now, bandgap voltage reference is expressed as: V
REF=V
BE2+ k* (V
TlnN
2+ V
TlnN
3), here, N
2as hereinbefore, N
3be expressed as: N
3=N
1* (W/L)
P11/ (W/L)
P5, positive temperature coefficient (PTC) further increases, and suitably sets the breadth length ratio of the 11 PMOS pipe P11, can in high temperature range, obtain another zero temperature coefficient point T3.Can find out thus, the present invention has three zero temperature coefficient points in whole temperature range, do not introduce high-order compensation, with respect to traditional single order bandgap voltage reference, simple in structure, has obviously improved compensation effect.
Switched-capacitor circuit work mainly is divided into two stages: the starting stage, when the first logic control signal Sw1 is high level, the second logic control signal Sw2 is low level, the 3rd logic control signal SW3 is low level, at this moment, operational amplifier is connected to the unity gain form, and the second capacitor C 2 is charged to V
BE1Current potential, amount of charge stored are C2*V
BE2, the first capacitor C 1 charging, the quantity of electric charge of storage is C1* (V
BE1-V
BE2); By the time in next moment, when the first logic control signal Sw1 was low level, the second logic control signal Sw2 was high level, the 3rd logic control signal Sw3 is high level, now, the electric charge on the first capacitor C 1 all is transferred on the 3rd capacitor C 3, and final reference voltage is output as: V
REF=V
BE2+ [C1* (V
BE1-V
BE2)/C3], change by the electric current of the first positive-negative-positive bipolar transistor Q1, thereby change △ V
BEValue, in whole temperature range, set three zero temperature coefficient points, thereby can obtain compensation effect preferably in the different temperatures scope.
In summary it can be seen, be compared to traditional bandgap voltage reference, the present invention adopts switched capacitor technique, avoided the use of large resistance on the sheet, simultaneously, temperature sensing circuit can be opened different branch roads under different temperatures, pour into electric current for a branch road of band-gap reference core circuit, thereby reach the temperature coefficient that changes PTAT voltage, in whole temperature range, three zero temperature coefficient points have been introduced, be compared to common first compensation phase circuit, the present invention has improved the precision of bandgap voltage reference output voltage, do not use large resistance, do not use high-order temperature compensation circuit yet, circuit structure is simple, saved chip area, reduced cost.
Claims (2)
1. bandgap voltage reference, it is characterized in that, comprise biasing circuit, the band-gap reference core circuit, temperature sensing circuit, switched-capacitor circuit and operational amplifier, the electric current that described biasing circuit produces by the current mirror mirror image to the band-gap reference core circuit, the output terminal of described band-gap reference core circuit is connected with the input end of switched-capacitor circuit, described temperature sensing circuit is connected on a branch road of band-gap reference core circuit, the input end in the same way of described operational amplifier is connected with an output terminal of switched-capacitor circuit, reverse input end is connected with another output terminal of switched-capacitor circuit, output terminal is connected with an output terminal of switched-capacitor circuit and as the output terminal of bandgap voltage reference.
2. a kind of bandgap voltage reference according to claim 1, it is characterized in that, described biasing circuit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS pipe N4, the 5th NMOS pipe N5 and the 6th NMOS pipe N6
Described band-gap reference core circuit comprises the 5th PMOS pipe P5, the 6th PMOS pipe P6, the first positive-negative-positive bipolar transistor Q1 and the second positive-negative-positive double-click transistor Q2,
Described temperature sensing circuit comprises the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 12 PMOS pipe P12, the 7th NMOS pipe N7, the 8th NMOS pipe N8, the 9th NMOS pipe N9, the tenth NMOS pipe N10, the first npn type bipolar transistor Q3 and the second npn type bipolar transistor Q4
Described switched-capacitor circuit comprises the 11 NMOS pipe N11, the 12 NMOS pipe N12, the 13 NMOS pipe N13, the 14 NMOS pipe N14, the 15 NMOS pipe N15, the 16 NMOS pipe N16, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, the first logic control signal SW1, the second logic control signal SW2 and the 3rd logic control signal SW3
Described operational amplifier comprises the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19, the 20 NMOS pipe N20, the 4th capacitor C 4 and the 5th capacitor C 5; Wherein,
The grid of the one PMOS pipe P1, the grid of the 2nd PMOS pipe P2, the grid of the 3rd PMOS pipe P3, the grid of the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the grid of the 6th PMOS pipe P6, the grid of the 7th PMOS pipe P7, the grid of the 8th PMOS pipe P8, the grid of the tenth PMOS pipe P10, the grid of the 11 PMOS pipe P11, the grid of the grid of the 13 PMOS pipe P13 and the 16 PMOS pipe P16 is connected and is connected with the drain electrode of the 3rd NMOS pipe N3 with the drain electrode of the 2nd PMOS pipe P2, the grid of the one NMOS pipe N1 is connected with the grid of the 2nd NMOS pipe N2 with the drain electrode of a PMOS pipe P1, the source electrode of a NMOS pipe N1, the drain electrode of the 2nd NMOS pipe N2 is connected with the source electrode of the 3rd NMOS pipe N3, the grid of the 3rd NMOS pipe N3, the grid of the 4th NMOS pipe N4 is connected with the drain electrode of the 3rd PMOS pipe P3, the source electrode of the 4th NMOS pipe N4, the source electrode of the 5th NMOS pipe N5 is connected with the drain electrode of the 6th NMOS pipe N6, and the grid of the grid of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected with the drain electrode of the 4th PMOS pipe P4,
The source electrode of the drain electrode of the drain electrode of the drain electrode of the 5th PMOS pipe P5, the 9th PMOS pipe P9, the 12 PMOS pipe P12, the 9th NMOS pipe N9 is connected with the emitter of the first positive-negative-positive bipolar transistor Q1, the base stage of the first positive-negative-positive bipolar transistor Q1 is connected with the base stage that the second positive-negative-positive is double-clicked transistor Q2, the drain electrode of the drain electrode of the drain electrode of the 6th PMOS pipe P6, the tenth NMOS pipe N10, the 12 NMOS pipe N12 is connected with the emitter that the second positive-negative-positive is double-clicked transistor Q2
The drain electrode of the 7th PMOS pipe P7, the base stage of the first npn type bipolar transistor Q3 is connected with the drain electrode of the 7th NMOS pipe N7, the grid of the 7th NMOS pipe N7 is connected bias voltage Vbias with the grid of the 8th NMOS pipe N8, the drain electrode of the 8th PMOS pipe P8 connects the source electrode of the 9th PMOS pipe P9, the grid of the 9th PMOS pipe P9 connects the collector of the first npn type bipolar transistor Q3, the drain electrode of the tenth PMOS pipe P10 connects the base stage of the second npn type bipolar transistor Q4 and the drain electrode of the 8th NMOS pipe N8, the collector of the second npn type bipolar transistor Q4 connects the grid of the 12 PMOS pipe P12, the source electrode of the 12 PMOS pipe P12 connects the drain electrode of the 11 PMOS pipe P11, the drain electrode of the 9th NMOS pipe N9 connects the drain electrode of an end and the 13 NMOS pipe N13 of the first capacitor C 1, the source electrode of the tenth NMOS pipe N10 connects the other end of the first capacitor C 1 and the source electrode of the 11 NMOS pipe N11,
The source electrode of the 12 NMOS pipe N12 connects the drain electrode of an end and the 15 NMOS pipe N15 of the second capacitor C 2, the drain electrode of the 11 NMOS pipe N11 connects the source electrode of the 14 NMOS pipe N14, an end of the 3rd capacitor C 3 and the grid of the 14 PMOS pipe P14, the drain electrode of the 14 NMOS pipe N14 and the other end of the 3rd capacitor C 3 are connected drain electrode and the drain electrode of the 17 NMOS pipe N17, an end of capacitor C 4 and the drain electrode of the 20 NMOS pipe N20 of the 16 PMOS pipe P16
The source electrode of the 14 PMOS pipe P14 is connected the drain electrode of the 13 PMOS pipe P13 with the source electrode of the 15 PMOS pipe P15, the source electrode of the 15 NMOS pipe N15 connects the drain electrode of the 16 NMOS pipe N16 and the grid of the 15 PMOS pipe P15, the drain electrode of the 14 PMOS pipe P14 connects the grid of the 18 NMOS pipe N18 and the grid of the 19 NMOS pipe N19, the drain electrode of the 15 PMOS pipe P15 connects the other end of the 4th capacitor C 4, the drain electrode of the 19 NMOS pipe N19 and the grid of the 20 NMOS pipe N20
The first logic control signal SW1 connects the grid of the 9th NMOS pipe N9, the grid of the tenth NMOS pipe N10, the grid of the 12 NMOS pipe N12, the grid of the 14 NMOS pipe N14 and the grid of the 16 NMOS pipe N16, the second logic control signal SW2 connects the grid of the 11 NMOS pipe N11, the grid of the 13 NMOS pipe N13 and the grid of the 15 NMOS pipe N15, the 3rd logic control signal SW3 connects the grid of the 17 NMOS pipe N17, the source electrode of the 17 NMOS pipe N17 is connected with an end of the 5th capacitor C 5 the output terminal VREF that makes voltage-reference
The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7, the 8th PMOS pipe P8, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 13 PMOS pipe P13 and the 16 PMOS pipe P16 all meets power vd D
The source electrode of the 2nd NMOS pipe N2, the source electrode of the 6th NMOS pipe N6, the source electrode of the 7th NMOS pipe N7, the source electrode of the 8th NMOS pipe N8, the source electrode of the 13 NMOS pipe N12, the source electrode of the 16 NMOS pipe N16, the source electrode of the 18 NMOS pipe N18, the source electrode of the 19 NMOS pipe N19, the source electrode of the 20 NMOS pipe N20, the collector of the first positive-negative-positive bipolar transistor Q1, the collector of the second positive-negative-positive bipolar transistor Q2, the emitter of the first npn type bipolar transistor Q3, the equal ground connection GND of the other end of the emitter of the second npn type bipolar transistor Q4 and the 5th capacitor C 5.
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| CN104111688A (en) * | 2014-05-13 | 2014-10-22 | 西安电子科技大学昆山创新研究院 | BiCMOS non-operational amplifier band gap voltage reference source with temperature monitoring function |
| CN105159381A (en) * | 2015-08-13 | 2015-12-16 | 电子科技大学 | Band-gap reference voltage source with index compensation feature |
| CN106339025A (en) * | 2016-05-23 | 2017-01-18 | 西安电子科技大学 | Low-voltage and high-precision band-gap reference circuit applied to node of Internet of Things |
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| CN104111688A (en) * | 2014-05-13 | 2014-10-22 | 西安电子科技大学昆山创新研究院 | BiCMOS non-operational amplifier band gap voltage reference source with temperature monitoring function |
| CN104111688B (en) * | 2014-05-13 | 2016-04-13 | 西安电子科技大学昆山创新研究院 | A kind of BiCMOS with temperature-monitoring function is without amplifier band gap voltage reference source |
| CN105159381A (en) * | 2015-08-13 | 2015-12-16 | 电子科技大学 | Band-gap reference voltage source with index compensation feature |
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| CN109032228A (en) * | 2017-06-12 | 2018-12-18 | 合肥格易集成电路有限公司 | A kind of operational amplifier and voltage reference source circuit |
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| CN111324168A (en) * | 2018-12-17 | 2020-06-23 | 比亚迪股份有限公司 | Band gap reference source |
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| US11843358B2 (en) | 2020-05-13 | 2023-12-12 | Radrock (shenzhen) Technology Co., Ltd. | Gain compensation device and bias circuit device |
| CN112732003A (en) * | 2021-04-06 | 2021-04-30 | 成都蕊源半导体科技有限公司 | Voltage regulator with temperature compensation and full-range input |
| CN114020085B (en) * | 2021-10-18 | 2023-10-27 | 杭州中科微电子有限公司 | Reference voltage generating circuit with multiple outputs |
| CN114020085A (en) * | 2021-10-18 | 2022-02-08 | 杭州中科微电子有限公司 | Multi-output reference voltage generating circuit |
| CN114185390A (en) * | 2021-12-08 | 2022-03-15 | 杭州海康威视数字技术股份有限公司 | Band-gap reference voltage source circuit, integrated circuit and electronic equipment |
| CN114356018A (en) * | 2021-12-31 | 2022-04-15 | 京微齐力(北京)科技有限公司 | Band-gap reference source circuit capable of switching conventional mode and low-voltage mode |
| WO2023231828A1 (en) * | 2022-06-02 | 2023-12-07 | 芯海科技（深圳）股份有限公司 | Bandgap reference voltage circuit, integrated circuit, and electronic device |
| CN115185329A (en) * | 2022-07-30 | 2022-10-14 | 上海锐星微电子科技有限公司 | Band gap reference structure |
| CN115562421A (en) * | 2022-10-24 | 2023-01-03 | 电子科技大学 | Single-particle radiation resistant reference source |
| CN117492507A (en) * | 2023-10-19 | 2024-02-02 | 华芯科技(恩施)有限公司 | Second-order compensation low-temperature coefficient reference voltage integrated circuit |
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