CN103399828B - Based on startup switching control and the method for active and standby storer - Google Patents
Based on startup switching control and the method for active and standby storer Download PDFInfo
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Abstract
The invention discloses a kind of startup switching control based on active and standby storer and method.The present invention substitutes existing logic chip and realizes the startup of CPU between primary storer and shelf storage to start switching control and switch, because startup switching control is made up of the digital element device of the low cost such as counter, logic gate, the Material Cost of electronic equipment thus can be avoided to improve; And the function starting switching device shifter only relies on annexation fixing between digital element device and does not need to carry out code loading as logic chip, thus can avoid the processing cost of electronic equipment and the raising of maintenance cost.
Description
Technical field
The present invention relates to start-up technique, particularly a kind of startup switching control based on active and standby storer and method.
Background technology
The startup of some electronic equipment needs CPU usually from such as all kinds of Flash(flash memory) etc. storer carry out Boot(guiding) load.But in actual applications, inevitably there is the situation such as Boot loss of data, destruction in storer, cause electronic equipment to complete and start and depot repair of having to.In order to avoid the problems referred to above, usually arrange physically or have in logic the storer of main and standby relation in prior art in the electronic device, and the root segment of Boot data is left in active and standby storer simultaneously.
Refer to Fig. 1, NORFlash(or non-flash is all selected for active and standby storer): the CPU of electronic equipment is connected with standby N ORFlash with the primary NORFlash depositing Boot data root segment with address bus respectively by data bus, so that can either carry out Boot loading, also can carry out Boot loading from standby N ORFlash from primary NORFlash when starting; And, in order to realize at primary NORFlash and standby N ORFlash the switching control selecting a loading, a logic chip, such as CPLD(ComplexProgrammableLogicDevice is also comprised in electronic equipment, CPLD), and be that the switching that CPU realizes starting controls by logic chip based on the active and standby framework of primary NORFlash and standby N ORFlash.Specifically:
After electronic equipment powers on, CPU sends chip selection signal CS0 to logic chip, the chip selection signal CS01 of primary for correspondence NORFlash is set to effectively according to chip selection signal CS0 acquiescence by logic chip, it is invalid to be set to by the chip selection signal CS02 of corresponding standby N ORFlash, then waiting for CPU from primary NORFlash carry out Boot loading and timing;
If CPU loads successfully before logic chip timing time-out, then CPU can utilize GPIO(GeneralPurposeInputOutput, universal input/output) signal notification logic chip stopping timing;
If but CPU does not load successfully yet after logic chip timing time-out, then logic chip can not receive this GPIO signal, thus logic core sector-meeting due to timing time-out and by cpu reset, and the chip selection signal CS02 of corresponding standby N ORFlash is set to effectively, the chip selection signal CS01 of primary for correspondence NORFlash is set to invalid, switch to realize loading between primary NORFlash and standby N ORFlash.
But, for have low cost require electronic equipment, above-mentioned utilize logic chip realize start switch control mode can cause electronic equipment following several in cost improve:
1, logic core sector-meeting causes the Material Cost of electronic equipment to improve;
2, logic chip needs to load the function that really can possess above-mentioned startup switching and control by carrying out code in advance, and the code of logic chip is loaded electronic equipment will certainly be made to increase by one extra operation, thus cause the processing cost of electronic equipment to improve;
3, the code loaded in logic chip needs to be safeguarded, thus causes the maintenance cost of electronic equipment to improve.
Summary of the invention
In view of this, the invention provides a kind of startup switching control based on active and standby storer and method.
A kind of startup switching control based on active and standby storer provided by the invention, this startup switching control is applied to the electronic equipment comprising CPU, primary storer, shelf storage; This startup switching control comprises clock generating circuit, timing reset circuit and sheet and selects commutation circuit;
Described clock generating circuit starts to produce square-like clock signal after described electronic equipment powers on;
Described timing reset circuit loads from described primary memory the process started to described CPU according to described square-like clock signal and carries out timing, and loads to start from described primary storer at described CPU and to stop timing successfully, after timing time-out, trigger described cpu reset;
The described storer selecting commutation circuit to carry out described CPU loading startup after the timing time-out of described timing reset circuit switches to described shelf storage from described primary storer;
Wherein, described timing reset circuit comprises the first counter;
The counting input end of described first counter receives described square-like clock signal, to make described first counter carry out binary counting to described square-like clock signal;
The clear terminal of described first counter receives the first indicator signal of described CPU output; Wherein, described first indicator signal be defaulted as after device power inactive level, rearmounted from described primary storer start-up loading success at described CPU be significant level; When described first indicator signal is inactive level, the clear terminal of described first counter is prohibited; When described first indicator signal is significant level, the clear terminal of described first counter is enabled;
The terminal count output of the highest meter digital of described first counter exports timing level signal; Wherein, after described first rolling counters forward reaches numerical value corresponding to described most significant digit, it is significant level that described timing level signal is overturn by inactive level; After counting spilling occurs described first counter, described timing level signal overturns as inactive level by counting the zero of the circulation after overflowing from significant level;
The counting of described first counter overflows the reset terminal output counting spill over of end to described CPU; Wherein, after counting spilling occurs described first counter, described counting spill over is set to significant level and is set to inactive level after described circulation zero.
Alternatively, described clock generating circuit comprises clock generator; Described clock generator starts to produce described square-like clock signal after described electronic equipment powers on.
Alternatively, described clock generating circuit comprises clock generator and the second counter; Described clock generator starts to produce initial clock signal after described electronic equipment powers on; The counting input end of described second counter receives described initial clock signal, to make described second counter carry out binary counting to described initial clock signal; The terminal count output of any one meter digital of described second counter exports the described square-like clock signal obtained described initial clock signal frequency division.
Alternatively, described clock generator is asymmetric multivibrator.
Alternatively, described clock generator produces the described initial clock signal of 1Hz; The terminal count output of the lowest count position of described second counter exports the described square-like clock signal of the 1/2Hz after two divided-frequency to described first counter; Described first counter has 4 meter digitals.
Alternatively, described is selected commutation circuit to comprise the 3rd counter and logic gate assembly;
The counting input end of described 3rd counter receives described timing level signal, to make described 3rd counter carry out binary counting to the level rollover event of described timing level signal from significant level to inactive level;
The terminal count output of the lowest count position of described 3rd counter produces latch level signal; Wherein, when described timing level signal produces the level upset from significant level to inactive level, the level that described latch level signal produces from inactive level to significant level thereupon overturns;
The clear terminal of described 3rd counter receives described first indicator signal; Wherein, when described first indicator signal is inactive level, the clear terminal of described first counter is prohibited; When described first indicator signal is significant level, the clear terminal of described 3rd counter is enabled;
The second indicator signal that described logic gate assembly exports according to described latch level signal and described CPU, exports the first chip selection signal and the second chip selection signal respectively to described primary storer and described shelf storage; Wherein, described second indicator signal is defaulted as inactive level, after described shelf storage start-up loading success, is set to significant level at described CPU after device power; When described latch level signal or described second indicator signal are significant level, the described first exported to described primary storer selects invalidating signal, described second chip selection signal that exports to described shelf storage is effective; When described latch level signal and described second indicator signal are inactive level, described first chip selection signal exported to described primary storer effectively, described second chip selection signal to export to described shelf storage is invalid.
Alternatively, the significant level of described timing level signal is high level, inactive level is low level, the counting input end of described 3rd counter with level rising edge for counting trigger condition; The terminal count output of the highest meter digital of described first counter connects the counting input end of described 3rd counter by the first reverser.
Alternatively, the significant level of described first indicator signal is identical with the enable level of the clear terminal of the first counter, contrary with the enable level of the clear terminal of the 3rd counter; Described first indicator signal exports the clear terminal of described 3rd counter to by the second reverser.
Alternatively, described logic gate assembly selects cue according to described latch level signal to described CPU output chip; Wherein, when described latch level signal is inactive level, described is selected cue to be set to the memory-aided level state of the described master of expression; When described latch level signal or described second indicator signal are significant level, described is selected cue to be set to the level state representing described shelf storage.
Alternatively, it is invalid that one of them of described first indicator signal and described second indicator signal is set to by force significant level by described CPU further, another is set to by force by described CPU.
Alternatively, described logic gate assembly controls described first chip selection signal and described second chip selection signal according to a chip enable signal further; Wherein, when described chip enable signal is invalid, it is invalid that described first chip selection signal and described second chip selection signal are all set to by force.
Alternatively, the significant level of described latch level signal and described second indicator signal is high level, inactive level is low level, described chip enable signal and described first chip selection signal and described second chip selection signal significant level is low level, inactive level is high level;
Described logic gate assembly comprises first or door, second or door, the 3rd or door and the 3rd reverser;
Described first or Men mono-road input end receives described latch level signal, another road input end receives described second indicator signal, described first or the output terminal of door produce described and select cue;
Described second or Men mono-road input end connected by described 3rd reverser and receive described chip enable signal from described first or the output terminal of door, another road input end, described second or the output terminal of door produce described second chip selection signal;
Described 3rd or Men mono-road input end connect and receive described chip enable signal from described first or the output terminal of door, another road input end, the described 3rd or the output terminal of door produce described first chip selection signal.
Alternatively, described is selected cue to be GPIO signal.
Alternatively, described first indicator signal is GPIO signal.
Alternatively, described second indicator signal is GPIO signal.
A kind of startup method for handover control based on active and standby storer provided by the invention, this startup method for handover control utilizes the loading of startup switching control control CPU as above between primary storer and shelf storage to start switching.
As can be seen here, the present invention substitutes existing logic chip and realizes the startup of CPU between primary storer and shelf storage to start switching control and switch, because startup switching control is made up of the digital element device of the low cost such as counter, logic gate, the Material Cost of electronic equipment thus can be avoided to improve; And the function starting switching device shifter only relies on annexation fixing between digital element device and does not need to carry out code loading as logic chip, thus can avoid the processing cost of electronic equipment and the raising of maintenance cost.
Accompanying drawing explanation
Fig. 1 realizes starting the hardware frame schematic diagram switched based on active and standby storer in prior art;
Fig. 2 realizes starting the hardware frame schematic diagram switched based on active and standby storer in the embodiment of the present invention;
Fig. 3 is a kind of concrete structure schematic diagram of the startup switching control shown in Fig. 2;
Fig. 4 a to Fig. 4 d is the signal sequence schematic diagram had in the startup switching control of structure as shown in Figure 3.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.
Refer to Fig. 2, startup switching control 20 in the present embodiment is applied to the electronic equipment comprising CPU and primary storer and shelf storage (can select any one Flash or other memory devices), substitutes existing logic chip realize the startup switching of CPU between primary storer and shelf storage to utilize this startup switching control 20.Wherein, the low-cost digital components and parts that this startup switching control 20 is loaded without the need to code by such as counter, logic gate etc. are formed, and are intended to avoid the raising of the Material Cost of electronic equipment, processing cost and maintenance cost.
Can realize the startup of CPU between primary storer and shelf storage to make startup switching control 20 as logic chip to switch, starting switching control 20 needs to have following functions:
1, the clock signal being used for timing is produced;
2, from the time of primary storer start-up loading, timing is carried out to CPU according to clock signal, and stop timing during the success of CPU start-up loading, reset CPU after timing time-out;
3, timing time out event is converted into CPU from primary storer to the switching of shelf storage.
Correspondingly, for realizing above-mentioned 3 functions, this startup switching control comprises clock generating circuit 21, timing reset circuit 22 and sheet and selects commutation circuit 23, wherein:
Clock generating circuit 21 starts to produce square-like clock signal Clk after electricity on an electronic device;
Timing reset circuit 22 carries out timing to CPU from main memory-aided loading start-up course according to square-like clock signal Clk, and loads to start from primary storer at CPU and to stop timing successfully, after timing time-out, trigger cpu reset;
Sheet selects commutation circuit 23, after the timing time-out of timing reset circuit, the current storer carrying out loading startup is switched to shelf storage from primary storer by CPU.
Below, refer to Fig. 3 and simultaneously composition graphs 2, select commutation circuit 23 to be described in detail respectively to above-mentioned clock generating circuit 21, timing reset circuit 22 and sheet.
(1), clock generating circuit 21:
In figure 3, clock generating circuit 21 comprises the counter C1 of clock generator O and 4 binary counting.Wherein, clock generator O0 can select any one asymmetric multivibrator existing, and correspondingly, the frequency of its initial clock signal Clk ' produced can be set by the capacitance of setting asymmetric multivibrator and resistance value; Counter C1 can select model to be two 4 digit counter chips of 74HC393, and a part for the two 4 digit counter chips utilizing model to be 74HC393 is to realize counter C1.
Clock generator O0 starts to produce an initial clock signal Clk ' after electricity on an electronic device.
The counting input end C1_CP of counter C1 receives initial clock signal Clk ', to make counter C1 carry out binary counting to initial clock signal Clk '; The terminal count output C1_Q0 of the lowest count position of counter C1 exports the square-like clock signal Clk obtained initial clock signal Clk ' two divided-frequency.
Thus, the generation of the clock signal for timing can be realized.In addition, when counter C1 selects model to be two 4 digit counter chips of 74HC393 a part of, can be high level by the clear terminal C1_CLR pull-up of counter C1, to forbid that counter C1 is cleared, thus guarantee the waveform correctness of square-like clock signal Clk.
It should be noted that:
1), the present embodiment is only that the meter digital of counter C1 adds up to 4 for example, but in practical application, counter C1 type selecting is not limited to two 4 digit counter chips that model is 74HC393, and correspondingly, the meter digital sum of counter C1 is not limited to 4.
2), the present embodiment is only the square-like clock signal Clk exporting two divided-frequency for the terminal count output C1_Q0 of the lowest count position of counter C1, but in actual applications, the terminal count output C1_Qi(i of any one meter digital of counter C1 is the positive integer being more than or equal to 0, being less than or equal to the meter digital of counter C1 sum-1) all can export and 2 are carried out to initial clock signal Clk '
i+1the square-like clock signal Clk of frequency division.
3), when clock generator O0 selects asymmetric multivibrator, the frequency of its initial clock signal Clk ' produced can be set arbitrarily by setting capacitance and resistance value, now, the oscillation frequency that also directly can arrange clock generator O0 meets the frequency requirement of square-like clock signal Clk and carries out scaling down processing without the need to recycling counter C1, that is, be not that necessary, clock generator O0 can directly start to produce square-like clock signal Clk after electricity on an electronic device for the counter C1 of frequency division.
(2), timing reset circuit 22:
In figure 3, timing reset circuit 22 comprises the counter C2 of 4 binary countings.Wherein, counter C2 can select model to be the 4 digit counter chips of 74HC193.
The counting input end C2_CP of counter C2 receives square wave clock signal C lk, to make counter C2 carry out binary counting to square wave clock signal C lk;
The clear terminal C2_MR of counter C2 receives the indicator signal GPIO0 of CPU output, wherein:
The acquiescence level state of indicator signal GPIO0 on an electronic device after electricity be invalid low level, to represent that CPU not yet completes start-up loading from primary storer, CPU from the level state after primary storer start-up loading success be effective high level, to represent that CPU completes start-up loading from primary storer;
When indicator signal GPIO0 is invalid low level, CPU not yet completes start-up loading from primary storer, and the clear terminal C2_MR of counter C2 connects and is prohibited, to guarantee proceeding of timing at CPU from the process that primary storer loading starts;
When indicator signal GPIO0 is effective high level, CPU completes start-up loading from primary storer, and the clear terminal C2_MR of counter C2 is enabled, stop counting to load to start successfully from primary storer at CPU.
The terminal count output C2_Q3 of the highest meter digital of counter C2 exports timing level signal u1.Wherein:
After counter C2 counting reaches numerical value corresponding to most significant digit (i.e. 8 clock period of square-like clock signal Clk), timing level signal u1 overturns as effective high level by invalid low level;
After counting spilling (i.e. 15 clock period of square-like clock signal Clk) occurs counter C2, circulation zero (i.e. 16 clock period of square-like clock signal Clk) after timing level signal u1 is overflowed by counting overturns for invalid low level, to represent timing time-out from effective high level.
The counting of counter C2 overflows the reset terminal CPU_RST output counting spill over Count_up of end C2_TCU to CPU.Wherein:
After counting spilling occurs counter C2, counting spill over Count_up is set to effective low level and is set to invalid high level after circulation zero.
Thus, counter C2 just can realize the timing of 16 clock period of square-like clock signal Clk from main memory-aided loading start-up course for CPU, and to load from primary storer at CPU and starts successfully by being stopped timing by CPU to the clearing of counter C2, utilizing when timing time-out is about to generation the counting of counter C2 spilling to trigger cpu reset.
Such as, suppose that clock generator O0 produces the initial clock signal Clk ' of 1Hz, the square-like clock signal Clk of the 1/2Hz after the terminal count output C1_Q0 two divided-frequency of the lowest count position of counter C1, then the counter C2 of 4 meter digitals can realize the timing duration of 32 seconds.And, counting due to counter C2 overflows and is really reaching just generation between 32 seconds timing durations, therefore, CPU can reset in advance before timing time-out, so that can switch to shelf storage immediately when the real generation of timing time-out to carry out start-up loading.
In addition, when counter C2 selects model to be the 4 digit counter chip of 74HC193, counter C2 also has 4 data input pin D0 ~ D4, but 4 data input pin D0 ~ D4 do not need to be used, and can be thus invalid high level by the asynchronous parallel control end C2_PL pull-up of counter C2.
It should be noted that:
1), the present embodiment is only that the meter digital of counter C2 adds up to 4 for example, but in practical application, counter C2 type selecting is not limited to the 4 digit counter chips that model is 74HC193, correspondingly, the meter digital sum of counter C2 is not limited to 4, but can the length according to the timing duration demand of reality and in conjunction with the clock period of square-like clock signal Clk select arbitrarily.
2), the present embodiment is only effective with timing level signal u1 high level, low level is invalid, and, the clear terminal C2_MR of counter C2 be high level enable be example, but in practical application, counter C2 type selecting is not limited to the 4 digit counter chips that model is 74HC193, correspondingly, according to the chip characteristics of the different type selecting chips of counter C2, effective and the inactive level of timing level signal u, and the enable level of the clear terminal C2_MR of counter C2 all can correspondingly adjust, so, the implication of the level rollover event of timing level signal u1, the level implication of indicator signal GPIO0 also needs adjustment with the enable level of clear terminal C2_MR and respective change.
(3), sheet selects commutation circuit 23:
In figure 3, sheet selects commutation circuit 23 to comprise counter C3 and the logic gate assembly LG of 4 binary countings.Wherein, when counter C1 selects model to be two 4 digit counter chips of 74HC393 a part of, counter C3 can select model to be that another part of two 4 digit counter chips of 74HC393 realizes; Logic gate assembly can be combined by various basic logical gate.
The counting input end C3_CP of counter C3 receives timing level signal u1, to make counter C3 represent that the negative edge level rollover event of timing time-out carries out binary counting to timing level signal u1 by a reverser Rev1.
The terminal count output C3_Q0 of the lowest count position of counter C3 produces latch level signal u2.Wherein:
When timing level signal u1 produces above-mentioned negative edge level upset, the latch level signal u2 rising edge level thereupon produced from invalid low level to effective high level overturns, to represent the negative edge level rollover event capturing timing level signal u1 and represent timing time-out.
The clear terminal C3_CLR of counter C3 receives indicator signal GPIO0 by reverser Rev2.Wherein:
When indicator signal GPIO0 is invalid low level, CPU does not complete start-up loading from primary storer, the clear terminal C3_CLR of counter C3 by through reverser Rev2 oppositely after high level indicator signal GPIO0 forbid, before making latch level signal u2 once produce on timing level signal u1 to represent the negative edge level rollover event of timing time-out, be latched as effective high level, that is, the loading starting state of CPU is continued be designated CPU failed from main memory-aided start-up loading;
When indicator signal GPIO0 is effective high level, when CPU completes start-up loading from primary storer, the clear terminal C3_CLR of counter C3 by through reverser Rev2 oppositely after low level indicator signal GPIO0 enable, to make latch level signal u2 be playbacked as invalid low level, that is, represent now whether overtime from main memory-aided start-up loading without the need to paying close attention to CPU again.
The indicator signal GPIO1 that logic gate assembly LG exports according to latch level signal u2 and CPU, exports chip selection signal CS01 and chip selection signal CS02 respectively to primary storer and shelf storage.Wherein:
The acquiescence level state of indicator signal GPIO1 on an electronic device after electricity be invalid low level, to represent that CPU not yet completes start-up loading from shelf storage, CPU from the level state after the success of shelf storage start-up loading be effective high level, to represent that CPU completes start-up loading from shelf storage;
When latch level signal u2 and indicator signal GPIO1 is invalid low level, the chip selection signal CS01 exported to primary storer is effective low level, the chip selection signal CS02 that exports to shelf storage is invalid high level;
When latch level signal u2 or indicator signal GPIO1 is effective high level, represent that CPU needs to load startup from shelf storage or represent that CPU has completed from shelf storage to load startup owing to starting unsuccessfully from primary storer loading, correspondingly, the chip selection signal CS02 that the chip selection signal CS01 exported to primary storer is invalid high level, export to shelf storage is effective low level.
Thus, by counter C3, timing level signal u1 is represented to the Logic judgment that the sampling latch of the negative edge level rollover event of timing time-out and logic gate assembly LG carry out from main memory-aided start-up loading state the CPU represented by latch level signal u2, chip selection signal CS01 and CS02 that logic gate assembly LG can be utilized to produce realize the sheet choosing switching of primary storer and shelf storage.
Further, logic gate assembly LG can also select cue GPIO2 according to latch level signal u2 to CPU output chip.Wherein:
When latch level signal u2 and indicator signal GPIO1 is invalid low level, sheet selects cue GPIO2 to be set to the main memory-aided low level of expression;
When latch level signal u2 or indicator signal GPIO1 is effective high level, sheet selects cue GPIO2 to be set to the high level representing shelf storage.
Thus, by the Logic judgment that logic gate assembly LG carries out from the start-up loading state of shelf storage from the CPU that main memory-aided start-up loading state and indicator signal GPIO1 represent the CPU represented by latch level signal u2, namely cue GPIO2 is selected to point out the storer of CPU current institute sheet choosing to be primary storer or shelf storage by sheet.
In addition, when any one in primary storer and shelf storage needs to be repaired, CPU can pass through that in indicator signal GPIO0 and GPIO1 is set to by force effective high level, another is set to by force invalid low level, to utilize indicator signal GPIO0 to the control of latch level signal u2 and indicator signal GPIO1 itself, Trigger Logic door assembly LG is by the set by force to chip selection signal CS01 and CS02, to realize sheet choosing by force for storer to be repaired.
And then logic gate assembly LG can also control chip selection signal CS01 and CS02 according to a chip enable signal CS00 further; Wherein, when chip enable signal CS00 is effective low level; each in chip selection signal CS01 and CS02 can both be allowed to be set to effective low level; and when chip enable signal CS00 is invalid high level, chip selection signal CS01 and CS02 is all set to by force invalid high level, to realize the read-write protection to primary storer and shelf storage.
For the logic gate assembly LG with above-mentioned functions, present embodiments provide one and preferably realize structure, refer to Fig. 3, logic gate assembly LG comprises or door OR1 or door OR2 or door OR3 and reverser Rev3, wherein:
Or a road input end of door OR1 receives latch level signal u2, another road input end receives indicator signal GPIO1, or the output terminal generation sheet of door OR1 selects cue GPIO2;
Or a road input end of door OR2 is connected certainly by reverser Rev3 or the output terminal of door OR1, another road input end reception chip enable signal CS00, or the output terminal of door OR2 produces chip selection signal CS02;
Or a road input end of door OR3 connects certainly or the output terminal of door OR1, another road input end reception chip enable signal CS00, or the output terminal of door OR3 produces chip selection signal CS01.
It should be noted that:
1), the present embodiment arranges reverser Rev1 between the terminal count output C2_Q3 and the counting input end C3_CP of counter C3 of the highest meter digital of counter C2, because timing level signal u represents that the level rollover event of timing time-out is negative edge, and the counting trigger condition of the counting input end C3_CP of counter C3 is rising edge, but in actual applications, if the chip characteristics of the type selecting chip of counter C2 sum counter C3 determines timing level signal u represent that the level rollover event of timing time-out and the counting trigger condition of counting input end C3_CP match, then reverser Rev1 can not be set.
In like manner, the clear terminal C3_CLR of the counter C3 in the present embodiment receives indicator signal GPIO0 by reverser Rev2, because indicator signal GPIO0 represents that the memory-aided level of the non-selected master of CPU is identical with the enable level of the clear terminal C2_MR of counter C2, but it is contrary with the enable level of the clear terminal C3_CLR of counter C3, but in actual applications, if the chip characteristics of the type selecting chip of counter C2 sum counter C3 determines indicator signal GPIO0 represent that the memory-aided level of the non-selected master of CPU is contrary with the enable level of the clear terminal C2_MR of counter C2, then the clear terminal C2_MR of counter C2 also can receive indicator signal GPIO0 by reverser, if indicator signal GPIO0 represents the non-selected master of CPU, memory-aided level is identical with the enable level of the clear terminal C3_CLR of counter C3, then the clear terminal C3_CLR of counter C3 is without the need to receiving indicator signal GPIO0 by reverser Rev2.
2), the present embodiment utilizes counter C3 to realize sampling latch, but any one trigger also can be utilized in practical application to carry out alternative counter C3, based on the sequential relationship between timing level signal u1 and latch level signal u2, those skilled in the art reasonably can arrange trigger, repeat no more herein.
3), the specific implementation structure that provides for logic gate assembly LG of the present embodiment, be based on latch level signal u2 and indicator signal GPIO1 significant level is high level, inactive level is low level, the significant level of chip enable signal CS00 and chip selection signal CS01 and CS02 is low level, to be high level be example to inactive level, but in actual applications, for different signal definitions, the structure of logic gate assembly LG also can correspondingly adjust, and will not enumerate herein.
Below, then in conjunction with the signal of sequential chart to above-mentioned each several part circuit be described in detail.
The time program process that CPU successfully realizes start-up loading from primary storer refers to Fig. 4 a:
After device power starts, indicator signal GPIO0 is invalid low level, counter C2 can count and can not be instructed to signal GPIO0 and continue to reset from 0, now, the timing level signal u1 that the terminal count output C2_Q3 of the highest meter digital of counter C2 exports is invalid low level, and the latch level signal u2 that the terminal count output C3_Q0 of the lowest count position of counter C3 exports also is invalid low level; Correspondingly, because indicator signal GPIO1 is also invalid low level, thus after the Logic judgment of logic gate assembly LG, chip selection signal CS01 is effective low level, chip selection signal CS02 is invalid high level, and CPU can carry out loading from primary storer and start;
When counter C2 counting reaches 8 clock period of square-like clock signal Clk, the timing level signal u1 that the terminal count output C2_Q3 of the highest meter digital of counter C2 exports becomes effective high level from invalid low level, now, the latch level signal u2 that the terminal count output C3_Q0 of the lowest count position of counter C3 exports is still invalid low level; Correspondingly, because indicator signal GPIO1 is also still now invalid low level, thus after the Logic judgment of logic gate assembly LG, chip selection signal CS01 continues to remain on effective low level, chip selection signal CS02 continues to remain on invalid high level, and CPU can continue to carry out loading from primary storer and start;
When counter C2 counting not yet reaches 15 clock period of square-like clock signal Clk and CPU completes start-up loading from primary storer, counting can not be there is and overflow in counter C2, its counting overflows holds C2_TCU to be the invalid of high level to the reset terminal CPU_RST output counting spill over Count_up of CPU, correspondingly, CPU can not carry out resetting and indicator signal GPIO0 being become the effective of high level;
After this, counter C2 is cleared, the timing level signal u1 that the terminal count output C2_Q3 of its highest meter digital exports becomes invalid low level and continues to reset owing to being instructed to signal GPIO0 and remaining on invalid low level, correspondingly, the latch level signal u2 that the terminal count output C3_Q0 of the lowest count position of counter C3 exports be still invalid low level, indicator signal GPIO1 is also still invalid low level, therefore, chip selection signal CS01 continues to remain on effective low level, chip selection signal CS02 continues to remain on invalid high level.
CPU is from the failure of primary storer start-up loading and switch to the time program process that shelf storage carries out start-up loading and refer to Fig. 4 b:
After device power starts, indicator signal GPIO0 is invalid low level, counter C2 can count and can not be instructed to signal GPIO0 and continue to reset from 0, now, the timing level signal u1 that the terminal count output C2_Q3 of the highest meter digital of counter C2 exports is invalid low level, and the latch level signal u2 that the terminal count output C3_Q0 of the lowest count position of counter C3 exports also is invalid low level; Correspondingly, because indicator signal GPIO1 is also invalid low level, thus after the Logic judgment of logic gate assembly LG, chip selection signal CS01 is effective low level, chip selection signal CS02 is invalid high level, and CPU can carry out loading from primary storer and start;
When counter C2 counting reaches 8 clock period of square-like clock signal Clk, the timing level signal u1 that the terminal count output C2_Q3 of the highest meter digital of counter C2 exports becomes effective high level from invalid low level, now, the latch level signal u2 that the terminal count output C3_Q0 of the lowest count position of counter C3 exports is still invalid low level; Correspondingly, because indicator signal GPIO1 is also still now invalid low level, thus after the Logic judgment of logic gate assembly LG, chip selection signal CS01 continues to remain on effective low level, chip selection signal CS02 continues to remain on invalid high level, and CPU can continue to carry out loading from primary storer and start;
When counter C2 counting has reached 15 clock period of square-like clock signal Clk but CPU fails to complete start-up loading from primary storer, there is counting and overflow in counter C2, its counting overflows holds C2_TCU to become effectively low level to the reset terminal CPU_RST output counting spill over Count_up of CPU, correspondingly, CPU resets;
After counter C2 counts zero, its counting overflows holds C2_TCU to revert to again the invalid of high level to the reset terminal CPU_RST output counting spill over Count_up of CPU, cpu reset terminates, and the timing level signal u1 that the terminal count output C2_Q3 of the highest meter digital of counter C2 exports becomes invalid low level from effective high level, now, the latch level signal u2 saltus step that the terminal count output C3_Q0 of the lowest count position of counter C3 exports is effective high level, but indicator signal GPIO1 is still invalid low level, correspondingly, after the Logic judgment of logic gate assembly LG, chip selection signal CS01 due to latch level signal u2 saltus step be that effective high level is changed to invalid high level, chip selection signal CS02 is changed to effective low level for effective high level due to latch level signal u2 saltus step, the CPU completing reset again can carry out loading from shelf storage and start,
After this, after CPU completes start-up loading from shelf storage, indicator signal GPIO1 is set to effective high level, correspondingly, constantly count although counter C2 now still can circulate and cause the saltus step repeatedly of latch level signal u2, continue to be set to effective high level indicator signal GPIO1 can make chip selection signal CS01 remain on invalid high level, chip selection signal CS02 remains on effective low level.
CPU to any one in primary storer and shelf storage carry out the choosing of sheet by force time program process as illustrated in fig. 4 c:
When CPU crosses, in indicator signal GPIO0 and GPIO1 is set to by force effective high level, another is set to by force invalid low level, control the level change of latch level signal u2 and the level change of indicator signal GPIO1 itself by indicator signal GPIO0, Trigger Logic door assembly LG is by the set by force to chip selection signal CS01 and CS02, to realize sheet choosing by force for storer to be repaired.
To primary storer and shelf storage carry out simultaneously read-write protection time program process as shown in figure 4d:
When chip enable signal CS00 is effective low level; each in chip selection signal CS01 and CS02 can both be allowed to be set to effective low level; and when chip enable signal CS00 is invalid high level, chip selection signal CS01 and CS02 is all set to by force invalid high level, to realize the read-write protection to primary storer and shelf storage.
Except above-mentioned startup switching control, the present embodiment additionally provides a kind of startup method for handover control based on active and standby storer, and this startup method for handover control utilizes the loading of startup switching control control CPU as above between primary storer and shelf storage to start switching.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (16)
1. based on a startup switching control for active and standby storer, it is characterized in that, this startup switching control is applied to the electronic equipment comprising CPU, primary storer, shelf storage; This startup switching control comprises clock generating circuit, timing reset circuit and sheet and selects commutation circuit;
Described clock generating circuit starts to produce square-like clock signal after described electronic equipment powers on;
Described timing reset circuit loads from described primary storer the process started to described CPU according to described square-like clock signal and carries out timing, and loads to start from described primary storer at described CPU and to stop timing successfully, after timing time-out, trigger described cpu reset;
The described storer selecting commutation circuit to carry out described CPU loading startup after the timing time-out of described timing reset circuit switches to described shelf storage from described primary storer;
Wherein, described timing reset circuit comprises the first counter;
The counting input end of described first counter receives described square-like clock signal, to make described first counter carry out binary counting to described square-like clock signal;
The clear terminal of described first counter receives the first indicator signal of described CPU output; Wherein, described first indicator signal be defaulted as after device power inactive level, rearmounted from described primary storer start-up loading success at described CPU be significant level; When described first indicator signal is inactive level, the clear terminal of described first counter is prohibited; When described first indicator signal is significant level, the clear terminal of described first counter is enabled;
The terminal count output of the highest meter digital of described first counter exports timing level signal; Wherein, after described first rolling counters forward reaches numerical value corresponding to described most significant digit, it is significant level that described timing level signal is overturn by inactive level; After counting spilling occurs described first counter, described timing level signal overturns as inactive level by counting the zero of the circulation after overflowing from significant level;
The counting of described first counter overflows the reset terminal output counting spill over of end to described CPU; Wherein, after counting spilling occurs described first counter, described counting spill over is set to significant level and is set to inactive level after described circulation zero.
2. startup switching control according to claim 1, is characterized in that, described clock generating circuit comprises clock generator;
Described clock generator starts to produce described square-like clock signal after described electronic equipment powers on.
3. startup switching control according to claim 1, is characterized in that, described clock generating circuit comprises clock generator and the second counter;
Described clock generator starts to produce initial clock signal after described electronic equipment powers on;
The counting input end of described second counter receives described initial clock signal, to make described second counter carry out binary counting to described initial clock signal;
The terminal count output of any one meter digital of described second counter exports the described square-like clock signal obtained described initial clock signal frequency division.
4. the startup switching control according to Claims 2 or 3, is characterized in that, described clock generator is asymmetric multivibrator.
5. startup switching control according to claim 3, is characterized in that,
Described clock generator produces the described initial clock signal of 1Hz;
The terminal count output of the lowest count position of described second counter exports the described square-like clock signal of the 1/2Hz after two divided-frequency to described first counter;
Described first counter has 4 meter digitals.
6. startup switching control according to claim 1, is characterized in that, described is selected commutation circuit to comprise the 3rd counter and logic gate assembly;
The counting input end of described 3rd counter receives described timing level signal, to make described 3rd counter carry out binary counting to the level rollover event of described timing level signal from significant level to inactive level;
The terminal count output of the lowest count position of described 3rd counter produces latch level signal; Wherein, when described timing level signal produces the level upset from significant level to inactive level, the level that described latch level signal produces from inactive level to significant level thereupon overturns;
The clear terminal of described 3rd counter receives described first indicator signal; Wherein, when described first indicator signal is inactive level, the clear terminal of described first counter is prohibited; When described first indicator signal is significant level, the clear terminal of described 3rd counter is enabled;
The second indicator signal that described logic gate assembly exports according to described latch level signal and described CPU, exports the first chip selection signal and the second chip selection signal respectively to described primary storer and described shelf storage; Wherein, described second indicator signal is defaulted as inactive level, after described shelf storage start-up loading success, is set to significant level at described CPU after device power; When described latch level signal or described second indicator signal are significant level, the described first exported to described primary storer selects invalidating signal, described second chip selection signal that exports to described shelf storage is effective; When described latch level signal and described second indicator signal are inactive level, described first chip selection signal exported to described primary storer effectively, described second chip selection signal to export to described shelf storage is invalid.
7. startup switching control according to claim 6, is characterized in that, the significant level of described timing level signal is high level, inactive level is low level, the counting input end of described 3rd counter with level rising edge for counting trigger condition;
The terminal count output of the highest meter digital of described first counter connects the counting input end of described 3rd counter by the first reverser.
8. startup switching control according to claim 6, is characterized in that, the significant level of described first indicator signal is identical with the enable level of the clear terminal of the first counter, contrary with the enable level of the clear terminal of the 3rd counter;
Described first indicator signal exports the clear terminal of described 3rd counter to by the second reverser.
9. startup switching control according to claim 6, is characterized in that, described logic gate assembly selects cue according to described latch level signal to described CPU output chip; Wherein, when described latch level signal is inactive level, described is selected cue to be set to the memory-aided level state of the described master of expression; When described latch level signal or described second indicator signal are significant level, described is selected cue to be set to the level state representing described shelf storage.
10. startup switching control according to claim 9, is characterized in that, it is invalid that one of them of described first indicator signal and described second indicator signal is set to by force significant level by described CPU further, another is set to by force by described CPU.
11. startup switching controls according to claim 9, is characterized in that, described logic gate assembly controls described first chip selection signal and described second chip selection signal according to a chip enable signal further; Wherein, when described chip enable signal is invalid, it is invalid that described first chip selection signal and described second chip selection signal are all set to by force.
12. startup switching controls according to claim 11, it is characterized in that, the significant level of described latch level signal and described second indicator signal is high level, inactive level is low level, described chip enable signal and described first chip selection signal and described second chip selection signal significant level is low level, inactive level is high level;
Described logic gate assembly comprises first or door, second or door, the 3rd or door and the 3rd reverser;
Described first or Men mono-road input end receives described latch level signal, another road input end receives described second indicator signal, described first or the output terminal of door produce described and select cue;
Described second or Men mono-road input end connected by described 3rd reverser and receive described chip enable signal from described first or the output terminal of door, another road input end, described second or the output terminal of door produce described second chip selection signal;
Described 3rd or Men mono-road input end connect and receive described chip enable signal from described first or the output terminal of door, another road input end, the described 3rd or the output terminal of door produce described first chip selection signal.
13. startup switching controls according to claim 6, is characterized in that, described is selected cue to be GPIO signal.
14. startup switching controls according to claim 1,6 or 8, it is characterized in that, described first indicator signal is GPIO signal.
15. startup switching controls according to claim 9 or 12, it is characterized in that, described second indicator signal is GPIO signal.
16. 1 kinds, based on the startup method for handover control of active and standby storer, is characterized in that, utilize the loading of the startup switching control control CPU as described in claim 1,2,3 or 6 between primary storer and shelf storage to start and switch.
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| CN1639672A (en) * | 2002-03-28 | 2005-07-13 | 高级模拟技术有限公司 | Single wire serial interface |
| CN1920879A (en) * | 2005-07-05 | 2007-02-28 | 英特尔公司 | Identifying and accessing individual memory devices in a memory channel |
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| CN1639672A (en) * | 2002-03-28 | 2005-07-13 | 高级模拟技术有限公司 | Single wire serial interface |
| CN1920879A (en) * | 2005-07-05 | 2007-02-28 | 英特尔公司 | Identifying and accessing individual memory devices in a memory channel |
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