CN103378137A - 带有凹口的栅电极及其形成方法 - Google Patents
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Abstract
一种器件包括半导体衬底,和从该半导体衬底的顶面延伸到半导体衬底内的器件隔离(DI)区。栅极电介质设置在半导体衬底的有源区上方,其中栅极电介质在DI区上方延伸。栅电极设置在栅极电介质上方,其中该栅电极的凹口与该DI区的一部分重叠。本发明提供带有凹口的栅电极及其形成方法。
Description
本申请要求于2012年4月24日提交的美国临时专利申请序列号为61/637,701,名称为“带有凹口的栅电极及其形成方法”的优先权,其全部内容结合于此作为参考。
技术领域
本发明涉及半导体器件及其形成方法,具体而言,涉及栅电极及其形成方法。
背景技术
在集成电路制造业中,集成电路器件的尺寸按比例大幅地减小。例如,互补金属氧化物半导体(CMOS)图像传感器(CIS)芯片的像素尺寸越来越小。相应地,对DC和CIS芯片的噪音性能的要求也越来越严格。因此,通过阱注入形成的器件隔离区(DI)替代传统的浅沟槽隔离(STI)区,用来分隔器件。相比STI区,使用注入形成的DI区消除了形成STI区对硅表面造成的损坏。
DI区的形成是通过将杂质注入衬底的部分,该部分围绕着被隔离的集成电路器件的有源区。被注入的杂质与其中形成器件的阱区具有相同的导电类型。然而,很难控制集成电路器件的部件与DI区重叠的准确性。例如,很难控制DI区和上覆的栅电极之间的重叠的准确性。在栅电极偏离DI区的情况下,栅电极可能并不能够充分地分隔在DI区形成的MOS器件的源极区和漏极区之间的沟道。漏电流可能在源极区和漏极区之间产生。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种器件,包括:半导体衬底,具有有源区;器件隔离(DI)区,围绕所述有源区并从所述半导体衬底的顶面延伸至所述半导体衬底内;栅级电介质,位于所述有源区上方并在所述DI区上方延伸;以及栅电极,位于所述栅极电介质上方,所述栅电极具有与所述DI区的第一部分重叠的第一凹口。
在上述器件中,其中,所述第一凹口的边缘与所述DI区的边缘基本上对准,所述DI区的边缘接触所述半导体衬底的有源区。
在上述器件中,其中,所述栅电极包括与所述DI区的第一部分重叠的第一端,所述第一凹口设置在所述栅电极的第一端。
在上述器件中,其中,所述栅电极包括与所述DI区的第一部分重叠的第一端,所述第一凹口设置在所述栅电极的第一端,其中,所述栅电极还包括:第二端,所述第二端与所述DI区的第二部分重叠,其中所述DI区的第一部分和第二部分接触有源区的相对侧壁;以及第二凹口,所述第二凹口设置在所述栅电极的第二端。
在上述器件中,其中,所述栅电极还包括与所述DI区重叠的第二凹口,所述栅电极还包括位于所述第二凹口相对面上的部分。
在上述器件中,其中,所述栅电极包含在金属氧化物半导体(MOS)器件中,其中所述DI区与MOS器件的源极和漏极区具有相反的导电类型。
在上述器件中,其中,所述DI区包括所述半导体衬底的掺杂p型或n型杂质的部分。
根据本发明的另一方面,还提供了一种器件,包括:半导体衬底,具有有源区;器件隔离(DI)区,围绕所述半导体衬底中的有源区,其中所述DI区包括所述半导体衬底的掺杂p型或n型杂质的部分;以及金属氧化物半导体(MOS)器件,其中包括:栅极电介质,位于所述有源区上方并与所述DI区的第一部分和第二部分重叠,其中所述DI区的第一部分和第二部分设置在所述有源区的相对面上;以及栅电极,位于所述栅极电介质上方,其中所述栅电极包括与所述DI区的第一部分重叠的第一端,和位于所述栅电极的第一端的第一凹口。
在上述器件中,其中,所述栅电极包括:第一顶面;第二顶面,低于所述第一顶面,所述第二顶面延伸至所述栅电极的第一端;以及连接所述第一顶面和所述第二顶面的侧壁,其中所述第一顶面、所述第二顶面和所述侧壁形成台阶。
在上述器件中,其中,所述栅电极包括:第一顶面;第二顶面,低于所述第一顶面,所述第二顶面延伸至所述栅电极的第一端;以及连接所述第一顶面和所述第二顶面的侧壁,其中所述第一顶面、所述第二顶面和所述侧壁形成台阶,其中,所述第一顶面和所述第二顶面基本上相互平行。
在上述器件中,其中,所述DI区的第一部分包括与所述有源区接触的侧壁,其中所述侧壁与所述第一凹口的边缘基本上对准。
在上述器件中,其中,所述栅电极包括与所述DI区的第二部分重叠的第二凹口,其中所述DI区的第二部分包括与所述有源区接触并且基本上与所述第二凹口的边缘对准的侧壁。
在上述器件中,其中,所述第一凹口的深度大于所述栅电极的厚度的约5%。
根据本发明的又一方面,还提供了一种方法,该方法包括:在半导体衬底上方形成栅电极层;在所述栅电极层上方形成硬掩模;使所述硬掩模图案化以在所述硬掩模中形成开口;通过所述开口蚀刻所述栅电极层以在所述栅电极层中形成凹口;注入杂质,其中所述杂质穿透所述栅电极层位于所述凹口下面的部分,从而在所述半导体衬底中形成注入器件隔离(DI)区;以及蚀刻所述栅电极层从而形成金属氧化物半导体(MOS)器件的栅电极,蚀刻步骤完成后所述凹口的一部分与所述栅电极一起保留。
在上述方法中,其中,所述凹口包括面对面的第一边缘和第二边缘,蚀刻步骤完成后,去除所述第一边缘,保留所述第二边缘。
在上述方法中,还包括:在凹口形成之后和注入所述杂质之前,在所述硬掩模上方形成另外的硬掩模;以及在注入所述杂质的步骤完成后,去除所述硬掩模和所述另外的硬掩模。
在上述方法中,其中,蚀刻所述栅电极层的步骤通过将所述凹口用作对准标记来实施。
在上述方法中,还包括:形成所述MOS器件的源极区和漏极区;以及形成分别与所述源极区和所述漏极区重叠的源极接触件和漏极接触件,其中形成所述源极接触件和所述漏极接触件的步骤通过将所述凹口用作对准标记来实施。
在上述方法中,其中,所述杂质的导电类型与所述MOS器件的源极/漏极区的导电类型相反。
在上述方法中,其中,图案化所述硬掩模的步骤和蚀刻所述栅电极层的步骤利用不同的蚀刻剂执行。
附图说明
为了更全面地理解实施例及其优势,现将结合附图所进行的描述作为参考,其中:
图1至图8c示出根据一些示例性实施例制造金属氧化物半导体器件的中间阶段的截面图和俯视图;
图9示出包含图8A-8C所示的MOS器件的互补金属氧化物半导体(CMOS)图像传感器(CIS)芯片的截面图;
图10示出示例性图像传感器和服务于图像传感器的相应晶体管的布局图;
图11示出图10所示的器件的电路图。
具体实施方式
在下面详细讨论本发明实施例的制造和使用。然而,应该理解,实施例提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅作说明之用,而不限制本发明的范围。
根据不同的示例性实施例,本公开提供一种形成注入的器件隔离(DI)区和处于邻近DI区的有源区的金属氧化物半导体(MOS)器件的方法。描述了形成注入DI区和MOS器件的中间阶段。讨论了本实施例的各种变化。在各个附图和示例性实施例中,相同的参考编号用于表示相同的元件。
参考图1,提供了包含衬底20的晶圆2。在一些实施例中,衬底20是块状硅衬底。在可选实施例中,衬底20由其他半导体材料形成,如碳化硅、硅锗、III-V族化合物半导体材料等。衬底20也可以是绝缘体上硅衬底。在一些实施例中,阱区21形成在衬底20中,例如,通过将p型或n型的杂质注入衬底20中。
在衬底20上方形成栅极介电层24和栅电极层26。栅极介电层24可以包括氧化物、氮化物、氮氧化物、碳化物以及它们的组合和/或它们的多层。栅电极层26具有导电性,可以由多晶硅形成。可选地,栅电极层26可以由其他导电材料如金属、金属硅化物、金属氮化物和它们的组合形成。
参考图2,在栅电极层26上方形成硬掩模28。在一些实施例中,硬掩模28包括氮化硅。在可选的实施例中,硬掩模28由其他介电材料如氮氧化物(SiON)、碳化硅或氧化硅形成。接下来,如图3A和3B所示,分别是硬掩模28图案化形成开口30的截面图和俯视图。开口30,尽管在图3A中看起来像分离的开口,但可以是连续开口30(图3B)的一部分。在一些实施例中,如图3B所示,开口30形成完整的环形。在可选的实施例中,取决于被隔离的器件的形状,开口30具有其他布局和形状。
在形成开口30之后,进一步实施蚀刻步骤以使开口30延伸到栅电极层26内,从而在栅电极层26内形成凹口31。可以使用相同的蚀刻剂或不同的蚀刻剂来实施开口30的形成和凹口31的形成。例如,可使用四氟化碳作为蚀刻剂来实施开口30的蚀刻,可使用氯作为蚀刻剂来实施栅电极层26的蚀刻。凹口31的深度D1可以大于约50埃,或大于约150埃。例如深度D1也可以介于约50埃到约950埃之间。凹口31的深度D1也足够大从而使得凹口31可被清晰地辨认,在随后的工序中可以被用作对准标记。根据一些实施例,深度D1和栅电极层26的厚度T1的比值D1/T1可以介于约0.05到0.95之间。比值D1/T1也可以介于约0.2到0.8之间。如图3A和图3B所示,当开口30形成完整的环形时,凹口31也形成完整的环形。
接下来,如图4A和图4B所示,在衬底20中形成注入DI区32。因此,可以用来形成MOS器件的有源区33被注入DI区32围绕。利用对于被注入的杂质来说足够穿透位于凹口31下方的栅电极层26部分和栅极介电层24部分,而不够穿透硬掩模28和下面的栅电极层26部分的能级实施注入(用箭头表示)。在一些实施例中,被注入的杂质是p型杂质,如包含硼、铟等的p型杂质。在可选的实施例中,被注入的杂质是n型杂质,如包含磷、砷、锑等的n-型杂质。注入DI区32的导电类型也与阱区21的导电类型相同。
在图4A中,通过硬掩模28中的凹口31执行形成注入DI区32的注入。在可选实施例中,如图4B所示,另外的硬掩模29形成于硬掩模28上方并填充在凹口31内。凹口31的未填充部分称为凹口31’。由于硬掩模29的形成,凹口31’的宽度W2小于凹口31的宽度W1(仍参考图4A)。硬掩模29可以形成为共形层,因此位于开口30的侧壁上的硬掩模29的厚度基本上等于位于硬掩模28的顶面上的硬掩模29的厚度。在一些实施例中,硬掩模28与硬掩模29可以由相同的材料形成。可选地,硬掩模29和硬掩模28包括不同的材料。由于凹口31’具有比凹口31的宽度W1减小的宽度W2,图4B中注入DI区32的宽度W4减小为小于图4A中注入DI区32的宽度W3。由于硬掩模29的形成,DI区32占有的芯片面积也相应减小。
图5A和5B分别是去除掩模28(和掩模29,若有的话)后晶圆2的截面图和俯视图。图5B示出凹口31(在示出的实施例中形成环形)叠盖注入DI区32,该注入DI区32围绕有源区33。凹口31的边缘也基本上与DI区32的边缘对准。
图6中,形成光刻胶34并图案化。图案化的光刻胶34包括边缘34A和34B。边缘34A和34B之一或两者都与凹口31对准。凹口31是可辨认的,可以用作找到有源区33的边界的对准标记。因此,凹口31可以用作对准标记来使光刻胶34的边缘34A和34B与下面的有源区33和注入DI区32精确对准。凹口31的一部分,例如所示的左凹口31的右半部分被光刻胶34覆盖,而左凹口31的其余部分(如所示的左凹口31的左半部分)未被光刻胶34覆盖。
然后实施图案化,去除栅电极层26中未被光刻胶34覆盖的部分,从而形成栅电极126。所产生的结构如图7A和图7B中所示。返回参考图6,每个凹口31包括两个面对面的边缘31A和31B。在一些实施例中,如图7A所示,边缘31A随着栅电极层26的相应部分被去除,边缘31B在蚀刻步骤后保留。栅极介电层24位于栅电极层26被去除的部分下方的部分在这时可以被去除,也可以不去除。在对栅电极层26图案化后,每个凹口31还包括由顶面26A、低于顶面26A的顶面26B和边缘31B形成的台阶。顶面26A和26B可以基本上是平直的,也可以相互平行。在一些实施例中,顶面26B延伸到栅电极126的端126C。边缘31可以基本上与相应的注入DI区32的侧壁32A对准,侧壁32A与有源区33相接触。
图7B是图7A的俯视图,其中图7A中的截面图是从图7B中的平面切割线7A-7A处获得的。在一些实施例中,如图7B所示,凹口31形成在栅电极126的相对端126C处。在可选的实施例中,如图7C中的虚线所示,其中一个凹口31形成在栅电极126的一个端126C处(图7C中的上端),而栅电极126延伸超出另一凹口31(也标记为31”)。因此,栅电极126包括位于凹口31”相对侧的部分。
图8A、8B、8C示出形成MOS器件100的剩余部分的截面图和俯视图。图8A和8B分别从图8C中的平面切割线8A-8A和8B-8B处获得。参考图8A,MOS器件100的剩余部分包括栅极间隔件38、源极和漏极延伸区40、源极和漏极区42、源极和漏极硅化区44、栅极硅化区45以及接触塞46。在形成MOS器件100的这些部件时,图7A至图7C中的凹口31也可以用作对准标记。如图8B所示,由于凹口31的存在,栅极硅化区45不是平坦的,而形成一个台阶(或两个台阶),每一个台阶都包括高部、低部和侧壁部分。源极和漏极区42可以与注入DI区32邻接,且具有与注入DI区32相反的导电类型。例如,当注入DI区和阱区21是p型时,源极和漏极区42是n型。相反,当注入DI区32和阱区21是n型时,源极和漏极区42是p型。
在实施例中,通过在栅电极层中形成凹口,提高了集成电路制造工艺中不同部件覆盖(对准)的准确性。凹口可以用来形成小间距的器件。例如,图9示出包含在晶圆2中的背面照明(BSI)传感器芯片200。MOS器件100和注入DI区32形成BSI图像传感器芯片200中的逻辑电路的一部分。可以由光电二极管形成的图像传感器50形成在衬底20的前表面。位于BSI图像传感器芯片200(晶圆2的一部分)的背面上的是滤色镜52和微透镜54。光从BSI传感器芯片200的背面穿过到达图像传感器50。BSI传感器芯片200与MOS器件100的元件覆盖时需要有很高的准确性,因此可以使用该实施例。
图10示出示例性图像传感器50的布局图,可以是光电二极管(PD)。传输栅极晶体管TX和复位晶体管RST与图像传感器50连接。源随器SF邻近图像传感器50形成。DI区32邻接传输栅极晶体管TX和复位晶体管RST形成,且可以围绕源随器SF。图8A至图8C中所示的MOS器件100可以是传输栅极晶体管TX、复位晶体管RST和源随器SF中的任何一个。图11示出图10中的器件的电路图。
在该实施例中,形成注入DI区,相比传统的浅沟槽隔离(STI)区,该DI区的形成对衬底20(图1)的表面的损坏较小。由于在栅电极内形成凹口,凹口在随后的步骤中可以被用作对准标记。这可提高工艺控制中的准确性。例如,在图案化栅电极时,可提高准确性,栅电极可以可靠地在DI区上延伸,因此消除了源极区-漏极区泄漏。通过使用图4B中的硬掩模再沉积,DI区可以占有减小的芯片面积。因此增加了图像传感器的最大阱容。
根据一些实施例,一种器件包括半导体衬底和从半导体衬底的顶面延伸至半导体衬底内的DI区。栅极电介质设置在半导体衬底的有源区上方,其中栅极电介质在DI区上方延伸。栅电极设置在栅极电介质上方,其中栅电极的凹口与DI区的一部分重叠。
根据其他的实施例,一种器件包括半导体衬底和围绕半导体衬底的有源区的DI区。该DI区包括掺杂p型或n型杂质的半导体衬底的一部分。MOS器件包括位于有源区上方并且与DI区的第一部分和第二部分重叠的栅极电介质。该DI区的第一部分和第二部分设置在有源区的相对侧上。栅电极设置在栅极电介质上方。该栅电极具有与该DI区的第一部分重叠的端和位于该栅电极端的凹口。
根据又一其他的实施例,一种方法包括在半导体衬底上方形成栅电极层,在栅电极上方形成硬掩模,对硬掩模图案化从而在硬掩模中形成开口,通过开口蚀刻栅电极层从而在栅电极层中形成凹口。然后注入杂质,其中该杂质穿透栅电极层位于凹口下面的部分从而在半导体衬底中形成注入DI区。栅电极层被蚀刻形成MOS器件的栅电极,蚀刻步骤之后凹口的一部分与栅电极一起保留。
尽管已经详细地描述了本发明以及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、器件、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、器件、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、器件、方法或步骤的范围内。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。
Claims (10)
1.一种器件,包括:
半导体衬底,具有有源区;
器件隔离(DI)区,围绕所述有源区并从所述半导体衬底的顶面延伸至所述半导体衬底内;
栅级电介质,位于所述有源区上方并在所述DI区上方延伸;以及
栅电极,位于所述栅极电介质上方,所述栅电极具有与所述DI区的第一部分重叠的第一凹口。
2.根据权利要求1所述的器件,其中,所述第一凹口的边缘与所述DI区的边缘基本上对准,所述DI区的边缘接触所述半导体衬底的有源区。
3.根据权利要求1所述的器件,其中,所述栅电极包括与所述DI区的第一部分重叠的第一端,所述第一凹口设置在所述栅电极的第一端。
4.根据权利要求3所述的器件,其中,所述栅电极还包括:
第二端,所述第二端与所述DI区的第二部分重叠,其中所述DI区的第一部分和第二部分接触有源区的相对侧壁;以及
第二凹口,所述第二凹口设置在所述栅电极的第二端。
5.一种器件,包括:
半导体衬底,具有有源区;
器件隔离(DI)区,围绕所述半导体衬底中的有源区,其中所述DI区包括所述半导体衬底的掺杂p型或n型杂质的部分;以及
金属氧化物半导体(MOS)器件,其中包括:
栅极电介质,位于所述有源区上方并与所述DI区的第一部分和第二部分重叠,其中所述DI区的第一部分和第二部分设置在所述有源区的相对面上;以及
栅电极,位于所述栅极电介质上方,其中所述栅电极包括与所述DI区的第一部分重叠的第一端,和位于所述栅电极的第一端的第一凹口。
6.根据权利要求5所述的器件,其中,所述栅电极包括:
第一顶面;
第二顶面,低于所述第一顶面,所述第二顶面延伸至所述栅电极的第一端;以及
连接所述第一顶面和所述第二顶面的侧壁,其中所述第一顶面、所述第二顶面和所述侧壁形成台阶。
7.根据权利要求6所述的器件,其中,所述第一顶面和所述第二顶面基本上相互平行。
8.一种方法,该方法包括:
在半导体衬底上方形成栅电极层;
在所述栅电极层上方形成硬掩模;
使所述硬掩模图案化以在所述硬掩模中形成开口;
通过所述开口蚀刻所述栅电极层以在所述栅电极层中形成凹口;
注入杂质,其中所述杂质穿透所述栅电极层位于所述凹口下面的部分,从而在所述半导体衬底中形成注入器件隔离(DI)区;以及
蚀刻所述栅电极层从而形成金属氧化物半导体(MOS)器件的栅电极,蚀刻步骤完成后所述凹口的一部分与所述栅电极一起保留。
9.根据权利要求8所述的方法,其中,所述凹口包括面对面的第一边缘和第二边缘,蚀刻步骤完成后,去除所述第一边缘,保留所述第二边缘。
10.根据权利要求8所述的方法,还包括:
在凹口形成之后和注入所述杂质之前,在所述硬掩模上方形成另外的硬掩模;以及
在注入所述杂质的步骤完成后,去除所述硬掩模和所述另外的硬掩模。
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US9263272B2 (en) | 2012-04-24 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate electrodes with notches and methods for forming the same |
WO2014002332A1 (ja) * | 2012-06-27 | 2014-01-03 | パナソニック株式会社 | 固体撮像装置 |
US9355888B2 (en) | 2012-10-01 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implant isolated devices and method for forming the same |
US9673245B2 (en) * | 2012-10-01 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Implant isolated devices and method for forming the same |
US9412859B2 (en) * | 2013-03-11 | 2016-08-09 | Globalfoundries Inc. | Contact geometry having a gate silicon length decoupled from a transistor length |
US9728637B2 (en) * | 2013-11-14 | 2017-08-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanism for forming semiconductor device with gate |
US10468490B2 (en) | 2017-11-09 | 2019-11-05 | Nanya Technology Corporation | Transistor device and semiconductor layout structure |
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US20180190494A1 (en) | 2018-07-05 |
US11456176B2 (en) | 2022-09-27 |
CN103378137B (zh) | 2016-01-13 |
US10510542B2 (en) | 2019-12-17 |
US20160163550A1 (en) | 2016-06-09 |
US20220359205A1 (en) | 2022-11-10 |
US20130277719A1 (en) | 2013-10-24 |
US12009214B2 (en) | 2024-06-11 |
US9905426B2 (en) | 2018-02-27 |
US20200083049A1 (en) | 2020-03-12 |
US9263272B2 (en) | 2016-02-16 |
KR101436215B1 (ko) | 2014-09-01 |
TW201344916A (zh) | 2013-11-01 |
TWI493717B (zh) | 2015-07-21 |
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