CN103377881A - 制造导线的方法 - Google Patents
制造导线的方法 Download PDFInfo
- Publication number
- CN103377881A CN103377881A CN2013101415784A CN201310141578A CN103377881A CN 103377881 A CN103377881 A CN 103377881A CN 2013101415784 A CN2013101415784 A CN 2013101415784A CN 201310141578 A CN201310141578 A CN 201310141578A CN 103377881 A CN103377881 A CN 103377881A
- Authority
- CN
- China
- Prior art keywords
- groove
- dopant
- dielectric layer
- wire
- broadened
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000002019 doping agent Substances 0.000 claims description 54
- 238000004804 winding Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 33
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 8
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000012071 phase Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910021389 graphene Inorganic materials 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 150000003949 imides Chemical class 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910001145 Ferrotungsten Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- NNIPDXPTJYIMKW-UHFFFAOYSA-N iron tin Chemical compound [Fe].[Sn] NNIPDXPTJYIMKW-UHFFFAOYSA-N 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明公开了制造导线的方法,更具体地讲,公开了制造半导体组件的圆形导线的方法。在该方法中,提供部分完成的半导体组件。所述部分完成的半导体组件具有底面和顶面,所述顶面在垂直方向上与所述底面远距离间隔。还提供蚀刻剂。在所述顶面上设置介电层。所述介电层具有当利用所述蚀刻剂蚀刻时呈现不同蚀刻速率的至少两个不同的区域。随后,在所述介电层中形成沟槽,使得所述沟槽横穿所述不同的区域中的每个区域。然后,通过利用所述蚀刻剂以不同的蚀刻速率蚀刻沟槽来加宽该沟槽。通过用导电材料填充加宽的沟槽,形成导线。
Description
技术领域
本发明实施方案涉及制造半导体组件的圆形导线(rounded conductorline)的方法。
背景技术
在许多半导体组件中,在组件操作期间高电压施加于组件的导线之间。由于如此高的电压可能导致电气击穿,因此,需要改良。
发明内容
发现通过至少在各个导线中至少一个导线的某些区域中避免尖锐外缘、顶点等,在各个导线之间介电质中出现的电场可被减少。因此,本发明的一个方面涉及制造半导体组件的圆形导线的方法。在该方法中,提供部分完成的半导体组件。所述部分完成的半导体组件具有底面和顶面,所述顶面在垂直方向上与所述底面远离地间隔。还提供蚀刻剂。在所述顶面上设置介电层。所述介电层具有当利用所述蚀刻剂蚀刻时呈现不同蚀刻速率的至少两个不同的区域。随后,在所述介电层中形成沟槽,使得所述沟槽横穿(intersect)所述不同的区域中的每个区。然后,通过利用所述蚀刻剂在不同蚀刻速率下蚀刻所述沟槽来加宽所述沟槽。任何各向同性湿式蚀刻和/或各问同性干式蚀刻方法可用作上述蚀刻方法。例如,合适的各向同性干式蚀刻技术有化学干式蚀刻(CDE)。在此上下文中,“各向同性”是指如果蚀刻材料为各向同性,那么蚀刻速率为各问同性。即,在“各向同性蚀刻方法”中,这样的方法为各向同性。然而,即使各向同性蚀刻方法用于蚀刻各向异性材料,蚀刻速率也通常为各向异性。通过利用导电材料填充被加宽的沟槽,形成导线。
根据本发明的其他方面,该导线可为半导体组件的无芯变压器的线圈的外绕组。
附图说明
参考以下附图和描述可更好地理解本发明。图中组件并不一定按照比例绘制,而是重点放在说明本发明原理。此外,图中,相同参考数字指定相应的部分。附图中:
图1为半导体器件的无芯变压器线圈的透视图;
图2为图1无芯变压器线圈的截面图;
图3A至图3H示出了制造半导体芯片的圆形导线的不同步骤;
图4A示出了半导体芯片的圆形导线的又一实例;
图4B示出了移除掩膜层之后的图4A的配置;
图5为通过半导体芯片的无芯变压器部分的截面图,其中变压器线圈的绕组为圆形的;
图6为通过半导体芯片的无芯变压器部分的截面图,该无芯变压器部分与图5无芯变压器部分不同之处在于屏蔽环在截面中也为圆形的;
图7A至图7F示出了制造半导体芯片的圆形导线的又一方法的不同步骤;
图8A和图8B示出了制造不同掺杂的介电层的方法的不同步骤;
图9为无芯变压器线圈的截面图,该无芯变压器线圈与图2的无芯变压器线圈不同之处在于顶线圈的所有螺旋形绕组为至少部分圆形;以及
图10为在半导体本体中实现且具有圆形电极的电容器的截面图。
具体实施方式
在以下具体描述中,参考附图,附图构成本发明一部分,且通过示出可实现本发明的特定实施方式来示出附图。在这方面,参考所描述的附图中的方位来使用诸如“顶”、“底”、“前”、“后”、“开头”、“结尾”等方向术语。因为实施方式的组件可定位于许多不同方位中,所以方向术语是用于说明目的,而不是限制性的。应当理解,可利用其它实施方式,且在不脱离本发明范围的情况下,可作出结构或者逻辑上的改变。以下具体实施方式因此不应视为限制性的,且本发明范围由所附权利要求界定。应当理解,除非另有明确说明,本文中描述的各种示例性实施方式的特征可相互组合。
现在参考图1和图2,示出的线圈为半导体组件1的无芯变压器的41、42、51、52、61、62。为了清晰起见,省略半导体组件1的其它部分。图2示出包括无芯变压器的半导体组件1的一部分,无芯变压器被嵌入半导体组件1的半导体本体10中。
一般地,无芯变压器需要至少两个线圈。一个线圈作为发射器,另一个线圈作为接收器。在图1实施方式中,有两个发射器线圈41、42和四个接收器线圈51、52、61、62。每个线圈41、42、51、52、61、62可具有扁平螺旋形形式,该形式具有一个或者更多绕组。线圈41、51、61具有共同线圈轴91,线圈42、52、62具有共同线圈轴92。经由接触端子45、46、47(例如,粘结盘(bond pad)或者焊垫)供应到发射器线圈41或者42的电流信号在分别在接收器线圈51、61和52、62中感生电流,接收器线圈51、61和52、62与各自的发射器线圈41、42电绝缘。为了抑制杂散辐射,可任选连接到接地电位(GND)的环形屏蔽环30包围发射器线圈41、42。
在半导体器件的操作期间,在接收器线圈51、52、61、62的电位与GND之间之差的绝对值通常不超过几伏特或者几十伏特,而在发射器线圈41、42的电位与GND之间之差可能超过几百伏特、几千伏特或者甚至几万伏特。因此,在发射器线圈41、42的电位与屏蔽环30之间的差也可能超过几百伏特、几千伏特或者甚至几万伏特。在常规配置中,电气击穿大部分发生在发射器线圈41、42与屏蔽环30之间的半导体组件1的顶面11处或者顶面11附近。因此,如果至少发射器线圈41和42的最外面绕组411和421至少在它们位于最接近屏蔽环30的部分(即,在它们分别背向各自的线圈轴91和92的部分)分别具有圆形截面是有利的。
图2示出在平行于垂直方向v且也平行于线圈轴91和92行进的截面平面中通过图1的无芯变压器的截面。垂直方向v垂直于半导体本体10的顶面(top side)l1且垂直于底面(bottom side)l2行进。关于这一点,顶面11和底面12被视为基本上平坦的。图2中示意性示出了半导体组件1的边界线。半导体组件1的半导体本体10可由诸如硅、锗、碳化硅、砷化镓等任意半导体材料形成,且可包括p掺杂半导体区、n掺杂半导体区、介电层(诸如硅氧化物层、氮化物层或者酰亚胺层)和导电层以及由金属和/或多晶半导体材料制成的区域。任选地,半导体组件1可包括有源半导体器件(诸如IGBT(绝缘栅极双极晶体管)、MOSFET(金属氧化物半导体场效晶体管)、J-FET(结型场效晶体管)、晶闸管、二极管)中的一个或者任何组合。半导体组件1可替代地包括或者还包括无源器件(诸如电阻器、电容器、电感器等)中一个或者任何组合。特别是,这样的器件可为具有控制电极(诸如栅极或者基极)的可控半导体器件。线圈41、42、51、52、61、62中至少一个可直接(即,仅经由导电线)或者间接(即,经由有源和/或无源元件,例如用于驱动可控半导体器件的驱动器电路)电气连接到这样的控制电极。
从图2可以看出,线圈41具有螺旋形绕组411、412、413和414。相应地,线圈42具有螺旋形绕组421、422、423和424,线圈51具有螺旋形绕组511、512、513和514,线圈52具有螺旋形绕组521、522、523和524,线圈61具有螺旋形绕组611、612、613和614,线圈62具有螺旋形绕组621、622、623和624。上线圈41、42(即,设置为接近顶面11的线圈)由屏蔽环30包围,屏蔽环30可任选连接到GND电位。屏蔽环30还可任选在负垂直方向v上尽可能远地延伸到接近底线圈51、52、61、62的水平。为了实现屏蔽效果,屏蔽环30可电气连接到接地电位GND。
如也在图2中示意性示出那样,发射线圈41、42中至少一个的外绕组411、421具有圆形截面,即,在分别平行于相应线圈轴91和92且垂直于相应绕组411、421的行进方向的至少一个截面平面中,外绕组411、421的表面40为至少部分圆形。例如,在所述截面平面中,相应表面40可在至少一个点Pl、P2中具有至少0.4μm和/或小于等于3.2μm(例如约1.6μm)的曲率半径。
接着,将参考图3A至图3H通过以图1和图2中发射线圈41的外绕组411为例说明制造在截面中至少部分圆形的导线的器件的方法。起点为具有底面12和顶面11'的部分完成的半导体本体10,顶面11'在垂直方向v上与底面12远离地间隔。在图2中,垂直于垂直方向v行进的前顶面11'的平面由虚线表示。
如图3B所示,图3B为图3A中由虚线表示的组件1的放大部分1",将介电层2设置于顶面11'上。在所示实例中,参考数字11'涉及半导体本体10的顶面。一般地,参考数字11'为部分完成的半导体组件1的顶面,即,顶面也可由单独的或者任何组合的介电材料、导电材料、掺杂半导体材料、末掺杂半导体材料、金属、多晶半导体材料形成或者包括所述材料。
介电层2具有不同子层21、22、23、24、25,其中直接相邻的层在用相同蚀刻剂蚀刻时呈现不同的蚀刻速率。为此,子层21、22、23、24、25中直接相邻的子层可由对于选定蚀刻剂呈现不同蚀刻速率的不同材料成分制成,随后将利用选定蚀刻剂蚀刻介电层2以加宽介电层2中的沟槽。在此上下文中,如果两个相邻子层由相同基材形成但被不同地掺杂,那么它们也被视为由不同材料成分制成。从这个意义上说,不同地掺杂包括"利用相同掺杂剂掺杂但掺杂剂浓度不同"和/或"利用不同掺杂剂掺杂"。也包括这样的组合:直接相邻子层中的一个子层由基材组成,因此末掺杂,而直接相邻子层中的另一个具有相同基材但掺杂有掺杂剂。在任何情况下,介电层2的材料在垂直方向v上呈现对于选定蚀刻剂的非恒定蚀刻速率。在本实施方式中,每个子层21、22、23、24、25在垂直方向v上具有至少100nm或者至少400nm和/或小于等于2μm的厚度。例如,所述厚度的可能范围为从100μm到2μm。然而,也可使用任何其它厚度。
在图3B所示的实施方式中,介电层2由例如硅氧化物的基材制成,基材掺杂有掺杂剂,例如磷(P)、硼(B)、银(Ag)、砷(As)、氩(Ar)或者它们组合,掺杂剂影响介电层2的湿式和/或干式蚀刻速率。在垂直方向v上,介电层2的掺杂剂具有非恒量浓度层次(nonconstant course ofconcentration)。因此,如果随后湿式和/或干式蚀刻介电层2,那么由于介电层2的各部分(section)具有不同掺杂剂浓度,所以即使这样的蚀刻方法为各向同性,在相同蚀刻处理期间也可实现不同蚀刻速率。
通过百先在顶面11'上沉积子层25,然后在子层25上沉积子层24,接着在子层24上沉积子层23,再在子层23上沉积子层22,最后在子层22上沉积子层21,可实现介电层2的制造。如图3B右侧上所示,子层21和25具有0%(重量)的掺杂剂浓度,子层22和24具有2%(重量)的掺杂剂浓度。子层23具有4%(重量)的掺杂剂浓度,4%(重量)的掺杂剂浓度为最大掺杂剂浓度。在这方面,1%(重量)是指1kg掺杂硅氧化物(SiO2)包括40g掺杂剂。在其它实施方式中,最大掺杂剂浓度可为例如大于4%(重量),例如至少8%(重量)。
在垂直方向v上,最大掺杂剂浓度可延伸厚度dcmax,dcmax可为例如至少100nm。此外,最大掺杂剂浓度可与前顶面11'和介电层2的背离底面(参见图2)的面都远离地间隔。
如果对于介电层2的所有子层21、22、23、24、25使用相同基材,例如硅氧化物,那么可使用从气相沉积介电层2的气相沉积处理在顶面11'上连续沉积所有子层21、22、23、24、25的基材,其中在沉积处理期间改变气相中的掺杂剂浓度,使得所得介电层2呈现上述的子层结构。与本实施方式不同,呈现不同蚀刻速率的相邻子层数可为小于或者大于5。一般地,介电层2具有至少两个子层。然而,随着子层数21、22、23、24、25不断增加,待制造导线的圆度可得到改良。
现在参考图3C至图3E,将蚀刻掩膜层31(例如硅氮化物层或者另一合适的层)设置于介电层2(图3C)上,然后例如光刻结构化以具有开口311,介电层2暴露于开口311中(图3D)。然后,如图3E所示,使用结构化蚀刻掩膜层31在开口311之下蚀刻沟槽13。例如,沟槽13可在垂直方向v上具有至少0.5μm或者至少3μm的深度。然而,沟槽13的最小深度可为低于或者高于所述值。
相应蚀刻处理可为干式蚀刻处理,例如各向异性等离子蚀刻处理,例如反应离子蚀刻(RIE)、深反应离子蚀刻(DRIE)或者高密度等离子蚀刻(HDP)。在图3E中,沟槽13的底部与顶面11'远离地间隔。然而,沟槽13也可穿透顶面11'达到半导体本体10中。如果待制造导线为螺旋形线圈,例如如上所述的无芯变压器的线圈,那么沟槽13的行进方向也可为螺旋形。然而,沟槽13以及沟槽13中的待制造导线也可采用任何其它行进形式。
在随后湿式和/或各向同性干式蚀刻处理中,将选定蚀刻剂引入到沟槽13中,使得利用液相或者气相蚀刻剂填充沟槽13,且蚀刻剂接触沟槽13的表面131(图3E)。合适湿蚀刻剂为例如氢氟酸(HF),或者氟化铵(NH4F)和氢氟酸(HF)的混合物,例如比例为30Vol%÷6Vol%。
在蚀刻处理期间,由于不同材料成分(这里:不同掺杂浓度),不同子层21、22、23、24、25中的相邻子层在不同蚀刻速率下蚀刻。不论通过不同子层21、22、23、24、25的不同掺杂剂浓度或者上述任何其它措施是否实现相邻子层21、22、23、24、25的不同蚀刻速率,图3E所示的沟槽13在湿式和/或干式蚀刻处理期间被加宽。图3F中示出加宽沟槽13。如图所示,可在结构化掩膜层31被设置于顶面11'上的情况下或者部分或者完全移除掩膜层31(未示出)的情况下进行湿式和/或干式蚀刻处理。如图3F所示,加宽沟槽13的表面在垂直于沟槽13的行进方向的截面平面中可具有沟槽13的表面的曲率半径R为至少0.4μm和/或小于等于3.2μm的一个或更多位置Sl、S1'。例如,在一些实施方式中,R可为约1.6μm。在沟槽13完成之后,阻挡层35(图3F)可任选被沉积于加宽沟槽13的表面上以覆盖沟槽13的整个表面。这样的阻挡层35避免导体材料扩散到半导体本体10中,导体材料将在随后步骤中被填充到沟槽13中。例如,铜可能对在半导体本体10中实现的电子半导体元件产生不利影响。因此,如果导体材料包括铜,并且如果半导体本体包括半导体元件,那么强烈建议提供阻挡层35。例如,防止铜和任何其它导电材料扩散的合适阻挡材料为钽(Ta)、钛(Ti)、钨(W)、氮化钽(TaN)、氮化钛(TiN)、氮化钨(WN)、钛钨(TiW)、氮化铁钨(TiWN)、氮化硅(SiN)或者它们组合。例如,合适的组合为具有钽(Ta)层和氮化钽(TaN)层的双层或者具有钛(Ti)层和氮化铁(TiN)层的双层。
如图3F所示,在垂直于行进方向(垂直于附图平面)的截面平面(附图平面)中,开口311具有最小宽度Wmin,且加宽沟槽13在开口311和底面12(图2)之间的区域中具有最大宽度Wmax,最大宽度Wmax大于最小宽度Wmin。换言之,由沟槽13和开口311形成的单元具有倒锥形。由此,最大宽度Wmax可大于(a)底面12(图2)和开口311之间的距离与(b)底面12和导线411之间的距离之间的差。
现在参考图3G,导线411形成于加宽沟槽13中。为此,利用导电材料填充加宽沟槽13,例如铜、铝、石墨、石墨烯或者分别包括上述材料和同素异形体中任何两个或者更多的混合物或者组合。如果导线411无需携带大电流,那么掺杂或者未掺杂多晶半导体材料也可用作导电材料。
可在结构化掩膜层31覆盖在介电质2上的情况下或者部分或者完全移除结构化掩膜层31的情况下进行填充加宽沟槽13。如果开口311仍然存在,那么导电材料可通过开口311引入到加宽沟槽13中。如图3G所示,那么加宽沟槽13可被装满溢出,使得导电材料形成覆盖在介电层2上面的导电层48,并且任选地,覆盖在结构化掩膜层31或其剩余部分上,如果在填充处理之前结构化掩膜层31末被移除或者未完全移除。
现在参考图3H,在填充处理之后的任选步骤中,例如通过研磨、抛光、精研等,该配置可在背向底面12的面(图3A)上平坦化。由此,导电层48(如果存在)可被部分或者完全移除。
完成导线411具有至少部分圆形的表面40。在表面40上至少一个点Pl、Pl'处,表面40在垂直于导线411的行进方向(行进方向垂直于附图平面行进)延伸的截面平面(这里:附图平面)中具有曲率半径R,由于任选的阻挡层35的厚度可被忽略,所以该曲率半径R可为在与参照图3F提到的曲率半径R相同的范围内。
根据图4A所示的又一实施方式,介电层2包括两个子层21和22。子层21由末掺杂基材制成,例如硅氧化物,子层22由相同基材制成,但额外掺杂有掺杂剂,例如磷(P)、硼(B)、银(Ag)、砷(As)、氩(Ar)或者这些掺杂剂中至少两种的组合。或者,第一子层21和第二子层22都可由掺杂有掺杂剂的基材制成,掺杂剂为例如磷(P)、硼(B)、银(Ag)、砷(As)、氩(Ar)或者这些掺杂剂中至少两种的组合,其中第一和第二子层21、22的掺杂使得当利用后面将用于加宽沟槽的相同蚀刻剂蚀刻时,第二子层22的蚀刻速率超过第一子层21的蚀刻速率。由于不同蚀刻速率,子层22的蚀刻速率大于子层21的蚀刻速率。通过首先如上参考图3D和图3E说明干式蚀刻沟槽到介电层2中,随后通过如上参考图3F说明湿式和/或干式蚀刻来加宽沟槽且任选用阻挡层35涂覆沟槽表面,以及通过如上参考图3G和图3H说明利用导电材料填充沟槽,制造出配置有导线411的加宽沟槽。
根据图4B所示的又一选项,已用于干式蚀刻处理的掩膜层31可部分或者完全移除。
图5示出半导体组件1的部分1'。所述部分1'对应于图2所示的部分1'。在制造无芯变压器的线圈的绕组411、412、413之前,部分完成的半导体组件具有顶面11'。在前顶面11'上,以与图4B导线411相同的方式制造线圈的绕组411。任选地,也如图5所示,可以与最外面绕组411相同的方式制造线圈的部分或全部的其它绕组412、413,以呈现至少部分圆形的表面。
线圈41(也参见图1和图2)由设置于沟槽中的导电屏蔽环30包围。这样的屏蔽环30可利用镶嵌(damascene)处理来制造,例如,通过利用各向异性干式蚀刻处理来制造沟槽,且通过随后利用导电材料来填充沟槽,导电材料也可为例如铜、铝、石墨、石墨烯或者分别包括上述材料和同素异形体中任何两个或更多的混合物或者组合。如果屏蔽环无需携带大电流,那么掺杂或者末掺杂多晶半导体材料也可用作导电材料。优选地,屏蔽环30由与绕组411、412、413使用的相同导电材料制成。然而,也可使用不同导电材料。任选地,可如以上参考图3F的说明以相同方式并使用相同材料,用阻挡层35涂覆沟槽表面。
在制造了包括绕组411、412、413的线圈41之后,器件可以任意方式进一步处理。在图5的实例中,硅氮化物层33、硅氧化物层72、含氢的硅氮化物层34和酰亚胺层73随后沉积于介电层2、绕组411、412、413和屏蔽环30上。
或者,如图6所示,截面至少部分圆形的屏蔽环30可使用与至少部分圆形的外绕组411相同的原理、步骤和材料来制造,特别是参见图3A至图3H、图4A和图4B,即,通过蚀刻沟槽,加宽沟槽,任选用阻挡层涂覆沟槽,以及通过用导电材料填充沟槽。在图6的配置中,沟槽包括导线411。
在以上参考图3B至图3H、图4A和图4B描述的实施方式中,从具有两个或更多子层21、22、23、24、25的介电层2开始已制造出至少部分圆形的导线411,其中当任何两个相邻子层21、22、23、24、25暴露于选定蚀刻剂时它们呈现不同蚀刻速率。
现在将参考图7A至图7F说明又一实施方式。从如参考图3A说明的配置开始,在顶面11'上制造图7A所示的介电层2。介电层2由例如硅氧化物的基材形成,基材掺杂有掺杂剂,例如磷(P)、硼(B)、银(Ag)、砷(As)、氩(Ar)或者它们组合,与以上参考图3B至图3H、图4A和图4B描述的实施方式不同,介电层2的掺杂分布图(doping proHle)不具有阶梯结构,而是在垂直方向v上连续、平滑变化。即,在介电层2内,介电层2的掺杂剂浓度为垂直方向v的可微函数。在垂直方向v上,掺杂剂浓度首先具有递增分支(increasing branch,递增部分),其中梯度cl'=dc(v)/dv大于零并达到至少lwt%/μm或者至少2wt%/μm的值。在通过最大掺杂剂浓度之后,掺杂剂浓度具有递减分支,其中梯度c2'=dc(v)/dv小于零并达到小于或等于-lwt%/μm或者甚至小于或等于-2wt%/μm的值。
随后,如上文参考图3C至图3H的描述执行相同的步骤。图3C、图3D、图3E、图3F和图3H的实施方式与分别对应图7B、图7C、图7D、图7E和图7F的实施方式的唯一区别在于各自的介电层2的不同结构。由于介电层2的掺杂剂浓度c的可微过程(differentiable course),沟槽13(图7E)的表面以及导线411的表面40分别比图3F和图3G所示的相应表面更平滑。
为了制造其中介电层2的掺杂剂浓度c为垂直方向v的可微函数的介电层2,可用包括一种或多种掺杂剂的气相将介电层2沉积于表面11'上,在所述气相中,在沉积处理期间适当地修正掺杂剂浓度以实现期望的掺杂剂分布图。
从图7F也可以看出,在垂直于沟槽13(参见图7E)的行进方向的截面平面(附图平面)中,对于沿着导线411的表面40的连续表面路径b40(由粗线表示)的任何点Pl、P2,导线411的曲率半径R可为至少0.4μm。任选地,对于连续表面路径的任何点Pl、P2,导线411的曲率半径R可为小于或者等于3.2μm。例如,对于连续表面路径的任何点Pl、P2,导线411的曲率半径R可为在从0.4μm到3.2μm的范围内。在垂直方向v上,连续表面路径可延伸至少100nm或者甚至至少0.8μm的距离d29。
又一替代方案是如图8A所示在表面11'上制造末掺杂或者均匀掺杂的介电层2'。然后,如图8B所示,一种或多种掺杂剂可被植入到介电层2'中。由于植入深度取决于植入掺杂剂的能量,所以可通过在植入处理期间以可微速率(粒子能量/时间)不断修正粒子能量简单地调整出期望的掺杂分布图。
然而,植入粒子也可用于制造具有基本上阶梯型掺杂剂浓度c(v)的配置,例如,如参考图3B说明的配置,图3B可用作参考图3B至图3H描述的方法中的起点。
当在常规无芯变压器的情况下,电气击穿主要发生在变压器线圈41和42的最外面绕组411和421中分别背向相应线圈41、42的底面12和线圈轴91、92(也参见图1和图2)的部分410上。因此,在本发明的任何实施方式中,至少最外面绕组411、421可在变压器线圈41和42的最外面绕组411、421中背向底面12和相应线圈41、42的线圈轴91、92的面的至少顶面部分410上为圆形。在该顶面部分410处,最外面绕组411、421可具有在上述范围内的曲率半径R。
线圈41和42的两个、更多或者所有绕组可以分别部分被圆形化或者如图9所示地完全被圆形化,而不是仅使无芯变压器线圈41和42的最外面绕组411、421分别圆形化。图9的配置与图2的配置相同,唯一不同之处在于线圈41的所有绕组411、412、413、414以及线圈42的所有绕组421、422、423、424在平行于垂直方向v且平行于相应线圈轴91和92的截面平面中分别具有如以上实例中描述的绕组411的圆形表面(roundedsurface)。
图10中示出了圆形导线71的又一实施方式。在这个实施方式中,导线71为电容器一部分,所述电容器由基本上垂直于附图平面延伸的片状平行导线(“导体板“)71和78形成。上导线71具有接触端子75,底导线78具有接触端子76。为了制造具有点P71的上导线71的表面70,点P71具有在上述范围内的曲率半径R,可使用参考至少部分圆形的导线411的制造实例描述的相同方法之一。也如图10所示,底导线78可以与上导线71相同或者相似的方式圆形化。然而,底导线78也可具有存在角度的截面。像无芯变压器一样,电容器71、78可用于将用于驱动可控半导体元件的电路与所述半导体元件的控制电极电去耦。这样的半导体元件可在与电容器71、78或者无芯变压器相同的半导体本体中或者在不同的半导体本体中实现。
为了便于描述,诸如“下面”、“之下”、“下”、“之上”、“上”等空间相对术语用于说明一个元件相对于第二元件的定位。除了图中所示不同定位外,这些术语也包括器件的其他不同定位。此外,诸如“第一”、“第二”等术语也用于描述各种元件、区域、部分等,且也并不是限制性的。类似的术语是指整个描述中的类似元件。
本文中使用的术语“具有”、“包括”、“包含”、“含有”等为开放式术语,表示存在所指出元件或者特征,但不排除另外的元件或者特征。除非上下文中另有明确指出,冠词“a”、“an”和“the”意在包括复数以及单数。
虽然已经详细描述了本发明实施方式及其优点,但是应当理解,在不脱离由所附权利要求界定的本发明精神和范围的情况下可作出各种改变、替换和变更。考虑到以上变化和应用范围,应当理解,本发明既不由以上描述也不由附图来限制。相反,本发明仅通过以下权利要求及其法律上的等同方案来限制。
Claims (26)
1.一种用于制造半导体组件的导线的方法,所述方法包括以下步骤:
提供具有底面和顶面的部分完成的半导体组件,所述顶面在垂直方向上与所述底面远离地间隔;
提供蚀刻剂;
在所述顶面上设置介电层,所述介电层具有在用所述蚀刻剂蚀刻时具有不同的蚀刻速率的至少两个不同的区域;
在所述介电层中形成沟槽,使得所述沟槽横穿所述至少两个不同的区域中的各个区域;
通过用所述蚀刻剂蚀刻所述沟槽使得以所述不同的蚀刻速率蚀刻所述至少两个不同的区域来加宽所述沟槽,;
通过用导电材料填充被加宽的沟槽来形成所述导线。
2.根据权利要求1所述的方法,其中,所述介电层包括用在所述垂直方向上具有非恒量浓度层次的至少一种掺杂剂掺杂的基材,其中如果被掺杂的基材用所述蚀刻剂蚀刻,则所述至少一种掺杂剂影响被掺杂的基材的蚀刻速率。
3.根据权利要求2所述的方法,其中:
所述至少两个不同的区域形成为子层;以及
所述子层的相邻子层中所述至少一种掺杂剂的非恒量浓度层次是不同的。
4.根据权利要求2所述的方法,其中,所述至少一种掺杂剂在所述垂直方向上具有至少1%(重量)/μm或者至少2%(原子)/μm的梯度。
5.根据权利要求2所述的方法,其中,所述至少一种掺杂剂在所述垂直方向上具有至少小于或等于-1%(重量)/μm或者小于或等于-2%(重量)/μm的梯度。
6.根据权利要求2所述的方法,其中,
在所述介电层内且沿着与所述垂直方向平行的线,所述至少一种掺杂剂包括最大掺杂剂浓度;
所述最大掺杂剂浓度的位置与所述顶面远离地间隔。
7.根据权利要求2所述的方法,其中,所述至少一种掺杂剂为磷(P)、硼(B)、银(Ag)、砷(As)、氩(Ar)中的一种。
8.根据权利要求1所述的方法,还包括以下步骤:
在所述顶面上设置掩膜层,所述掩膜层包括开口;
通过蚀刻在所述开口之下的所述介电层来形成所述沟槽,从而使用所述掩膜层作为蚀刻掩膜。
9.根据权利要求8所述的方法,其中,填充所述被加宽的沟槽包括通过所述开口将所述导电材料引入到所述被加宽的沟槽中。
10.根据权利要求8所述的方法,还包括部分或者完全移除所述掩膜层以及设置于所述开口中的所述导电材料的一部分。
11.根据权利要求8所述的方法,其中,在与所述被加宽的沟槽的行进方向垂直的截面平面中,
(a)所述开口包括最小宽度;
(b)所述被加宽的沟槽在所述开口与所述底面之间的区域中包括最大宽度,其中所述最大宽度大于所述最小宽度。
12.根据权利要求11所述的方法,其中,在与所述被加宽的沟槽的行进方向垂直的截面平面中,所述最大宽度大于(a)与(b)之差:
(a)在所述底面与所述开口之间的距离;以及
(b)在所述底面与所述导线之间的距离。
13.根据权利要求8所述的方法,其中,在用所述导电材料填充所述被加宽的沟槽之前,在所述被加宽的沟槽的表面上未沉积另外的材料。
14.根据权利要求1所述的方法,其中,所述介电层包括硅氧化物(SiOx)。
15.根据权利要求1所述的方法,其中,所述导线在与所述被加宽的沟槽的行进方向垂直的截面平面中包括具有如下表面位置的表面:所述表面位置的曲率半径在0.4μm到3.2μm的范围。
16.根据权利要求1所述的方法,其中,所述导线在与所述被加宽的沟槽的行进方向的截面平面中包括连续表面路径,所述连续表面路径在所述垂直方向上延伸到至少1OOnm或者至少0.8μm的距离且在任何一处具有在0.4μm到3.2μm的范围的曲率半径。
17.根据权利要求1所述的方法,其中,所述导电材料
(a)由铜或铝组成;或者
(b)包括铜或铝;或者
(c)由铜和铝组成;或者
(d)包括铜和铝;或者
(e)包括多晶半导体材料或由多晶半导体材料组成。
18.根据权利要求1所述的方法,其中,所述导线为所述半导体组件的无芯变压器的线圈的外绕组。
19.根据权利要求18所述的方法,其中,所述无芯变压器将被配置成控制半导体元件的控制电路从所述半导体元件的控制电极电去耦。
20.根据权利要求1所述的方法,其中,所述导线为电容器的电极。
21.根据权利要求20所述的方法,其中,所述电容器将被配置成控制半导体元件的控制电路从所述半导体元件的控制电极电去耦。
22.一种用于制造半导体组件的导线的方法,所述方法包括以下步骤:
提供具有底面和顶面的部分完成的半导体组件,所述顶面在垂直方向上与所述底面远离地间隔;
在所述顶面上设置介电层,所述介电层用在所述垂直方向上具有非恒量浓度层次的掺杂剂掺杂;
在所述介电层中形成沟槽,使得所述沟槽横穿所述介电层的多个区域,所述多个区域具有不同的掺杂剂浓度;
通过在由所述不同的掺杂剂浓度造成的不同蚀刻速率下蚀刻所述沟槽来加宽所述沟槽;
通过用导电材料填充被加宽的沟槽来形成导线。
23.根据权利要求22所述的方法,其中,所述导线在与所述被加宽的沟槽的行进方向的截面平面中包括如下表面位置:所述表面位置的曲率半径在0.4μm到3.2μm的范围。
24.根据权利要求23所述的方法,其中,
所述沟槽为螺旋形;并且
所述导线为螺旋形并且形成所述半导体组件的无芯变压器的线圈的外绕组。
25.一种用于制造半导体组件的导线的方法,所述方法包括以下步骤:
提供具有底面和顶面的部分完成的半导体组件,所述顶面在垂直方向上与所述底面远离地间隔;
提供蚀刻剂;
通过随后沉积至少两个子层来在所述顶面上设置被掺杂有掺杂剂的介电层,其中在所述至少两个子层的任何两个相邻子层中,所述掺杂剂的浓度为
(a)不同;或者
(b)在所述至少两个子层的所述两个相邻子层中的一个中为零,在所述至少两个子层的所述两个相邻子层中的另一个中大于零;
在所述介电层中形成沟槽,使得所述沟槽横穿所述至少两个子层中的各个子层;
通过在由所述掺杂剂的不同浓度造成的不同蚀刻速率下蚀刻所述沟槽来加宽所述沟槽;
通过用导电材料填充被加宽的沟槽来形成导线。
26.根据权利要求25所述的方法,其中,所述导线在截面平面中包括具有如下表面位置的表面:所述表面位置的曲率半径在0.4μm到3.2μm的范围。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/452,044 | 2012-04-20 | ||
US13/452,044 US9214424B2 (en) | 2012-04-20 | 2012-04-20 | Method for producing a conductor line |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103377881A true CN103377881A (zh) | 2013-10-30 |
CN103377881B CN103377881B (zh) | 2016-08-03 |
Family
ID=49290355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310141578.4A Active CN103377881B (zh) | 2012-04-20 | 2013-04-22 | 制造导线的方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9214424B2 (zh) |
CN (1) | CN103377881B (zh) |
DE (1) | DE102013206899A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105990228A (zh) * | 2015-03-16 | 2016-10-05 | 台湾积体电路制造股份有限公司 | 半导体器件结构及其形成方法 |
CN109427733B (zh) * | 2017-08-16 | 2024-01-23 | 德克萨斯仪器股份有限公司 | 具有嵌入式电感器或变压器的集成电路 |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9118241B2 (en) * | 2012-06-13 | 2015-08-25 | Intel Deutschland Gmbh | Switched-mode power supply and a two-phase DC to DC converter having switches and a filter that deliver current from a node among converter stages |
US9048730B2 (en) | 2012-06-13 | 2015-06-02 | Intel Mobile Communications GmbH | Switched mode power supply and a method for operating a switched mode power supply |
US9035627B2 (en) | 2012-06-13 | 2015-05-19 | Intel Mobile Communications GmbH | Switched mode power supply employing first and second feedback signals and a method of operating thereof |
JP6395304B2 (ja) * | 2013-11-13 | 2018-09-26 | ローム株式会社 | 半導体装置および半導体モジュール |
CN105990314B (zh) * | 2015-03-16 | 2018-10-26 | 台湾积体电路制造股份有限公司 | 半导体器件结构及其形成方法 |
EP3363050B1 (en) | 2015-07-23 | 2020-07-08 | Artilux Inc. | High efficiency wide spectrum sensor |
US10861888B2 (en) * | 2015-08-04 | 2020-12-08 | Artilux, Inc. | Silicon germanium imager with photodiode in trench |
US10761599B2 (en) | 2015-08-04 | 2020-09-01 | Artilux, Inc. | Eye gesture tracking |
US10707260B2 (en) | 2015-08-04 | 2020-07-07 | Artilux, Inc. | Circuit for operating a multi-gate VIS/IR photodiode |
WO2017024121A1 (en) | 2015-08-04 | 2017-02-09 | Artilux Corporation | Germanium-silicon light sensing apparatus |
EP3783656B1 (en) | 2015-08-27 | 2023-08-23 | Artilux Inc. | Wide spectrum optical sensor |
US10254389B2 (en) | 2015-11-06 | 2019-04-09 | Artilux Corporation | High-speed light sensing apparatus |
US10886309B2 (en) | 2015-11-06 | 2021-01-05 | Artilux, Inc. | High-speed light sensing apparatus II |
US10739443B2 (en) | 2015-11-06 | 2020-08-11 | Artilux, Inc. | High-speed light sensing apparatus II |
US10741598B2 (en) | 2015-11-06 | 2020-08-11 | Atrilux, Inc. | High-speed light sensing apparatus II |
US10418407B2 (en) | 2015-11-06 | 2019-09-17 | Artilux, Inc. | High-speed light sensing apparatus III |
ITUA20162049A1 (it) * | 2016-03-25 | 2017-09-25 | St Microelectronics Srl | Dispositivo elettronico con isolamento galvanico integrato e metodo di fabbricazione dello stesso |
US10170419B2 (en) | 2016-06-22 | 2019-01-01 | International Business Machines Corporation | Biconvex low resistance metal wire |
US9991199B1 (en) * | 2016-11-23 | 2018-06-05 | International Business Machines Corporation | Integrated shielding and decoupling capacitor structure |
GB2557614A (en) * | 2016-12-12 | 2018-06-27 | Infineon Technologies Austria Ag | Semiconductor device, electronic component and method |
US10901543B1 (en) * | 2017-09-29 | 2021-01-26 | Apple Inc. | Touch screen with transparent electrode structure |
US11105928B2 (en) | 2018-02-23 | 2021-08-31 | Artilux, Inc. | Light-sensing apparatus and light-sensing method thereof |
WO2019165220A1 (en) | 2018-02-23 | 2019-08-29 | Artilux, Inc. | Photo-detecting apparatus and photo-detecting method thereof |
CN112236686B (zh) | 2018-04-08 | 2022-01-07 | 奥特逻科公司 | 光探测装置 |
TWI795562B (zh) | 2018-05-07 | 2023-03-11 | 美商光程研創股份有限公司 | 雪崩式之光電晶體 |
US10969877B2 (en) | 2018-05-08 | 2021-04-06 | Artilux, Inc. | Display apparatus |
US11448830B2 (en) | 2018-12-12 | 2022-09-20 | Artilux, Inc. | Photo-detecting apparatus with multi-reset mechanism |
TW202104927A (zh) | 2019-06-19 | 2021-02-01 | 美商光程研創股份有限公司 | 光偵測裝置以及電流再利用方法 |
JP7170685B2 (ja) | 2020-03-19 | 2022-11-14 | 株式会社東芝 | アイソレータ |
JP7284121B2 (ja) * | 2020-03-23 | 2023-05-30 | 株式会社東芝 | アイソレータ |
US20230275118A1 (en) * | 2022-02-28 | 2023-08-31 | Analog Devices International Unlimited Company | Shaped metal edge for galvanic or capacitive isolator |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020093105A1 (en) * | 2000-10-30 | 2002-07-18 | Samsung Electronics Co., Ltd. | Semiconductor device having a contact window and fabrication method thereof |
US6482701B1 (en) * | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
US20020190301A1 (en) * | 2001-06-15 | 2002-12-19 | Chen-Chiu Hsue | Capacitor with lower electrode located at the same level as an interconnect line |
US6960519B1 (en) * | 2004-06-25 | 2005-11-01 | International Business Machines Corporation | Interconnect structure improvements |
CN1738046A (zh) * | 2004-08-20 | 2006-02-22 | 株式会社瑞萨科技 | 具备电感器的半导体装置 |
CN101390204A (zh) * | 2006-03-01 | 2009-03-18 | 国际商业机器公司 | 用于金属集成的新颖结构和方法 |
US20110156854A1 (en) * | 2007-10-12 | 2011-06-30 | Via Technologies, Inc. | Spiral Inductor Device |
CN102130510A (zh) * | 2010-01-18 | 2011-07-20 | 英飞凌科技奥地利有限公司 | 信号传输装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6458657B1 (en) * | 2000-09-25 | 2002-10-01 | Macronix International Co., Ltd. | Method of fabricating gate |
US6706637B2 (en) * | 2002-05-09 | 2004-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual damascene aperture formation method absent intermediate etch stop layer |
US9018730B2 (en) * | 2011-04-05 | 2015-04-28 | Stmicroelectronics S.R.L. | Microstructure device comprising a face to face electromagnetic near field coupling between stacked device portions and method of forming the device |
US9183977B2 (en) | 2012-04-20 | 2015-11-10 | Infineon Technologies Ag | Method for fabricating a coil by way of a rounded trench |
-
2012
- 2012-04-20 US US13/452,044 patent/US9214424B2/en not_active Expired - Fee Related
-
2013
- 2013-04-17 DE DE102013206899A patent/DE102013206899A1/de active Pending
- 2013-04-22 CN CN201310141578.4A patent/CN103377881B/zh active Active
-
2015
- 2015-11-09 US US14/936,339 patent/US10090192B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6482701B1 (en) * | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
US20020093105A1 (en) * | 2000-10-30 | 2002-07-18 | Samsung Electronics Co., Ltd. | Semiconductor device having a contact window and fabrication method thereof |
US20020190301A1 (en) * | 2001-06-15 | 2002-12-19 | Chen-Chiu Hsue | Capacitor with lower electrode located at the same level as an interconnect line |
US6960519B1 (en) * | 2004-06-25 | 2005-11-01 | International Business Machines Corporation | Interconnect structure improvements |
CN1738046A (zh) * | 2004-08-20 | 2006-02-22 | 株式会社瑞萨科技 | 具备电感器的半导体装置 |
CN101390204A (zh) * | 2006-03-01 | 2009-03-18 | 国际商业机器公司 | 用于金属集成的新颖结构和方法 |
US20110156854A1 (en) * | 2007-10-12 | 2011-06-30 | Via Technologies, Inc. | Spiral Inductor Device |
CN102130510A (zh) * | 2010-01-18 | 2011-07-20 | 英飞凌科技奥地利有限公司 | 信号传输装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105990228A (zh) * | 2015-03-16 | 2016-10-05 | 台湾积体电路制造股份有限公司 | 半导体器件结构及其形成方法 |
CN105990228B (zh) * | 2015-03-16 | 2019-04-23 | 台湾积体电路制造股份有限公司 | 半导体器件结构及其形成方法 |
CN109427733B (zh) * | 2017-08-16 | 2024-01-23 | 德克萨斯仪器股份有限公司 | 具有嵌入式电感器或变压器的集成电路 |
Also Published As
Publication number | Publication date |
---|---|
US9214424B2 (en) | 2015-12-15 |
DE102013206899A1 (de) | 2013-10-24 |
US20160064273A1 (en) | 2016-03-03 |
US20130280879A1 (en) | 2013-10-24 |
CN103377881B (zh) | 2016-08-03 |
US10090192B2 (en) | 2018-10-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103377881A (zh) | 制造导线的方法 | |
TWI527162B (zh) | 包含在一凹槽中之特徵之電子裝置 | |
CN103700650B (zh) | 半导体元件和制造半导体元件的方法 | |
US6420773B1 (en) | Multi-level spiral inductor structure having high inductance (L) and high quality factor (Q) | |
US10157706B2 (en) | Inductor structure with magnetic material | |
JP2004526311A (ja) | 高qインダクタ | |
CN102280496A (zh) | 变容器与形成其的方法以及应用此变容器的三维集成电路 | |
EP3174094B1 (en) | Integrated circuit comprising a metal-insulator-metal capacitor and fabrication method thereof | |
US8866223B2 (en) | Process for manufacturing a power semiconductor device having charge-balance columnar structures on a non-planar surface, and corresponding power semiconductor device | |
JPH09162354A (ja) | 集積インダクタ構造およびその製造方法 | |
CN105047627A (zh) | 半导体结构及其制造方法 | |
US7723821B2 (en) | Microelectronic assembly | |
US9673081B2 (en) | Isolated through silicon via and isolated deep silicon via having total or partial isolation | |
US7264986B2 (en) | Microelectronic assembly and method for forming the same | |
US9343352B2 (en) | Integrated circuit using deep trench through silicon (DTS) | |
EP2875525B1 (en) | Semiconductor die with a through-silicon via and corresponding method of fabrication | |
US9431286B1 (en) | Deep trench with self-aligned sinker | |
US7485945B2 (en) | Integrated capacitor structure | |
US20200243602A1 (en) | Integrated circuits with integrated memory structures and capacitors and methods for fabricating the same | |
US20140147985A1 (en) | Methods for the fabrication of semiconductor devices including sub-isolation buried layers | |
CN114096865A (zh) | 霍尔集成式传感器和对应的制造工艺 | |
CN106898458A (zh) | 电感器及其形成方法 | |
TW518619B (en) | Integrated circuit | |
WO2014204401A1 (en) | Protective structure for through-silicon-via | |
US20080197495A1 (en) | Structure for reducing lateral fringe capacitance in semiconductor devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |