CN103350983A - Integrated wafer-level vacuum packaged MEMS device and manufacturing method thereof - Google Patents
Integrated wafer-level vacuum packaged MEMS device and manufacturing method thereof Download PDFInfo
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- CN103350983A CN103350983A CN2013102721931A CN201310272193A CN103350983A CN 103350983 A CN103350983 A CN 103350983A CN 2013102721931 A CN2013102721931 A CN 2013102721931A CN 201310272193 A CN201310272193 A CN 201310272193A CN 103350983 A CN103350983 A CN 103350983A
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Abstract
The invention discloses an integrated wafer-level vacuum packaged MEMS device and a manufacturing method thereof. The manufacturing method comprises the following steps: forming an MEMS structure on a monocrystalline silicon wafer substrate; forming a first sacrificial layer on the MEMS structure; forming a patterned electrode layer on the first sacrificial layer; forming a second sacrificial layer on the electrode layer; forming a sealed cavity on the monocrystalline silicon wafer substrate located below the MEMS structure and sealing the cavity with a third sacrificial layer; allowing the second and third sacrificial layers to be patterned; forming a cover layer on the third sacrificial layer; allowing the cover layer to be patterned and removing the first, second and third sacrificial layers to enable the MEMS structure to be released; forming a sealing structure on the cover layer; forming a metal lead wire on the sealing structure; and carrying out low temperature annealing. According to the invention, the MEMS structure is a monocrystalline silicon material and is anchored on the upper part of a packaging structure, so influence of the stress of the substrate on the device is reduced; a gap between an electrode and the MEMS structure is fairly small, so energy loss of the device is reduced, and low cost and high quality of the MEMS device are obtained.
Description
Technical field
The present invention relates to semiconductor fabrication, be specifically related to a kind of MEMS device and manufacture method thereof of integrated wafer-level vacuum packaged.
Background technology
MEMS (Micro-Electro-Mechanical Systems, be called for short MEMS), but refer to batch making, integrate that micro mechanism, microsensor, miniature actuator and signal process and microdevice or the system of control circuit etc.MEMS device manufacturing technology has merged multiple Micrometer-Nanometer Processing Technology, has opened up a brand-new technical field and industry.The microsensor that adopts the MEMS fabrication techniques has very wide application prospect in Aeronautics and Astronautics, automobile, military affairs and all spectra that almost people touch.
Present modal MEMS manufacture method is exactly to use silicon (SOI) wafer on the insulator to make the MEMS device.Sacrifice layer between MEMS structure and the substrate is the silica material in the middle of the SOI wafer at this moment, the material that binds is polysilicon, silica, germanium silicon of epitaxially grown polysilicon or low-pressure chemical vapor phase deposition (LPCVD) etc., and MEMS structure and the sacrifice layer that binds between the material are the LPCVD silica.Another kind of manufacture method uses monocrystalline silicon wafer crystal to make the MEMS device exactly, and the crystal orientation of monocrystalline silicon wafer crystal is＜100 usually 〉.This moment, the MEMS structure was by epitaxially grown silicon materials manufacturing, this silicon epitaxial layers part is monocrystalline silicon, and another part is polysilicon, the material that binds of Vacuum Package is epitaxially grown polysilicon or LPCVD silica, and the sacrifice layer that MEMS structure and substrate or Vacuum Package bind between the layer is low-doped silicon.
Yet, use now the method for SOI wafer manufacturing MEMS device mainly based on wafer bonding technique, its manufacturing process is complicated, processing cost is high, has increased the manufacturing cost of MEMS device.On the other hand, if process the MEMS structure with epitaxially grown silicon materials, because silicon epitaxial layers comprises the part polysilicon, and there is the structure cell boundary effect in the polycrystalline silicon material, greatly increased the energy loss of MEMS device.And the structure member of MEMS device commonly used all is anchored on the substrate layer of bottom at present, like this in follow-up encapsulation process, any unmatched residual stress all can cause the distortion of MEMS structure member anchor point in the substrate, has greatly affected the MEMS performance of devices.
Summary of the invention
The object of the invention is to propose a kind of MEMS device and manufacture method thereof of integrated wafer-level vacuum packaged, to solve the problem that has substrate stress in the MEMS device, reduce the manufacturing cost of MEMS device.
The invention discloses a kind of manufacture method of MEMS device of integrated wafer-level vacuum packaged, may further comprise the steps:
Form the MEMS structure at the monocrystalline silicon wafer crystal substrate;
Form the first sacrifice layer in described MEMS structure;
Form patterned electrode layer at described the first sacrifice layer;
Form the second sacrifice layer at described patterned electrode layer;
Form sealed cavity at described monocrystalline silicon wafer crystal substrate, wherein said sealed cavity is positioned at MEMS structure below, and described sealed cavity is by the 3rd sacrifice layer sealing that is formed on described the second sacrifice layer;
Graphical described the second sacrifice layer and the 3rd sacrifice layer form hatch frame at described the second sacrifice layer and the 3rd sacrifice layer;
Form cover layer at described patterned the 3rd sacrifice layer, described cover layer and described electrode layer are connected with opening on the 3rd sacrifice layer by described the second sacrifice layer;
Graphical described cover layer, form hatch frame at described cover layer, and remove the part-structure of the part-structure of described the first sacrifice layer, described the second sacrifice layer and the part-structure of described the 3rd sacrifice layer by described tectal hatch frame, make the MEMS structure obtain discharging;
Form hermetically-sealed construction at described cover layer, be useful on the hatch frame of Metal Contact at described hermetically-sealed construction;
Form metal lead wire at described hermetically-sealed construction;
Process annealing.
Further, the crystal orientation of described monocrystalline silicon wafer crystal substrate is＜111 〉.
Further, form the first sacrifice layer in described MEMS structure and also comprise graphical described the first sacrifice layer, obtain hatch frame at described the first sacrifice layer, the hatch frame of wherein said the first sacrifice layer is used for determining the anchor station of described MEMS structure.
Further, forming sealed cavity at described monocrystalline silicon wafer crystal substrate comprises:
Form at least one at described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate and be communicated with the opening of described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, be used for the described monocrystalline silicon wafer crystal substrate of expose portion;
By described opening, form a cavity at described monocrystalline silicon wafer crystal substrate, wherein said cavity is positioned at MEMS structure below, and the method that forms cavity at described monocrystalline silicon wafer crystal substrate is the anisotropic etching method of silicon;
Form the 3rd sacrifice layer at described the second sacrifice layer, seal described opening, so that described cavity forms a sealed cavity.
Further, forming at least one opening that is communicated with described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate at described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate comprises:
Form at least one at described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate and be communicated with the first opening of described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, wherein the degree of depth of the first opening on described monocrystalline silicon wafer crystal substrate is less than the height of described MEMS structure;
Inner surface at described the first opening forms protective layer, and removes the described protective layer that is positioned at described the first opening lower surface;
Continue to form the second opening at described the first opening, wherein the first opening degree of depth on described monocrystalline silicon wafer crystal substrate and the second opening degree of depth sum are greater than the height of described MEMS structure.
Further, the thickness of described protective layer is less than the thickness sum of the first sacrifice layer and the second sacrifice layer.
Further, the method for removing the described protective layer be positioned at described the first opening lower surface is the autoregistration anisotropic etching method.
Further, forming hermetically-sealed construction at described cover layer comprises:
Form insulating barrier at described cover layer, graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
Further, described electrode layer and cover layer all are epitaxially grown polysilicon layers, and doping type is identical.
Further, forming hermetically-sealed construction at described cover layer comprises:
Form sealant at described cover layer, graphical described cover layer and sealant form hatch frame, and wherein said hatch frame aligns with described the second sacrifice layer and the 3rd sacrifice layer do not removed;
Form insulating barrier at described sealant, graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
Further, described electrode layer, cover layer and sealant all are epitaxially grown polysilicon layers, and doping type is identical.
The present invention discloses a kind of MEMS device of integrated wafer-level vacuum packaged on the other hand, comprising:
The monocrystalline silicon wafer crystal substrate;
The MEMS structure that the described monocrystalline silicon wafer crystal substrate of etching forms;
Be arranged on the structural electrode layer of described MEMS, be used for control MEMS structure;
Be arranged on the cover layer of described electrode layer top, be formed on the first cavity between described cover layer and the described MEMS structure and be formed on described MEMS structure and described monocrystalline silicon wafer crystal substrate between the second cavity, wherein said cover layer links to each other with described electrode layer electricity, be formed with hatch frame on described cover layer and the described electrode layer, described hatch frame is used for the electricity isolation;
Be arranged on the separation layer between described monocrystalline silicon wafer crystal substrate and the cover layer, be used for sealing the side of described the first cavity;
Be arranged on described supratectal hermetically-sealed construction, be used for sealing described tectal hatch frame, wherein said the first cavity and the second cavity form sealed cavity, and described MEMS structure can be movable in described sealed cavity;
Be arranged on the metal lead wire on the described hermetically-sealed construction.
Further, described electrode layer and cover layer all are epitaxially grown polysilicon layers, and doping type is identical.
The present invention directly forms the MEMS structure on the monocrystalline silicon wafer crystal substrate, and the monocrystalline silicon wafer crystal substrate below the MEMS structure forms sealed cavity, form electrode layer and hermetically-sealed construction at the MEMS superstructure, so that the MEMS Structure anchor, has reduced the residual stress effect that substrate brings in the top of encapsulating structure.The present invention uses a plurality of sacrificial layer structures to be used for the release of MEMS structure, so that the gap between electrode and the MEMS movable structure is very little, usually tens nanometers, can reduces the driving voltage of MEMS device and then reduce total power consumption.Simultaneously the MEMS structure is single crystal silicon material, does not have the structure cell boundary effect, has reduced the energy loss of device, and the MEMS device has the Vacuum Package of wafer scale, has realized low-cost, high-quality MEMS device fabrication.
Description of drawings
Fig. 1 is the flow chart of the manufacture method of first embodiment of the invention.
Fig. 2 A-2P is the process chart of the manufacture method of first embodiment of the invention.
Fig. 3 A-3C is the process chart of the manufacture method of second embodiment of the invention.
Fig. 4 is the structural representation of the MEMS device of third embodiment of the invention.
Fig. 5 is the structural representation of the MEMS device of fourth embodiment of the invention.
The specific embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.Be understandable that specific embodiment described herein only is used for explaining the present invention, but not limitation of the invention.Also need to prove in addition, for convenience of description, only show part related to the present invention in the accompanying drawing but not all.
The first embodiment
Fig. 1 is the flow chart of manufacture method of MEMS device of the integrated wafer-level vacuum packaged of first embodiment of the invention, and Fig. 2 A-2P is the process chart of the manufacture method of first embodiment of the invention.As shown in Figure 1, described manufacture method comprises:
Step 101A, form mask layer at the monocrystalline silicon wafer crystal substrate.
Shown in Fig. 2 A, be mask layer 202 of deposit on＜111〉the monocrystalline silicon wafer crystal substrates 201 in the crystal orientation, described mask layer 202 can be silica, low-pressure chemical vapor deposition (LPCVD) silica or plasma activated chemical vapour deposition (PECVD) silica of heat growth.
The crystal orientation refers to the atom row by the different directions at crystal Atom center.Form because monocrystal is arranged institute by the atom periodic regular, therefore can mark off a series of crystal faces parallel to each other in monocrystal, come crystal face of mark with the indices of crystallographic plane traditionally, the crystal orientation just can use the normal direction perpendicular to this crystal face to represent.Because silicon belongs to cubic crystal structure, the arranging density of atom is different on different crystal faces, causes the anisotropy of silicon crystal, so the diffusion velocity of impurity, corrosion rate are not identical yet.Silicon single crystal in the atomic density on the crystal face in crystal orientation＜111, crystal orientation＜110 and crystal orientation＜100 on successively decrease successively, therefore Impurity Diffusion speed is in crystal orientation＜111 〉, crystal orientation＜110 and crystal orientation＜100 on increase progressively successively, then corrosion rate is in crystal orientation＜111 〉, crystal orientation＜110 and crystal orientation＜100 on increase progressively successively.
Chemical vapor deposition, being called for short CVD (Chemical Vapor Deposition) is to supply with substrate containing one or several compounds or the elementary gas that consist of the film element, generate required film by gas phase action or at on-chip chemical reaction, specifically refer to gas-phase reaction at high temperature, for example, the thermal decomposition of metal halide, organic metal, hydrocarbon etc., hydrogen reduction or make its mist chemical reaction at high temperature occur with the method for the inorganic material such as precipitating metal, oxide, carbide.And low-pressure chemical vapor deposition is called for short LPCVD(Low Pressure Chemical Vapor Deposition) refer to the chemical vapour deposition (CVD) carried out under the atmospheric condition being lower than.Plasma activated chemical vapour deposition is called for short PECVD(Plasma Enhanced Chemical Vapor Deposition) refer in low pressure chemical vapor deposition, utilize the growing film that affects of glow discharge plasma.
Chemical vapour deposition (CVD) has can deposit that all kinds of films, film forming speed are fast, good, the plurality of advantages such as residual stress is little, film purity height of compactness of film, so be widely used in refining, the technical fields such as powder is synthetic, semiconductive thin film of high purity metal.The effect of chemical vapour deposition (CVD) is exactly the various functional thin layers of deposit in an embodiment of the present invention, with the technological effect of realizing that the embodiment of the invention will reach.
Step 101B, the described mask layer of patterning form hatch frame.
Shown in Fig. 2 B, graphical described mask layer 202, specifically, adopt the techniques such as photoetching, dry etching or wet etching to remove the part-structure of described mask layer 202 at described mask layer 202 exactly, to form the patterns of openings that needs at described mask layer 202.
Step 101C, carry out etching to form the MEMS structure by the hatch frame on the described mask layer at described monocrystalline silicon wafer crystal substrate.Shown in Fig. 2 C, adopt deep reactive ion silicon etching (DRIE) technique etching to obtain MEMS structure 203 at monocrystalline silicon wafer crystal substrate 201, and the lift off mask layer.Can obtain some deep holes after the etching, the size and shape of described deep hole determines according to the design needs of MEMS device.
Deep reactive ion silicon etching (DRIE) is based on the principle (also being known as " suitching type etching technics ") of " Bosch technique ", and a kind of method of fabulous anisotropic high speed etch silicon can be provided, and keeps simultaneously very high etching photoresistance to select ratio.This method is in plasma etch system, repeats in proper order etching and polymer deposition step.The polymer deposition step can form protecting film at silicon guide hole sidewall, prevents the side direction etching.Etch step is optimised, removes first deposited polymer from etching structure bottom, then with the silicon of high etch rate etching under it.In embodiments of the present invention, DRIE technique is used to form high-precision MEMS structure.
In the preferred embodiment of the embodiment of the invention, preferred described mask layer 202 is photoresist, such as the technological process of Fig. 2 A-2C, can only realize by a photoetching process, has simplified procedure of processing.
Shown in Fig. 2 D, form the first sacrifice layer 204 in described MEMS structure 203, form the first sacrifice layer in described MEMS structure and also comprise graphical described the first sacrifice layer 204, obtain hatch frame at described the first sacrifice layer, the hatch frame of wherein said the first sacrifice layer 204 is used for determining the anchor station of described MEMS structure.
Particularly, described the first sacrifice layer 204 uses chemical vapor deposition method to form, and its material is silica.Graphical described the first sacrifice layer 204 just refers to adopt the techniques such as photoetching, dry etching or wet etching to remove the part-structure of described the first sacrifice layer 204, to form the pattern that needs at described the first sacrifice layer 204, the position of described pattern is exactly the position that MEMS structure 203 arranges anchor point.
Of particular note, graphic method described in the embodiment of the invention all refers to adopt the techniques such as photoetching, dry etching or wet etching to remove part-structure, thereby forms the method for required pattern, and the back will repeat no more.
Shown in Fig. 2 E, form patterned electrode layer 205 at described the first sacrifice layer 204.Specifically, described electrode layer 205 is formed by epitaxially grown polysilicon, and is in-situ doped into P type or N-type.Epitaxial growth just refers to have the process of the thin layer crystal of identical or approaching crystallographic orientation in certain initial crystal (substrate) growth.Being used for each component and the adulterant of growth compound crystal can pass in the reative cell in the gaseous state mode, can control by the flow of controlling various gases the characteristic such as component, conduction type, carrier concentration, thickness of epitaxial loayer.Extension occurs on the surface of substrate of heating, can control course of reaction by the monitoring substrate temperature.
Shown in Fig. 2 F, deposit forms the second sacrifice layer 206 on described patterned electrode layer 205, and the material of described the second sacrifice layer 206 is silica.
In a preferred embodiment of the embodiment of the invention, use LPCVD ethyl orthosilicate (TEOS) technique deposit the second sacrifice layer 206.When using TEOS as the reactant source of chemical vapor deposition, because the TEOS molecule does not have completely symmetrical structure, can form hydrogen bond and surface mobility is high at substrate surface, have better Step Coverage characteristic.
Step 105A, form at least one at described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate and be communicated with the opening of described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, be used for the described monocrystalline silicon wafer crystal substrate of expose portion.Described step 105A also comprises three sub-steps:
Step 105AI, form at least one at described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate and be communicated with the first opening of described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, wherein the degree of depth of the first opening on described monocrystalline silicon wafer crystal substrate is less than the height of described MEMS structure.
Shown in Fig. 2 G, form first opening that is communicated with described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate at described the first sacrifice layer 204, the second sacrifice layer 206 and monocrystalline silicon wafer crystal substrate 201.Specifically, at first etch an opening that runs through described the first sacrifice layer 204 and second layer sacrifice layer 206 at described the first sacrifice layer 204 and second layer sacrifice layer 206, then by the described opening that runs through the first sacrifice layer 204 and second layer sacrifice layer 206, thereby adopt DRIE technique to continue the described monocrystalline silicon wafer crystal substrate 201 of etching and obtain the first opening, the degree of depth of described the first opening on described monocrystalline silicon wafer crystal substrate 201 is H1, and wherein H1 is less than the height D of described MEMS structure 203.
Step 105AII, form protective layer at the inner surface of described the first opening, and remove the described protective layer that is positioned at described the first opening lower surface.
Shown in Fig. 2 H, at the inner surface formation protective layer 207 of described the first opening, particularly, the described protective layer 207 that obtains by the thermal oxide growth method is silica material, and its thickness is T3.So, described the first sacrifice layer 204, the second sacrifice layer 206 and protective layer 207 all are silica, and the thickness T 3 of described protective layer 207 will be much smaller than the thickness T 1 of described the first sacrifice layer 204 and thickness T 2 sums of the second sacrifice layer 206.Therefore, just can adopt autoregistration anisotropy silica dry etch process to remove the described protective layer 207 that is positioned at described the first opening lower surface.Like this, the part that described protective layer 207 is positioned at the first open side is retained, and is used for the cross-protection of described the first opening.
So-called self-aligned technology refer to utilize in microelectric technique element, device architecture characteristics realize the self-aligning technology of recovery seal.When using the removal of autoregistration anisotropy silica dry etching to be positioned at the described protective layer 207 of described the first opening lower surface; etching depth is the thickness T 3 of described protective layer 207; because the thickness T 1 of described the first sacrifice layer 204 and thickness T 2 sums of the second sacrifice layer 206 are much larger than T3; so described Self-aligned etching does not affect described the first sacrifice layer 204 and the second sacrifice layer 206 substantially, thereby has simplified etch step.
Step 105AIII, continue to form the second opening at described the first opening, wherein the first opening degree of depth on described monocrystalline silicon wafer crystal substrate and the second opening degree of depth sum are greater than the height of described MEMS structure.
Shown in Fig. 2 I, continue to form the second opening at described the first opening, lithographic method still adopts DRIE technique, the degree of depth of described the second opening is H2, and wherein the first opening depth H 1 on described monocrystalline silicon wafer crystal substrate 201 and the second opening depth H 2 sums are greater than the height D of described MEMS structure.
Step 105B, by described opening, form a cavity at described monocrystalline silicon wafer crystal substrate, wherein said cavity is positioned at MEMS structure below, the method that forms cavity at described monocrystalline silicon wafer crystal substrate is the anisotropic etching method of silicon.
Shown in Fig. 2 J, by the hatch frame on the described monocrystalline silicon wafer crystal substrate 201, form a cavity at the described monocrystalline silicon wafer crystal substrate 201 that is positioned at below the MEMS structure 203, the method that wherein forms cavity is the anisotropic etching method of silicon, etching solution can be potassium hydroxide (KOH) or TMAH (TMAH), because etching solution has selectively the etching of silicon crystal different crystal orientations, and used in embodiments of the present invention＜111〉crystal orientation monocrystalline silicon wafer crystal substrate 201, so can form very smooth housing surface after the etching.The degree of depth of described cavity is the height D that described the first opening depth H 1 and the second opening depth H 2 sums deduct described MEMS structure.
Step 105C, form the 3rd sacrifice layer at described the second sacrifice layer, seal described opening, so that described cavity forms a sealed cavity.
Shown in Fig. 2 K, deposit forms the 3rd sacrifice layer 208 on described the second sacrifice layer 206, seals described opening, so that described cavity forms a sealed cavity, the material of wherein said the 3rd sacrifice layer 208 is silica.
Shown in Fig. 2 L, graphical described the second sacrifice layer 206 and the 3rd sacrifice layer 208, etching forms hatch frame on described the second sacrifice layer 206 and the 3rd sacrifice layer 208.
Shown in Fig. 2 M, form cover layer 209 at described patterned the second sacrifice layer 206, described cover layer 209 is connected with the opening of described electrode layer 205 by described the second sacrifice layer 206 and the 3rd sacrifice layer 208.Specifically, described cover layer 209 is formed by epitaxially grown polysilicon, and is in-situ doped into P type or N-type, and its doping type is the same with the doping type of described electrode layer 205, and described like this cover layer 209 has been realized electric linking to each other with described electrode layer 205.
Shown in Fig. 2 N, graphical described cover layer 209, namely etching forms hatch frame on described cover layer 209, and the hatch frame by described cover layer 209, use described the first sacrifice layer 204 of gaseous state hf etching, the second sacrifice layer 206 and the 3rd sacrifice layer 208, make the MEMS structure obtain discharging.
Of particular note, described the first sacrifice layer 204, the second sacrifice layer 206 and the 3rd sacrifice layer 208 form but kept a part of part as follow-up vacuum encapsulation structure not by fully etching removal.Because described the first sacrifice layer 204, the second sacrifice layer 206 and the 3rd sacrifice layer 208 all are silica materials, structurally can regard an integral body as, so in the follow-up technique of present embodiment, unified the 3rd sacrifice layer 208 that uses is described as representative.
Shown in Fig. 2 O, deposit forms insulating barrier 210 on described cover layer 209, and graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier 210 is used for Metal Contact.
Shown in Fig. 2 P, form metal lead wire 211 at described hermetically-sealed construction.
At last, the MEMS device that adopts above-mentioned technological process to make is carried out process annealing
The embodiment of the invention is passed through directly etching formation MEMS structure on the monocrystalline silicon wafer crystal substrate, and the monocrystalline silicon wafer crystal substrate below the MEMS structure forms sealed cavity, so that the MEMS structure is single crystal silicon material, there is not the structure cell boundary effect, reduced the energy loss of MEMS device, and the MEMS Structure anchor has reduced the stress effect that substrate brings in the top of encapsulating structure.Present embodiment has used a plurality of sacrificial layer structures to be used for the release of MEMS structure, so that the gap between electrode and the MEMS movable structure is very little, can reduces the driving voltage of MEMS device and then reduce total power consumption.The monocrystalline silicon wafer crystal manufacturing process is simple, cheap simultaneously, thereby has reduced the production cost of MEMS device.
The second embodiment
Fig. 3 A-3C is the process chart of the manufacture method of second embodiment of the invention.Step 101 among the technological process of described second embodiment of the invention and described the first embodiment is identical to the technique of step 108, repeats no more here, on the basis of described step 108, continues the technological process of described third embodiment of the invention, comprising:
Step 109 ＇, form hermetically-sealed construction at described cover layer, be useful on the hatch frame of Metal Contact at described hermetically-sealed construction.Described step 109 ＇ comprises two sub-steps:
Step 109 ＇ A, form sealant at described cover layer, graphical described cover layer and sealant form hatch frame, and wherein said hatch frame aligns with described the second sacrifice layer and the 3rd sacrifice layer do not removed.
As shown in Figure 3A, form sealant 212 at described cover layer 209, graphical described cover layer 209 and sealant 212 form hatch frame, and wherein said hatch frame aligns with described the second sacrifice layer 206 and the 3rd sacrifice layer 208 do not removed.Specifically, described sealant 212 is formed by epitaxially grown polysilicon, and is in-situ doped into P type or N-type, and its doping type is the same with the doping type of described electrode layer 205 and described cover layer 209.Form hatch frame by etching technics at described cover layer 209 and sealant 212, and described hatch frame aligns with described the second sacrifice layer 206 and the 3rd sacrifice layer 208 do not removed, has realized simultaneously like this electricity isolation of described electrode layer 205 different pieces at the seal that guarantees not destroy sealed cavity.
Of particular note, described the second sacrifice layer 206 and the 3rd sacrifice layer 208 all are silica materials, structurally can regard an integral body as, so in the follow-up technique of present embodiment, unified the 3rd sacrifice layer 208 that uses is described as representative.
Step 109 ＇ B, form insulating barrier at described sealant, graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
Shown in Fig. 3 B, deposit forms insulating barrier 213 on described sealant 212, and graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier 213 is used for Metal Contact.
Step 110 ＇, form metal lead wire at described insulating barrier, described metal lead wire links to each other with external control circuit.
Shown in Fig. 3 C, form metal lead wire 214 at described insulating barrier 213.
Step 111 ＇, process annealing.
At last, the MEMS device that adopts above-mentioned technological process to make is carried out process annealing.
The embodiment of the invention seals the cavity structure of MEMS device by the mode of epitaxial growth polysilicon, like this in described sealed cavity remaining gas take hydrogen as main, because hydrogen molecule is minimum, so in follow-up process annealing process, not only reduced the contact resistance of metal and polysilicon, and so that the remaining hydrogen in the sealed cavity all spreads out, realized pressing the Vacuum Package of millitorr level.
The 3rd embodiment
Fig. 4 is the structural representation of MEMS device of the integrated wafer-level vacuum packaged of third embodiment of the invention, and wherein said MEMS device is to adopt the technological process manufacturing of first embodiment of the invention to obtain.As shown in Figure 4, described device comprises:
Monocrystalline silicon wafer crystal substrate 41.
The MEMS structure 42 that the described monocrystalline silicon wafer crystal substrate 41 of etching forms.
Be arranged on the electrode layer 43 on the described MEMS structure 42, be used for control MEMS structure 42.
Be arranged on the cover layer 44 of described electrode layer 43 tops, be formed on the first cavity between described cover layer 44 and the described MEMS structure 42 and be formed on described MEMS structure 42 and described monocrystalline silicon wafer crystal substrate 41 between the second cavity, wherein said cover layer 44 links to each other with described electrode layer 43 electricity, be formed with hatch frame on described cover layer 44 and the described electrode layer 43, described hatch frame is used for the electricity isolation, described electrode layer 43 and cover layer 44 all are epitaxially grown polysilicon layers, and doping type is identical.
Be arranged on the separation layer 45 between described monocrystalline silicon wafer crystal substrate 41 and the cover layer 44, be used for sealing the side of described the first cavity.
Be arranged on the hermetically-sealed construction 46 on the described cover layer 44, be used for sealing the hatch frame of described cover layer 44, wherein said the first cavity and the second cavity form sealed cavity, and described MEMS structure 42 can be movable in described sealed cavity.
Be arranged on the metal lead wire 47 on the described hermetically-sealed construction 46, be used for connecting external control circuit.
The embodiment of the invention arranges the MEMS structure at the monocrystalline silicon wafer crystal substrate, and the monocrystalline silicon wafer crystal substrate below the MEMS structure arranges sealed cavity, so that the MEMS structure is single crystal silicon material, there is not the structure cell boundary effect, reduced the energy loss of MEMS device, and the MEMS Structure anchor has reduced the stress effect that substrate brings in the top of encapsulating structure.Manufacturing process owing to monocrystalline silicon wafer crystal is simple, cheap simultaneously, thereby has reduced the production cost of MEMS device.
The 4th embodiment
Fig. 5 is the structural representation of MEMS device of the integrated wafer-level vacuum packaged of fourth embodiment of the invention, and wherein said MEMS device is to adopt the technological process manufacturing of second embodiment of the invention to obtain.As shown in Figure 5, described device comprises:
Monocrystalline silicon wafer crystal substrate 51.
The MEMS structure 52 that the described monocrystalline silicon wafer crystal substrate 51 of etching forms.
Be arranged on the electrode layer 53 on the described MEMS structure 52, be used for control MEMS structure 52.
Be arranged on the cover layer 54 of described electrode layer 53 tops, be formed on the first cavity between described cover layer 54 and the described MEMS structure 52 and be formed on described MEMS structure 52 and described monocrystalline silicon wafer crystal substrate 51 between the second cavity, wherein said cover layer 54 and described electrode layer 53 electricity link to each other.
Be arranged on the separation layer 55 between described monocrystalline silicon wafer crystal substrate 51 and the cover layer 54, be used for sealing the side of described the first cavity.
Be arranged on the sealant 56 on the described cover layer 54, be used for sealing the hatch frame of described cover layer 54, wherein said the first cavity and the second cavity form sealed cavity, described MEMS structure 52 can be movable in described sealed cavity, be formed with hatch frame on described cover layer 54 and the described sealant 56, described hatch frame is used for the electricity isolation.
Of particular note, described electrode layer 53, cover layer 54 and sealant 56 all are epitaxially grown polysilicon layers, and doping type is identical.Position and the separation layer 55 of the hatch frame on described cover layer 54 and the described sealant 56 align, wherein separation layer 55 refers to the part between electrode layer 53 and cover layer 54, has realized simultaneously like this electricity isolation of described electrode layer 205 different pieces at the seal that guarantees not destroy described sealed cavity.
Be arranged on the insulating barrier 57 on the described sealant 56, described sealant 56 and insulating barrier 57 have consisted of the hermetically-sealed construction of device.
Be arranged on the metal lead wire 58 on the described insulating barrier 57, it is used for connecting external control circuit.
The embodiment of the invention seals the cavity structure of MEMS device with epitaxially grown polysilicon, this so that in the sealed cavity of MEMS device remaining gas take hydrogen as main, because hydrogen molecule is minimum, so only surplus remaining hydrogen almost all spreads out, realized pressing the Vacuum Package of millitorr level in the process annealing process.
Notice that above-mentioned only is preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that to the invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious variations, readjust and substitute and can not break away from protection scope of the present invention.Therefore, although by above embodiment the present invention has been carried out comparatively detailed explanation, the present invention is not limited only to above embodiment, in the situation that does not break away from the present invention's design, can also comprise more other equivalent embodiment, and scope of the present invention is determined by appended claim scope.
Claims (13)
1. the MEMS device making method of an integrated wafer-level vacuum packaged is characterized in that, may further comprise the steps:
Form the MEMS structure at the monocrystalline silicon wafer crystal substrate;
Form the first sacrifice layer in described MEMS structure;
Form patterned electrode layer at described the first sacrifice layer;
Form the second sacrifice layer at described patterned electrode layer;
Form sealed cavity at described monocrystalline silicon wafer crystal substrate, wherein said sealed cavity is positioned at MEMS structure below, and described sealed cavity is by the 3rd sacrifice layer sealing that is formed on described the second sacrifice layer;
Graphical described the second sacrifice layer and the 3rd sacrifice layer form hatch frame at described the second sacrifice layer and the 3rd sacrifice layer;
Form cover layer at described patterned the 3rd sacrifice layer, described cover layer and described electrode layer are connected with opening on the 3rd sacrifice layer by described the second sacrifice layer;
Graphical described cover layer, form hatch frame at described cover layer, and remove the part-structure of the part-structure of described the first sacrifice layer, described the second sacrifice layer and the part-structure of described the 3rd sacrifice layer by described tectal hatch frame, make the MEMS structure obtain discharging;
Form hermetically-sealed construction at described cover layer, be useful on the hatch frame of Metal Contact at described hermetically-sealed construction;
Form metal lead wire at described hermetically-sealed construction;
Process annealing.
2. the method for claim 1 is characterized in that, the crystal orientation of described monocrystalline silicon wafer crystal substrate is＜111 〉.
3. the method for claim 1, it is characterized in that, form the first sacrifice layer in described MEMS structure and also comprise graphical described the first sacrifice layer, obtain hatch frame at described the first sacrifice layer, the hatch frame of wherein said the first sacrifice layer is used for determining the anchor station of described MEMS structure.
4. the method for claim 1 is characterized in that, forms sealed cavity at described monocrystalline silicon wafer crystal substrate and comprises:
Form at least one at described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate and be communicated with the opening of described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, be used for the described monocrystalline silicon wafer crystal substrate of expose portion;
By described opening, form a cavity at described monocrystalline silicon wafer crystal substrate, wherein said cavity is positioned at MEMS structure below, and the method that forms cavity at described monocrystalline silicon wafer crystal substrate is the anisotropic etching method of silicon;
Form the 3rd sacrifice layer at described the second sacrifice layer, seal described opening, so that described cavity forms a sealed cavity.
5. method as claimed in claim 4 is characterized in that, forms at least one opening that is communicated with described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate at described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate and comprises:
Form at least one at described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate and be communicated with the first opening of described the first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, wherein the degree of depth of the first opening on described monocrystalline silicon wafer crystal substrate is less than the height of described MEMS structure;
Inner surface at described the first opening forms protective layer, and removes the described protective layer that is positioned at described the first opening lower surface;
Continue to form the second opening at described the first opening, wherein the first opening degree of depth on described monocrystalline silicon wafer crystal substrate and the second opening degree of depth sum are greater than the height of described MEMS structure.
6. method as claimed in claim 5 is characterized in that, the thickness of described protective layer is less than the thickness sum of the first sacrifice layer and the second sacrifice layer.
7. method as claimed in claim 6 is characterized in that, the method for removing the described protective layer that is positioned at described the first opening lower surface is the autoregistration anisotropic etching method.
8. the method for claim 1 is characterized in that, forms hermetically-sealed construction at described cover layer and comprises:
Form insulating barrier at described cover layer, graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
9. method as claimed in claim 8 is characterized in that, described electrode layer and cover layer all are epitaxially grown polysilicon layers, and doping type is identical.
10. the method for claim 1 is characterized in that, forms hermetically-sealed construction at described cover layer and comprises:
Form sealant at described cover layer, graphical described cover layer and sealant form hatch frame, and wherein said hatch frame aligns with described the second sacrifice layer and the 3rd sacrifice layer do not removed;
Form insulating barrier at described sealant, graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
11. such as claim 1 or 10 described methods, it is characterized in that described electrode layer, cover layer and sealant all are epitaxially grown polysilicon layers, and doping type is identical.
12. the MEMS device of an integrated wafer-level vacuum packaged is characterized in that, comprising:
The monocrystalline silicon wafer crystal substrate;
The MEMS structure that the described monocrystalline silicon wafer crystal substrate of etching forms;
Be arranged on the structural electrode layer of described MEMS, be used for control MEMS structure;
Be arranged on the cover layer of described electrode layer top, be formed on the first cavity between described cover layer and the described MEMS structure and be formed on described MEMS structure and described monocrystalline silicon wafer crystal substrate between the second cavity, wherein said cover layer links to each other with described electrode layer electricity, be formed with hatch frame on described cover layer and the described electrode layer, described hatch frame is used for the electricity isolation;
Be arranged on the separation layer between described monocrystalline silicon wafer crystal substrate and the cover layer, be used for sealing the side of described the first cavity;
Be arranged on described supratectal hermetically-sealed construction, be used for sealing described tectal hatch frame, wherein said the first cavity and the second cavity form sealed cavity, and described MEMS structure can be movable in described sealed cavity;
Be arranged on the metal lead wire on the described hermetically-sealed construction.
13. device as claimed in claim 12 is characterized in that, described electrode layer and cover layer all are epitaxially grown polysilicon layers, and doping type is identical.
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