GB2501307A

GB2501307A - Suspended Ge or Si-Ge semiconductor structure on mono-crystal line Si substrate

Info

Publication number: GB2501307A
Application number: GB201206913A
Authority: GB
Inventors: Vishal Ajit Shah; Maksym Myronov
Original assignee: University of Warwick
Current assignee: University of Warwick
Priority date: 2012-04-19
Filing date: 2012-04-19
Publication date: 2013-10-23
Also published as: GB201206913D0

Abstract

A semiconductor structure comprises a mono-crystalline silicon substrate 27 carrying a patterned germanium or germanium-silicon alloy layer 24 that has a patterned portion 12 suspended above the substrate, preferably at regions 25, 26 about an etched portion ii of the substrate. The method of construction may include depositing the Ge or Ge-Si layer and etching it to give side walls with <110> and <100> faces relative to a <001> Si substrate and shaping the layer such that an undercut etch of the substrate preferentially proceeds at some orientated faces rather than others. The patterned layer maybe amorphous, mono-crystalline or poly-crystalline and may comprise wires (figs 10a, 10b, 11) or a platform as patterned sheet, mesh or web ( figures 6, 6a, 7, 8, 9, 9a ). Devices may be formed on the suspended part of the Ge or SiGe layer.

Description

Semiconductor structure

Description

The present invention relates to a semiconductor structure particiflarly but not exclusively to a semiconductor structure comprising a germanium member supported on a silicon substrate.

Micromachining can be used to fabricate micromechanical systems (MEMS). One form in of micromachining is surface micromachining which uses selective etching to form suspended structures.

Micromechanical systems are commonly formed from silicon. Silicon suspended structures can be fabricated by defining a silicon structure on a sacrificial layer, such as i the buried oxide layer in silicon on insulator (501), and selectively removing the sacrificial layer under the structure using a highly-selective such as hydrofluoric (HF) acid. In some cases, the sacrificial layer is formed of a dielectric material, such as silicon dioxide (Si02) or silicon nitride (SiN) . However, a combination of s&ective etching and etch-resistant planes can be used to form suspended structures without the use of a dielectric layer using, for example, anisotropic etchants such as potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP) or tetramethylammonium hydroxide (TMAI-T).

According to a first aspect of the present invention there is provided a semiconductor structure. The semiconductor structure comprises a monocrystalilne silicon substrate.

The semiconductor structure comprises a patterned germanium ayer or silicon-germanium ahoy layer (for example comprising at least io% germanium) which includes first and second regions directly supported by the silicon substrate and a patterned member suspended between the first and second regions over an etched portion of the silicon substrate.

io The semiconductor structure can be formed more reliably using two separate etch processes. Preferably, the first etch process is a dry etch which is anisotropic and which is used to form the patterned member and the second etch process is a wet etch which is anisotropic and highly selective (i.e. silicon is etched at a much higher rate than germanium or silicon-germanium).

The patterned layer may be monocrystafline, polycrystalline or amorphous.

The patterned member may include a wire, web (or "mesh"), patterned sheet (e.g. a sheet which includes perforations) and/or a platform. The patterned sheet may include an array of perforations. The array may be a regular array, for example, a square or rectangular array of apertures. The patterned member may extend over 100 nm, over 1 jim or over 100 jim. The platform may have a width or length, or a diameter of, at least 2 pm, at least 10 jim or at least 100 pm, for example, to accommodate a plurality of devices.

The first and second regions (or "first and second anchoring regions") may be joined by a third region which is directly supported by the silicon substrate. For example, the first and second anchoring regions may form part of a frame around a window in the patterned ayer which is direcfly supported by the silicon substrate. The first and second anchoring regions may be separate. Thus, the first and second anchoring regions may provide dectrical contacts to the patterned member.

The silicon substrate may comprise a (001)-orientated substrate. The patterned member may comprise edges which are not orientated along a surface <no> direction.

The first and second regions include edges which are orientated along a surface <110> direction.

The patterned layer may be unstrained or under tensile strain. The patterned layer may have a thickness of at east 10 nm, at least 20 nm, at least 50 nm, at east 100 nm or at east 200 nm and/or may have a thickness no more than 2 pm, no more than 5 jim no more than 10 pm.

The semiconductor structure may include at least one further layer disposed on the patterned layer. The at least one further layer may provide a protective layer.

The patterned layer and/or at least one further layer disposed on the patterned layer io may be configured to provide at east one functional device. One of the further layer(s) may comprise a pcilycrystafline or amorphous thyer of germanium.

The at least one functional device may include at least one electronic device. The at least one functional device may include at least one optical and/or photonic device.

The at least one functional device may include at east one spintronic device. The at least one functional device may include at east one microdectromechanical system and/or nanoelectromechanical systems device.

According to a second aspect of the present invention there is provided a method of forming a semiconductor structure. The method may comprise providing a monocrystalline silicon substrate having a principal surface, forming a germanium layer or silicon-germanium layer directly on the principal surface, etching regions of the layer through the layer to at least the principal surface of the substrate so as to form a patterned layer which includes first and second regions which are not orientated and dimensioned for underetching and a patterned member which is orientated and dimensioned for underetching and etching the silicon substrate under the patterned member so as to form at least one suspended, patterned member.

The method may comprise providing a monocrystafline silicon substrate having a o principal surface, sdectively forming (e.g. by growing or depositing) direcfly on the principal surface a patterned thyer comprising germanium or silicon-germanium, the patterned layer including a first region which is orientated and dimensioned for underetching and a second region which is not orientated and dimensioned for underetching and etching the silicon substrate under the first region so as to form at least one suspended, patterned member.

Thus, the process can provide a controllable way of forming a suspended, patterned member. The process does not need require etching from a back surface of the substrate.

Forming the layer may comprise growing an epitaxial layer of silicon or silicon-germanium. The layer maybe graded. Selectively forming the patterned layer may comprise forming a mask on the principle surface, the mask having window(s) defining the patterned layer outline depositing or growing material, e.g. germanium or silicon-germanium, on the principal surface in the window(s). The mask may comprise a didectric, such a silicon dioxide. The mask may be removed prior to etching the silicon substrate.

The principai surface may coincides with a (ooi) lattice plane. The first and second regions may form edges with the silicon substrate which are orientated along a surface <110> lattice direction. The patterned member may forms edges with the silicon substrate which are not orientated along a surface <no> lattice direction.

The layer has a thickness, t. The patterned member may have a minimum in-plane dimension, w, which is equal to or greater than ioxt.

The suspended, patterned member may include a bar, wire, web and/or platform, or patterned sheet (e.g. perforated).

The layer may be unstrained or under tensile strain. The layer may be under compressive strain.

The method may comprise annealing the layer, for example, to remove compressive strain.

Etching the regions of the layer may comprise dry etching the regions of the germanium layer using a gas mixture which includes, for example, SF6.

Etching the substrate may comprise wet etching the substrate using an etchant, such as tetramethylammonium hydroxide.

The epitaxial germanium layer may be deposited, for example, using chemical vapour deposition, at a temperature of at least 250 °C, at least 300 DC, at least 350 °C, at least 400 DC, at east 450 DC, at least oo DC, at east 550 DC, at least 600 DC, at east 6o DC at least 700 DC or at least 750 DC. The ayer may be deposited at a temperature no more than 800 DC The method may comprise depositing a first part of the epitaxial germanium layer at a first temperature and depositing the rest of the layer at a second, higher temperature.

Growing part of the germanium layer at a lower temperature can help to provide a io smooth surface for subsequent deposition of the rest of the thyer at a higher temperature and/or can help to reduce the number of dislocations. The first temperature maybe no more than 400 °C, no more than 450 °C, no more than 500 °C or no more than 550 °C. The second temperature may be at least 550 °C, at least 6oo °C, at least 650 DC at least 700 DC, at least 750 DC or at least Boo °C. The method may further comprise, after depositing the germanium thyer, annealing the germanium layer at a temperature of at east 700 °C, at east 750 °C or at least Boo °C, and/or below 900 °C.

Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of a germanium-silicon heterostructure; Figure 2 is a schematic diagram of a germanium-silicon heterostructure having a suspended germanium member; Figures a and 3b illustrate steps during fabrication of a germanium-silicon heterostructure; Figure 4 is a schematic diagram of a chemical vapour deposition reactor; io Figures a to c ilhistrate fabrication of a structure at different stages; Figure 6 is a first scanning electron micrograph of a first stnicture; Figure 6a is a plan view of the first structLlre shown in Figure 6; Figure 7 is a second scanning electron micrograph of a first structure; Figure a is a cross section of part of the first structure shown in Figure 7 taken along is the line A-A'; Figure 8 is a third scanning dectron micrograph of a second structure; Figure 9 is a fourth scanning electron micrograph of a second structure; Figure a is a plan view of the first structure shown in Figure 9; Figure 10 is a fifth scanning electron micrograph of a third structure; Figure ba is a cross section of part of the third structure shown in Figure 10 taken along the line B-B'; Figure iob is a sixth scanning electron micrograph of a third structure; Figure 11 is a seventh scanning electron micrograph of a fourth structure; Figure 12 are temperature-dependent plots of resistivity for the fourth structure and a fifth structure providing a comparative example; Figure 13 is an eighth scanning electron micrograph of a fifth structure; Figure ia shows dimensions of perforations of the fifth structure shown in Figure i; Figures ia and 14b show dimensions and orientations which can be varied when dcsigning a structurc; and Figure 15 is a schematic diagram of a device formed on a suspended germanium member.

Referring to Figures land 2, a device is shown which comprises a (001)-orientated silicon (Si) substrate 1 having first and second opposite sides 2, 3 (herein also referred to as the "upper face" and "lower face" respectively, "upper surface" and "lower surface" respectively and "top side" and "bottom side") and a layer 4 of germanium (Ge) grown on the upper face 2 of the substrate 1. In this case, the germanium layer 4 is monocrystathne and is grown epitaxiafly on the substrate 1. The germanium layer 4 has first and second opposite sides, 6 (herein also referred to as the "upper face" and "lower face" respectively or "upper surface" and "lower surface" respectively). The device includes first and second contacts 7, 8 to the germanium layer 4 which are spaced apart on the upper surface 5 of the germanium layer 2.

Although the germanium layer 4 can be grown which is smooth and crystalline and io which has a ow defect density, the thyer 4 can include a network 9 of dislocations including threading dis'ocations 9 propagating between the upper and tower surfaces s, 6 of the germanium layer 4 and a misfit interface 92 found at the interface 10 between the silicon substrate 1 and the germanium layer 4. The dislocation network 9 is highly conductive and can provide an undesirable conductive path between the contacts 7, 8.

One solution is to reduce the density ofthreading dislocations 9. However, another solution, as shown in Figure 2, is to form a recess 11 at the upper surface 2 of the silicon substrate 1 which interrupts the misfit interface 92. This forms a suspended germanium structure (or "member") 12. As will be explained, the suspended germanium member can include one or more wires, a web (or "meshes") and/or one or more platforms.

Methods of forming a suspended germanium member and examples of structures which include suspended germanium member will now be described in more detail.

Referring to Figure a, a low-resistivity (10-25 flcm) silicon (Si) wafer 1 is shown. The wafer has a diameter of 4 inches (ioo mm) and a thickness, t1, of 525 pm. The wafer 1 is polished only on one side, namely the top side 2.

Referring to Figure 3b, an epitaxial layer 4 of germanium 4 is grown on the top side 2 of the wafer ito form a germanium-silicon heterostnuctiure 13 having an upper surface 5.

Referring also to Figure 4, the wafer 1 is placed in an ASM Epsilon 2000 reactor 17 for reduced pressure chemical vapour deposition (RP-cVD) of germanium using germane (GeH4) as a precursor gas.

As shown in Figure 4, the reactor 17 includes a quartz chamber 18 into which susceptors 19 (only one is shown) carrying a plurality of wafers (not shown) including the wafer 1 can be placed via a load lock (not shown). The wafer 1 is heated from above by a first, upper lamp arrangement 20 and from below by a second, lower lamp arrangement 21. Temperatures of the wafers 1 and susceptors 19 are monitored using thermocoup'es (not shown). Precursor gas 22 is introduced through an injector flange (not shown) and flows through the tube 18, over the wafers 1. The flow rate of precursor gas 22 is monitored using a mass flow meter (not shown). Growth product gases 23 flow out through an exhaust flange (not shown).

Prior to growth, the native oxide (not shown) on the wafer 1 is desorbed by heating the io wafers ito 1100 "C for 90 seconds.

Referring again to Figure 3b, the germanium layer 4 is grown in two stages.

First, a first germanium layer 4A (herein referred to as a seed layer) is grown at a relativdy low temperature, T1, of 400°C. The first germanium layer 4A has a thickness of about 100 nm. Then, a second germanium thyer 411 is grown at a relativdy high temperature, T2, of 670°C. The second germanium thyer 411 has a thickness of about 900 nm. The germanium layer 4 is monocrystalline and is under slight tensile strain.

The surface 5 has an rms roughness, Rq, less than 1 nm.

Another germanium-silicon heterostructure (not shown) which is the same as the germanium-silicon heterostructure 13(Figure 3b) but which has a thinner second germanium layer 411, namely 100 nm.

Referring to Figures a to c, a method of processing the germanium-silicon heterostructure 13 will now be described.

Referring in particular to Figure 5a, a layer (not shown) of 51813 photoresist having a thickness of 1.3 tm is applied by spin-coating to thc surface 5 of the germanium layer 4, is exposed using an MJB3 optical mask aligner and developed to provide a masked heterostructure (not shown). The masked heterostructure is loaded into a Corial 200 IL reactive ion etching (RIB) system (not shown) for etching.

Referring in particular to Figure 5b, a germanium mesa (or "patterned germanium layer") 24 is formed by reactive ion etching (RIE) using a mixture of 02 and SF6, 100W RF power, total gas pressure of 20 mTorr (2.67 Pa) and a total gas flow of 30 sccm at an etch rate of approximately 150 nm/s. The etch exhibits high selectivity over photoresist (not shown).

As shown in Figure 5b, a partiafly-etched heterostructure includes the silicon substrate i and a germanium mesa 24. The germanium mesa 24 includes a patterned, but unsuspended germanium member 12' in the form of a bar.

Referring in particular to Figure 5c, the partially-etched heterostructure is wet-etched in a bath of 25% wt TMAH at 85°C to form the patterned, suspended germanium io member 12. The patterned germanium member 12 is suspended between first and second regions 25, 26 of the germanium layer 24 which are still directly supported by an etched silicon substrate 27.

As shown in Figure 5c, <ioo>-orientated features are completely underetched and <iio>-orientated features eave various etch-resistant planes. The etch rate along the <ioo>-direction is approximately 0.6 JIm/mm.

The germanium-silicon heterostructure and the fabrication process hereinbefore described can be used to form a variety of different structures which include one or more suspended germanium members.

Referring to Figures 6, 6a, 7 and a, a first structure 31 is shown. Figures 6 and 7 are scanning electron micrographs of the structure 31 imaged using a beam voltage of 5 kV and a Zeiss Supra InLens backscattered electron detector.

The first structure 31 includes a patterned germanium layer (or "mesa") 32 comprising a suspended germanium structure 33 and a germanium frame 34. The germanium structure 33 and a germanium frame 34 form a single continuous, i.e. unitary, structure. The suspended gernianium stnicture 33 has the appearance of a spider's web spanning a square inner edge 35 of the germanium frame 34 having dimensions of Soo pm by 800 jim.

The suspended germanium stnicture 33 includes circular portions (or "rings") 36 and radial portions (or "arms" or "beams") 37. An innermost set of arms 37 are joined at a hub 38. The rings 36 and arms 37 are 5 pm wide and 1 pm thick, i.e. the thickness of the germanium epilayer 4 (Figure 3a). -10-

The suspended germanium structure 33 lies over a partitioned recess 39. The recess 39 is formed in the partially-etched silicon substrate 40 and is divided into four quadrants by thin silicon walls 41.

As shown in Figure 7, shadows 42 can be seen in the electron micrograph on the floor of the recess 39 cast by the rings 36 and arms 37 when illuminated by incident electrons (not shown). This confirms that the rings 36 and arms 37 are suspended.

io As shown in Figures 7 and a, arms 37 orientated along surface <110> directions are still anchored to the substrate 40 via unetched portions of the substrate 40, i.e. walls 41. The walls 41 exhibit {iii} etch planes 43 which resist underetching. Arms 37 which are orientated off surface <110> directions are underetched.

Referringto Figures 8,9 and a, a second structure 51 is shown. Figures 8 and 9 are scanning electron micrographs of the structure 51 imaged using a beam voltage of 20 kV and a Zeiss Supra InLens backscattered dectron detector.

In this case, the structure 51 is formed from a germanium-silicon heterostructure which is the same as that hereinbefore described except that a thinner germanium epilayer is grown, such that t2 = 200 nm, t2A = 100 nm and t2B = 100 nm.

The second structure 51 includes a germanium mesa 52 comprising a suspended germanium structure 53 and a germanium frame 54. The germanium stnicture 53 and a germanium frame 54 form a single continuous, i.e. unitary, structure. The suspended germanium structure 53 has the appearance of a spider's web spanning a square inner edge ss of the germanium frame 54 having dimensions of 200 pm by 200 pm.

Thc suspcndcd gcrmanium stnicturc 53 includcs circular portions (or "rings") 56 and radial portions (or "arms" or "beams") 57. An innermost set of arms 57 are joined at a square-shaped hub 8. The rings 6 and arms are 3 pm wide and 200 nm thick.

The suspended structure 52 lies over a partitioned recess. The recess is formed in the partially-etched silicon substrate 59.

-11 -The aims 57 are orientated so that they do not lie along surface <110> directions. The germanium mesa 52 is anchored to the substrate 59 by patterning the edges 55 of the frame 54 along the surface <no> axes.

The edges 55 of the frame 54 were not properly aligned along surface <no> directions thereby allowing some underetching of the frame 54 in regions 61. When viewed at a beam voltage of 20 kV, the underetched portions 6i are partially transparent.

Referring to Figures 10, ba and iob, a third structure 71 is shown. I0

In this case, the structure 71 is formed using the germanium-sflicon heterostructure having the thinner germanium epilayer i.e. t2 = 200 nm.

The third structure 71 includes a germanium mesa 72 comprising a set of suspended wires 73 and a pair of germanium pads 74. The germanium wires 73 and pads 74 are unitaiy. The wires 73 are 2 pm wide, 285 pm tong and 200 nm thick. The suspended wires 73 lie over a recess 78. The channel is formed in the partially-etched sihcon substrate 79.

As shown in Figures 10 and iob, the wires 73 are patterned along the surface <100> directions and the edges of the germanium pads 74 are patterned along the surface <110> directions.

To investigate the electrical properties of unsuspended and suspended germanium structure, van-der Pauw structures are formed.

Figure ii shows a fourth, van-der Pauw structure 91.

In this casc, thc structure 91 is formed using the germanium-silicon heterostructurc having the thicker germanium epilayer i.e. t2 = 900 nm.

The fourth structure 91 includes a germanium mesa 92 comprising a suspended germanium cross 93 and four germanium pads 94. The germanium cross 93 and pads 94 are unitary. The arms of the cross 93 are 20 pm wide and 1 pm thick.

-12 -The fifth structure (not shown) is the same as the fourth structure except that the germanium mesa is not underetched.

Contact (not shown) to the pads of the fourth and fifth structures are made by indenting the pads with a diamond scribe (not shown) so that the silicon substrate is also contacted and an InGa eutectic is applied using copper needles (not shown).

A set of van-der Pauw resistivity measurements are carried out over a range of temperature down to 10 IC using currents in the range of 20 -0.1 pA I0 Figure 12 shows plots of resistivity against temperature for the fourth structure (which includes the suspended cross) and the fifth structure (which includes the unsuspended or "on bulk" cross) From room temperature down to 150 K, conductivity is dominated by the silicon substrate in both structures. This allows conduction to be calibrated for both samples Below 100 K, carriers in the silicon substrate "freeze out".

Below 100 K and down to 30 K, the effect of suspension is observed in the resistivity shift of the two curves. Whilst there is still conduction in the dislocation network due to carrier hopping between dislocation localised states, there is also conduction within the bulk Ge. This observation is confirmed when carrier freezing out occurs in Ge belowo K and a minimal resistivity shift is observed in the fifth structure. The effect of removing most of the misfit dislocation network can now be seen in the fourth structure without bulk material effects. In this regime, the resistivity reaches a plateau below 20 IC. The difference in resistivity between the fourth and fifth structures is over two orders of magnitude. In the fourth structure, resistivity reaches a maximum of 280 2cm, whereas in the fifth structure resistivity reaches 2.5 2cm.

The values suggest that studied Ge on Si layer is an impurity semiconductor. However, RP-C\TD is a high-punty growth process and SIMS analysis shows no common impurities above the detection limit of 1X17 cm3.

-13 -In the structures hereinbefore described, the gennanium mesa generally comprise two parts, namely suspended portion(s) and anchored portion(s), i.e. portion(s) anchored to the underlying silicon substrate.

Referring to Figures 13 and isa, a fifth structure 101 is shown. The fifth structure 101 can be used a porous membrane and may be included in a fluidic circuit.

In this case, the structure 101 is formed using the germanium-silicon heterostructure having the thinner germanium epilayer i.e. t2 = 200 nm. I0

The fifth structure 101 includes a germanium mesa comprising a mesh 103 and a frame 104. The germanium mesh 103 and pads 104 are unitary. The mesh 103 includes a regular array of rectangular perforations 105 having a long sides io6 aligned along the <100> direction. The apertures have a length, w, between of 48 tm and a width, h, of about 16 tim, so that 3h = w. The mesh 103 Bes over a recess (not shown). However, w can be between 1 nm and 1ootm. In this case, a = b = c/2.

As shown in Figures 13 and isa, the wires 73 are patterned along the surface <100> directions and the edges of the germanium frame 104 is patterned along the surface <110> directions.

Figures ia and 14b show first and second types of anchored portions.

Referring to Figure ia, a structure 121 is shown which comprises a germanium mesa 122 comprising one or more suspended portions 123 and an anchored portion 124 supported by a silicon pedestal 125.

Anchored parts of the mesa 122 are formed by forming a polygon 126 (in this case a rectangle) in the germanium layer which exploits sides 126 aligned exclusive'y »=dong the surface <ho> axes. Anisotropic etching will result in formation of {113} planes which are angled at 20 degrees from a surface <no> axes.

Suspended parts of the mesa 122 are formed by extending the p&ygon 126 with sides which are not aligned along a surface <ho> axes. Preferably, the edges are aligned along a surface <100> axes.

Referring to Figure 14b, a structure 131 is shown which comprises a germanium mesa 132 comprising one or more suspended portions 133 and an anchored portion 134 supported by a sihcon pedestal 135. The anchored portion 134 comprises of a polygon 134 (in this case a square) in the germanium layer where it exploits sides 136 aligned exclusively along the surface <ho> axes.

Referring to both Figure ia and 14b, w is a user-defined patterned feature width to be underetched, L is a user-defined feature ength, t is germanium thickness, and Xi and X2 are user-defined lengths.

The maximum values of w and L generally depend on germanium thickness, t, namely: y »= ioxt (i) L «= 1425Xt (2) ER<100> is the etch rate of sflicon for a given time and temperature. a is a factor (set, for example, to 0.83) to artificially increase time for etching to ensure comp'ete underetching. h the height of the suspended feature from the underlying substrate which has a minimum of h »= w.

The time required for etching can be defined as: T = max {(w/(ER<ioo>xa)), (h/ ER<100>)} () 2S is the minimum anchor size and S is the minimum feature size from the edge of the patterned anchor. The minimum feature size can be found using: S <4XTXER<100>Xct. () The fourth structure 91 can be used as an examp'e, where t = i pm. The arms of the suspended Van-Der Pauw has a width 20 pm, i.e. w = 20 pm. The height from substrate is 20 pm, i.e. h = 20 pm The actua' underetch rate is approximately o.6 pm/mm. However, to take account of human error, an assumed underetch rate of 0.5 pm/minis used, i.e. ER<00> = 0.5 -15 -Mm/mill. Therefore, the arms require 40 mill of etching and the <113> planes underetching shows a feature of 8opm.

The minimum anchor size, S, for a 20 tm single wire, is 180 pm by 180 rIm so as to incorporate both corners on a square anchor. This assumes the wire is placed in the middle of one side of the anchor, i.e. 8o im either side of the wire.

Devices may be formed in and/or on the germanium mesa including a suspended portion. I0

Referring to Figure i, a suspended germanium pthtform 137 is provided by mesa 138 comprising a semiconductor material either unstrained or under tensile strain is shown. The suspended portion 137 is formed over a recess 139 in a silicon substrate 140. The germanium layer 138 is supported directly on the top side 141. The suspended germanium platform 137 can be fabricated using a similar process to that hereinbefore described.

A device, such as metal-oxide-semiconductor field-effect transistor (MOSFET) 144, can be formed in and on the platform 137. Thus, in the case of a germanium membrane, a germanium MOSFET can be formed.

A thin (e.g. a few nanometres) gate dielectric layer 145 is disposed on the substrate 40.

For a germanium MOSFET, the gate dielectric may comprise, for example, zirconium oxide (Zr02) which may be deposited by sputtering. However, other dielectric materials, such as silicon dioxide (SiOj, germanium oxide (GeO) or hafnium oxide (Hf02), and other deposition processes, such as CVD or atomic layer deposition (ALD), may be used. The gate dielectric layer 145 separates the substrate 40 from a gate electrode 146. The gate electrode 146 may comprise a semiconductor material, a metal or other conductive material, such as tantalum nitride (TaN). As shown in Figure 14, a seff-aligned diffusion process can be used to form doped we regions 147, 148 which provide source and drain regions. A chann& region 149 is formed under the gate didectric 145 between the source and drain regions 147, 148.

It will be appreciated that many modifications may be made to the embodiments hereinbefore described.

The patterned layer need not be formed by depositing or growing a layer and then etching the layer, but can be formed by selectively depositing or growing the patterned layer, e.g. through a patterned mask. The mask may be formed from, for example, silicon dioxide, which may be patterned using lithography and etching. The growth mask may be removed prior to etching the substrate.

The silicon substrate can have other diameters, e.g. smaller or larger, other resistivities, e.g. higher or lower, and other thicknesses, e.g. small or larger. The substrate can have an orientation other than (ooi), such as (iii) or (no). The substrate can be a Jo composite wafer, such as silicon-on-insulator (SOT) or silicon-on sapphire (SOS). The substrate may indude a surface epitaxial thyer.

Other forms of chemical vapour deposition can be used, such as plasma-enhanced chemical vapour deposition (PECVD), atmospheric pressure chemical vapour deposition (APCVD) etc. A chemical vapour deposition process need not be used. For example, molecular beam epitaxy (MBE) or atomic layer deposition (ALD) process may be used.

Other precursor gases, such as germanium tetrachloride (GeCI4), may be used.

Layers can be deposited which are doped, e.g. n-type or p-type, having a doping concentration in the range of between about ix 1016 cm3 and 1 X102° cm3 or more.

Doping need not be uniform. For example, the layers can be grown such that doping concentration varies with layer thickness.

In some examples, silicon-germanium (SiEXGeX) with a high germanium content (i.e. x »= o.i) can be used instead of germanium.

The layers actively used can be heterostructures of Si1Ge or other 111-V materials epitaxiafly grown or deposited on a germanium layer and capped with a layer of germanium.

Thicker or thinner thyers can be grown. For examp'e, the germanium layer can have a thickness of a few mon&ayers or a few tens of monolayers. The germanium layer can have a thickness of at least 5 nm, at least 10 nm, at least 20 nm, at least 50 nm, at least nm, at least 200 nm, at least 500 nm or at least 1 m or more. -17-

Other wet etchants can be used.

The substrate need not be a wafer, but can be a wafer die or chip.

Some or all of a monocrystalline layer providing a membrane may be amorphorised, for example by ion implantation, after the layer is deposited and, optionally, after the membrane is formed.

io A p&ycrystailine or amorphous thyer may be deposited on some or all of a germanium mesa after forming the suspended stnicture it is formed. Thus, a mixed form of membrane comprising a monocrystalline base and a polycrystalline or amorphous top can be formed.

Other non-semiconductor material thyers can be deposited (or formed) on some or all of the monocrystalline thyer. For exampk, a layer may be a metallization thyer or a didectric layer.

One or more of the layers need not be an inorganic material. For example, an organic material, such as organic semiconductor material or organic dielectric material may be used.

Other forms of electronic device can be formed in and/or on a membrane. Integrated circuits comprising a plurality of devices can be formed in and/or on a mesa.

Additionally or alternatively, other forms of device can be used. For example, optical devices (such as a laser, light emitting diode or modulator), photonic devices, spintronic devices and/or microelectromechanical (MEMS) or nanoelectromechanical (NEMS) devices may be formed.

The etches may be performed after devices, such as transistors, have been fabricated. A protective layer, such as a polycrystalline or amorphous thyer of germanium, may be deposited over the devices before the etching to protect the devices during the etches.

The protective layer may be removed after the etches. -18-

Claims

Claims 1. A semiconductor structure comprising: a monociystafline silicon substrate; and a patterned germanium ayer which includes first and second regions directly supported by the silicon substrate and a patterned member which is suspended between the first and second regions over an etched portion of the silicon substrate.
2. A semiconductor structure comprising: io a monocrystalline silicon substrate; and a patterned silicon-germanium layer which includes first and second regions directly supported by the silicon substrate and a patterned member which is suspended between the first and second regions over an etched portion of the silicon substrate.
3. A semiconductor structure according to claim 2, wherein the silicon-germanium layer comprises at east io% genlm]lium.
4. A semiconductor structure according to any preceding daim, wherein the patterned layer comprises monociystathne material.
5. A semiconductor structure according to any preceding claim, wherein the patterned layer comprises polyciystalline crystalline material.
6. A semiconductor structure according to any preceding claim, wherein the patterned layer comprises amorphous material.
7. A semiconductor structure according to any preceding claim, wherein the patterned member includes a wire.
8. A semiconductor structure according to any preceding daim, wherein the patterned member]lcludes a web or patterned sheet.
9. A semiconductor structure according to any preceding daim, wherein patterned member includes a platform.
10. A semiconductor structure according to any one of claims 1 to 9, wherein the first and second regions are joined by a third region which is directly supported by the silicon substrate.
11. A semiconductor structure according to claim 10, wherein the first and second regions form part of a frame around a window in the patterned layer which is directly supported by the silicon substrate.
12. A semiconductor structure according to any one of claims 1 to 9, wherein the io first and second regions are separate.
13. A semiconductor structure according to any preceding claim, wherein: the silicon substrate comprises a (ooi)-orientated substrate; the patterned member comprises edges which are not orientated along surface <110> directions.
14. A semiconductor structure according to daim 13, wherein the first and second regions include edges which are orientated along a surface <110> direction.
15. A semiconductor structure according to any preceding claim, wherein the patterned layer is unstrained or under tensile strain.
16. A semiconductor structure according to any preceding claim, wherein the patterned layer has a thickness of at least 5 nm.
17. A semiconductor structure according to any preceding claim, wherein the patterned layer has a thickness no more than 100 pm.
18. A semiconductor structure according to any preceding claim, further comprising: at least one further thyer disposed on the patterned thyer, optionally a thyer of Si1Ge and a capping ayer of germanium.
19. A semiconductor structure according to any preceding claim, wherein the patterned layer and/or at least one further layer disposed on the patterned layer is configured to provide at least one functional device.
20. A semiconductor structure according to claim 19, wherein one of the at least one further thyer comprises a p&ycrystafline or amorphous thyer of germanium.
21. A semiconductor structure according to claim 19 or 20, wherein the at least one functional device includes at least one electronic device.
22. A semiconductor structure according to claim 19, 20 or 21, wherein the at least one functional device includes at least one optical and/or photonic device. I0
23. A semiconductor structure according to daim 19, 20, 21 or 22, wherein the at least one functional device includes at least one spintronic device.
24. A semiconductor structure according to any one of claims 19 to 23, wherein the at least one functional device includes at least one microelectromechanical system and/or nanoelectromechanical systems device.
25. A method of forming a semiconductor structure comprising: providing a monocrystalline silicon substrate having a principal surface; forming a layer directly on the principal surface, the layer comprising germanium or silicon-germanium; etching regions of the layer through the layer to at least the principal surface of the substrate so as to form a patterned layer which includes a first region which is orientated and dimensioned for underetching and a second region which is not orientated and dimensioned for underetching; and etching the silicon substrate under the first region so as to form at least one suspended, patterned member.
26. A method according to daim 25, wherein the princip& surface coincides with a (ooi) lattice plane and wherein: the first region forms edges with the sihcon substrate which are not onentated along surface <no> lattice directions; and the second region forms edges with the silicon substrate which are orientated along a surface <no> lattice direction.
27. A method according to claim 25 or 26, wherein the layer has a thickness, t and wherein: the first region has a minimum in-pthne dimension, w, which is equal to or greater than ioxt.
28. A method according to any one of claims 25 to 27, wherein the suspended, patterned member indudes a bar.
29. A method according to any one of claims 25 to 28, wherein the suspended, patterned member includes a platform.
30. A method according to any one of claims 25 to 29, wherein the suspended, patterned member indudes a mesh or patterned sheet.
31. A method according to any one of claims 25 to 30, wherein the layer is under tensile strain or unstrained.
32. A method according to any one of claims 25 to 31, further comprising: annealing the layer.
33. A method according to any one of claims 25 to 32, wherein etching the regions of the layer comprises dry etching the regions of the layer.
34. A method of forming a semiconductor structure comprising: providing a monocrystalline silicon substrate having a principal surface; selectively forming a patterned layer directly on the principa' surface, the patterned ayer comprising germanium or silicon-germanium and including a first region which is orientated and dimensioned for underetching and a second region which is not orientated and dimensioned for underetching; and etching the sflicon substrate under the first region so as to form at least one suspended, patterned member.
35. A method according to daim 34, wherein sdectiv&y forming a patterned thyer comprises: forming a mask having window(s) defining the patterned layer outline; and depositing material on the forming the principal surface in the window(s). -22-
36. A method according to my one of claims 25 to 35, wherein etching the substrate comprises wet etching the substrate using an etchant.
37. A method according to daim 36, wherein the etchant comprises tetramethylammonium hydroxide.