CN103325331A - Array substrate of flat display panel - Google Patents
Array substrate of flat display panel Download PDFInfo
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- CN103325331A CN103325331A CN2013101618721A CN201310161872A CN103325331A CN 103325331 A CN103325331 A CN 103325331A CN 2013101618721 A CN2013101618721 A CN 2013101618721A CN 201310161872 A CN201310161872 A CN 201310161872A CN 103325331 A CN103325331 A CN 103325331A
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Abstract
The invention discloses an array substrate of a flat display panel. The array substrate of the flat display panel comprises a substrate, a plurality of signal lines, a plurality of first connecting wires and a plurality of second connecting wires. The substrate comprises a display area and a peripheral area, the signal lines are arranged in the display area of the substrate, the first connecting wires are arranged in the peripheral area of the substrate, one end of each first connecting wire is in electric connection with a part of signal lines, the second connecting wires are arranged on the peripheral area of the substrate, and one end of each second connecting wire is in electric connection with a part of the signal lines. The first connecting wires and the second connecting wires are defined out through patterning metal layers with similar sheet resistors in different layers, and a part of the first connecting wires and a part of the second connecting wires are partially overlapped in the vertical projection direction.
Description
Technical field
The invention relates to a kind of multiple substrate, espespecially a kind of multiple substrate of two-d display panel.
Background technology
Two-d display panel (flat display panel), for example liquid crystal display (liquid crystal display, LCD) panel, organic light-emitting diode display (organic light emitting diode display, OLED display) panel, electric slurry display panel (plasma display panel, PDP) and Field Emission Display (field emission display, FED) panel etc., owing to having thinner thickness, the main flow that becomes gradually on the market shows product.The problem that above-mentioned display panel can run into usually is: be positioned at the neighboring area and be used for the resistance of connection wire of transmission scan signal or data signals uneven and cause the not good problem of signal transmission quality.
Please refer to Fig. 1 and Fig. 2, Fig. 1 and Fig. 2 are the schematic diagram of the multiple substrate of known two-d display panel.As shown in Figure 1, the multiple substrate of known two-d display panel comprises a substrate 10, a plurality of signal line 16, a plurality of connection wires 18 and a plurality of driving chips 20.Substrate 10 comprises a viewing area 12 and a neighboring area 14.Signal line 16 is arranged in the viewing area 12 of substrate 10.Connects wire 18 and be arranged in the neighboring area 14 of substrate 10, and an end that respectively connects wire 18 is to be electrically connected with signal line 16 respectively, the other end that respectively connects wire 18 then with drive chip 20 and be electrically connected.By this, driving chip 20 can connect wire 18 and will drive signal and be sent to each signal line 16 via each.As shown in Figure 1, each connection wire 18 that drives chip 20 electric connections has symmetrical distribution, have an identical spacing t between the center c that namely respectively drives chip 20 and the connection wire 18 farthest of its electric connection, the distribution resistance that therefore respectively drives chip 20 presents the distribution of homogeneous and rule.Yet, as shown in Figure 2, if be subject to the design of display panel, the connection wire 18 that part drives chip 20 ' electric connection can't have symmetrical distribution because layout areas is not enough, that is the center c of driving chip 20 ' and the spacing t1 that is connected wire 18 farthest of its electric connection, t2 is also unequal, by the 2nd figure as can be known, spacing t1 is greater than spacing t2, therefore drive the distribution resistance distribution of chip 20 ' and drive the widely different of chip 20 ', make the transmission quality that drives signal not good, and then it is uneven to produce the block relative with the position that drives chip 20 ' on causing showing.
Summary of the invention
One of fundamental purpose of the present invention is to provide a kind of multiple substrate of display panel, causes distribution resistance difference excessive and affect the problem of display quality with the driving chip that solves asymmetric configuration.
For reaching above-mentioned purpose, the invention provides a kind of multiple substrate of display panel, it comprises that a substrate, a plurality of signal line, a plurality of the first connection wires, several the second connection wires, at least one first drive chip, and at least one second drives chip.Substrate comprises a viewing area and a neighboring area.Signal line is arranged in the viewing area of substrate.First connects wire is arranged in the neighboring area of substrate, and each first end that connects wire is to be electrically connected with signal line partly respectively.Second connects wire is arranged in the neighboring area of substrate, and each second end that connects wire is to be electrically connected with signal line partly.First connects wire is connected wire and is defined by the patterned metal layer of different layers respectively with second, and the first connection wire partly and second being connected wire and overlapping in a vertical projection direction partly.First drives chip is electrically connected with each first other end that is connected wire.Second drives chip is electrically connected with each second other end that is connected wire.
In addition, the invention provides a kind of multiple substrate of display panel, it comprises that a substrate, a plurality of signal line, a plurality of the first connection wires, a plurality of the second connection wires, at least one first drive chip and at least one second and drive chip.Substrate comprises a viewing area and a neighboring area.Signal line is to be arranged in the viewing area of substrate, and each signal line is to be arranged in parallel with each other.First connects wire is arranged in the neighboring area of substrate, and each first end that connects wire is to be electrically connected with signal line partly respectively.Second connects wire is arranged in the neighboring area of substrate, and each second end that connects wire is to be electrically connected with signal line partly.The first number that connects wire is not equal to the number of the second connection wire.First drives chip is electrically connected with each first other end that is connected wire.Second drives chip is electrically connected with each second other end that is connected wire.
Multiple substrate at display panel of the present invention, what utilization had that the patterned metal layer of the different layers of close sheet resistance defines first connects wire and second and connects the design of wire or change and respectively drive the connection wire number that chip is electrically connected, and can avoid the driving chip of asymmetric configuration to cause the excessive problem of distribution resistance difference.
Description of drawings
Fig. 1 and Fig. 2 are the schematic diagram of the multiple substrate of known two-d display panel.
Fig. 3 A is the schematic diagram of multiple substrate of the two-d display panel of first embodiment of the invention.
Fig. 3 B is the local enlarged diagram of multiple substrate of the two-d display panel of Fig. 3 A.
Fig. 4 is the schematic diagram of the multiple substrate of another of the first embodiment of the invention two-d display panel of implementing aspect.
Fig. 5 is the schematic diagram of multiple substrate of the two-d display panel of second embodiment of the invention.
Fig. 6 is the schematic diagram of the multiple substrate of another of the second embodiment of the invention two-d display panel of implementing aspect.
[primary clustering symbol description]
10 substrates, 12 viewing areas
14 neighboring areas, 16 signal line
18 connect wire 20,20 ' drives chip
C drives the position t of chip center, t1, t2 spacing
31 substrates, 32 viewing areas
34 neighboring areas, 36 signal line
38a first connects wire 38b second and connects wire
40a first drives chip 40b second and drives chip
42 adapter assemblies, 44 gate drive chips
51 substrates, 52 viewing areas
54 neighboring areas, 56 signal line
58a first connects wire 58b second and connects wire
60a first drives chip 60b second and drives chip
62 gate drive chip C drive the center of chip
S, S1, S2 spacing M1 the first metal layer
M2 the second metal level DL data line
The GL sweep trace
The multiple substrate of 30,30 ' two-d display panel
The multiple substrate of 50,50 ' two-d display panel.
Embodiment
Please refer to Fig. 3 A and Fig. 3 B.Fig. 3 A is the schematic diagram of multiple substrate of the two-d display panel of first embodiment of the invention, and Fig. 3 B is the local enlarged diagram of multiple substrate of the two-d display panel of Fig. 3 A.As shown in Figure 3A, the multiple substrate 30 of the two-d display panel of the present embodiment comprises that a substrate 31, a plurality of the first connection wires 38a, a plurality of the second connection wires 38b, at least one first drive chip 40a, at least one second and drive chip 40b and at least one the 3rd driving chip 44.Substrate 31 comprises a viewing area 32 and a neighboring area 34.Bar signal line 36 is arranged in the viewing area 32 of substrate 31.First connects wire 38a is arranged in the neighboring area 34 of substrate 31, and each first end that connects wire 38a is to be electrically connected with signal line partly 36 respectively.Second connects wire 38b is arranged in the neighboring area 34 of substrate 31, and each second end that connects wire 38b is to be electrically connected with signal line partly 36.First drives chip 40a is electrically connected with each first other end that is connected wire 38a.Second drives chip 40b is electrically connected with each second other end that is connected wire 38b.In the present embodiment, the first driving chip 40a and second drives chip 40b and can be for example membrane of flip chip (chip on film, COF), but not as limit.
Shown in Fig. 3 B, the first connection wire 38a is connected wire 38b with part second and overlaps in a vertical projection direction.First connects wire 38a, and be connected wire 38b with second be respectively by the patterned metal layer of different layers, for example the first connection wire 38a is defined by a first metal layer M1, and the second connection wire 38b is defined by one second metal level M2, and the first metal layer M1 and the second metal level M2 is better has close sheet resistance, but not as limit.In addition, signal line 36 can be connected wire 38b and be defined by the second metal level M2 equally with second, but not as limit.For example signal line 36 also can be connected wire 38a with first and defined by the first metal layer M1 equally.In the present embodiment, because signal line 36 is connected the wire that wire 38a is different layers with first, therefore first to connect wire 38a be through a plurality of adapter assemblies 42 and corresponding signal line 36 electric connections.
From the above, the present embodiment is that the patterned metal layer definition first that utilizes different layers and have a close sheet resistance connects wire 38a and is connected wire 38b with second, makes the first connection wire 38a be connected wire 38b with part second and overlaps in a vertical projection direction.Overlapping distribution design on this vertical space, can overcome the not enough restriction in plane figure zone, make simultaneously each first first connection wire 38a that drives chip 40a electric connection have symmetrical distribution, first being connected wire 38a and having an equal interval S farthest of i.e. each first center C that drives chip 40a and its electric connection, and each second drive that chip 40b is electrically connected second connect wire 38b and have symmetrical distribution, be i.e. second being connected wire 38b and also having an equal interval S farthest of each second center C that drives chip 40b and its electric connection.Therefore each first distribution resistance that drives chip 40a and each the second driving chip 40b presents the distribution of homogeneous and rule.
Please continue the 3A with reference to figure, in the present embodiment, the signal line 36 in the viewing area 32 for example be data line DL, and first drive chip 40a and second to drive chip 40b be source driving chip, and the 3rd driving chip 44 is the gate drive chip.The 3rd driving chip 44 is to be electrically connected at the end that a plurality of connect wires (not being shown among the figure), and the other end of connection wire is electrically connected at each sweep trace (not being shown among the figure).In the present embodiment, the 3rd driving chip 44 is to be arranged within the surrounding zone 34 of substrate 31, and it can have the design of gate driver on array (GOA), but is not limited to this.
Please refer to Fig. 4, Fig. 4 is the schematic diagram of the multiple substrate of another of the first embodiment of the invention two-d display panel of implementing aspect.For the different differences of implementing aspects in the clear relatively first embodiment of the invention, below be illustrated mainly for different part, and use the identical identical assembly of label mark.As shown in Figure 4, in this enforcement aspect, the signal line 36 of the multiple substrate 30 ' of two-d display panel is sweep trace GL.It is the gate drive chip that the first driving chip 36a and second drives chip 36b, and the 3rd driving chip 44 is source driving chip.First connects wire 38a is connected wire 38b and is defined by the patterned metal layer (please refer to Fig. 3 B) of different layers respectively with second, and is electrically connected at each signal line 36.And first connect wire 38a is connected wire 38b with second configuration mode with and effect as aforesaid embodiment, no longer this gives unnecessary details.In the multiple substrate of the two-d display panel of first embodiment of the invention, being defined first by the patterned metal layer of different layers connects wire 38a and is connected wire 38b with second and can be used for being electrically connected source driving chip and data line, or be electrically connected gate drive chip and sweep trace, also or simultaneously be used for being electrically connected source driving chip and data line and be electrically connected gate drive chip and sweep trace.
Please refer to Fig. 5, Fig. 5 is the schematic diagram of multiple substrate of the two-d display panel of second embodiment of the invention.As shown in Figure 5, the multiple substrate 50 of the two-d display panel of the present embodiment comprises that a substrate 51, a plurality of signal line 56, a plurality of the first connection wires 58a, a plurality of the second connection wires 58b, at least one first drive chip 60a, at least one second and drive chip 60b and at least one the 3rd driving chip 62.Substrate 51 comprises a viewing area 52 and a neighboring area 54.Signal line 56 is to be arranged in the viewing area 52 of substrate 51, and each signal line 56 is to be arranged in parallel with each other.First connects wire 58a is arranged in the neighboring area 54 of substrate 51, and each first end that connects wire 58a is to be electrically connected with signal line partly 56 respectively.Second connects wire 58b is arranged in the neighboring area 54 of substrate 51, and each second end that connects wire 58b is to be electrically connected with signal line partly 56.It should be noted that the first number that connects wire 58a is not equal to the number of the second connection wire 58b.
In the present embodiment, the first driving chip 60a is electrically connected at first to connect wire 58a, and second drives chip 60b is electrically connected at second to connect wire 58b, and the first number that connects wire 58a is different from the number of the second connection wire 58b.In the situation that layout areas deficiency, the first the second connection wire 58b that connects wire 58a and the second driving chip 60b electric connection that the design of the present embodiment still can make the first driving chip 60a be electrically connected all can reach and have symmetrical distribution, first being connected wire 58a and having an interval S 1 that equates farthest of i.e. each first center C that drives chip 60a and its electric connection, and second being connected wire 58b and also having an equal interval S 2 farthest of the center C of each the second driving chip 60b and its electric connection.
Please continue with reference to figure 5, in the present embodiment, the signal line 56 in the viewing area 52 for example is data line DL.It is source driving chip that the first driving chip 60a and second drives chip 60b, and the 3rd driving chip 62 is the gate drive chip.The 3rd driving chip 62 is to be electrically connected at the end that a plurality of connect wires (not being shown among the figure), and the other end of connection wire is electrically connected at each sweep trace (not being shown among the figure).In the present embodiment, the 3rd driving chip 62 is to be arranged within the surrounding zone 54 of substrate 51, has the design of gate driver on array (GOA), but is not limited to this.
Then, please refer to Fig. 6, Fig. 6 is the schematic diagram of the multiple substrate of another of the second embodiment of the invention two-d display panel of implementing aspect.For the different differences of implementing aspects in the clear relatively first embodiment of the invention, below be illustrated mainly for different part, and use the identical identical assembly of label mark.As shown in Figure 6, implement in the aspect at this, the signal line 56 of the multiple substrate 50 ' of two-d display panel for example is sweep trace GL, and it is the gate drive chip that the first driving chip 60a and second drives chip 60b, and the 3rd driving chip 62 is source driving chip.The first driving chip 60a and second drives chip 60b and is electrically connected at respectively first to be connected wire 58a and the second connection wire 58b, and the first number that connects wire 58a is not equal to the number of the second connection wire 58b.By above-mentioned configuration, the first the second connection wire 58b that connects wire 58a and the second driving chip 60b electric connection that the first driving chip 60a is electrically connected all can reach and have symmetrical distribution.In the multiple substrate of the two-d display panel of second embodiment of the invention, first connects wire 58a is connected data line in the viewing area 52 that wire 58b can be used for being electrically connected substrate 51 with second, or be electrically connected sweep trace in the viewing area 52 of substrate 51, also or simultaneously be used for being electrically connected data line and the sweep trace of the viewing area 52 of substrate 51.
In sum, the multiple substrate of two-d display panel of the present invention, utilization has connection wire partly overlapping design on the vertical projection direction that the patterned metal layer of the different layers of close sheet resistance defines, or change the connection wire number that respectively drives the chip electric connection, can make respectively to drive connection wire that chip is electrically connected and present symmetrically, cause distribution resistance difference excessive and affect the problem of display quality with the driving chip that solves asymmetric configuration.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (5)
1. the multiple substrate of a two-d display panel is characterized in that, comprising:
One substrate comprises a viewing area and a neighboring area;
A plurality of signal line are arranged in this viewing area of this substrate, and this each signal line is to be arranged in parallel with each other;
A plurality of first connect wires, be arranged in this neighboring area of this substrate, and respectively this first end that connects wire are to be electrically connected with this signal line of part respectively;
A plurality of the second connection wires are arranged in this neighboring area of this substrate, and respectively this second end that connects wire is and this signal line electric connection of part, and wherein this first number that connects wire is not equal to the number of this second connection wire;
At least one first drives chip, with respectively this first other end electric connection that is connected wire; And
At least one second drives chip, with respectively this second other end electric connection that is connected wire.
2. the multiple substrate of two-d display panel according to claim 1 is characterized in that: wherein this first connects wire and has symmetrical distribution.
3. the multiple substrate of two-d display panel according to claim 1 is characterized in that: wherein this second connects wire and has symmetrical distribution.
4. the multiple substrate of two-d display panel according to claim 1, it is characterized in that: wherein this signal line comprises a plurality of sweep traces, and this first to drive chip be the gate drive chip with this second driving chip.
5. the multiple substrate of two-d display panel according to claim 1, it is characterized in that: wherein this signal line comprises a plurality of data lines, and this first to drive chip be source driving chip with this second driving chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101618721A CN103325331A (en) | 2011-07-23 | 2011-07-23 | Array substrate of flat display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101618721A CN103325331A (en) | 2011-07-23 | 2011-07-23 | Array substrate of flat display panel |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110207051 Division CN102290416B (en) | 2011-07-23 | 2011-07-23 | Digit group substrate of plane display panel |
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| Publication Number | Publication Date |
|---|---|
| CN103325331A true CN103325331A (en) | 2013-09-25 |
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| CN2013101618721A Pending CN103325331A (en) | 2011-07-23 | 2011-07-23 | Array substrate of flat display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016188009A1 (en) * | 2015-05-28 | 2016-12-01 | 京东方科技集团股份有限公司 | Drive chip for driving display panel, display apparatus and drive control method |
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| CN1811540A (en) * | 2006-03-07 | 2006-08-02 | 广辉电子股份有限公司 | Display panel for reducing difference of electric resistance and capacity effect when transmitting signals and producing method thereof |
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| US20060267160A1 (en) * | 2005-05-30 | 2006-11-30 | Sanyo Epson Imaging Devices Corporation | Electro-optical device, method of manufacturing the same, and electronic apparatus |
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2011
- 2011-07-23 CN CN2013101618721A patent/CN103325331A/en active Pending
Patent Citations (4)
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| US20060267160A1 (en) * | 2005-05-30 | 2006-11-30 | Sanyo Epson Imaging Devices Corporation | Electro-optical device, method of manufacturing the same, and electronic apparatus |
| CN1746966A (en) * | 2005-10-21 | 2006-03-15 | 友达光电股份有限公司 | Display panel |
| CN1811540A (en) * | 2006-03-07 | 2006-08-02 | 广辉电子股份有限公司 | Display panel for reducing difference of electric resistance and capacity effect when transmitting signals and producing method thereof |
| CN1847965A (en) * | 2006-03-23 | 2006-10-18 | 友达光电股份有限公司 | Electronic device with fan-out block possessing homogeneous impedance |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016188009A1 (en) * | 2015-05-28 | 2016-12-01 | 京东方科技集团股份有限公司 | Drive chip for driving display panel, display apparatus and drive control method |
| US10304398B2 (en) | 2015-05-28 | 2019-05-28 | Boe Technology Group Co., Ltd. | Driver integrated circuit for driving display panel, display device and method for driving driver integrated circuit capable of providing different current intensities to different length transmission wires |
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Application publication date: 20130925 |