CN102290416B - Digit group substrate of plane display panel - Google Patents
Digit group substrate of plane display panel Download PDFInfo
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- CN102290416B CN102290416B CN 201110207051 CN201110207051A CN102290416B CN 102290416 B CN102290416 B CN 102290416B CN 201110207051 CN201110207051 CN 201110207051 CN 201110207051 A CN201110207051 A CN 201110207051A CN 102290416 B CN102290416 B CN 102290416B
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- lead
- substrate
- signal line
- display panel
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Abstract
The invention relates to a digit group substrate of a display panel, which comprises a substrate, a plurality of signal lines, a plurality of first connecting leads and a plurality of second connecting leads, wherein the substrate comprises a first display zone and a periphery zone; the signal lines are arranged in the display zone of the substrate; the first connecting leads are arranged in the periphery zone of the substrate, and one end of each first connecting lead is respectively electrically connected with parts of signal lines; the second connecting leads are arranged in the periphery zone of the substrate; one end of each second connecting lead is electrically connected with parts of signal lines; the first connecting leads and the second connecting leads are respectively defined by different layers of patterning metal layers with similar sheet resistors; and parts of first connecting leads and parts of second connecting leads are partially overlapped on the vertical projection direction.
Description
Technical field
The invention relates to a kind of multiple substrate, refer to a kind of multiple substrate of two-d display panel especially.
Background technology
Two-d display panel (flat display panel), for example liquid crystal display (liquid crystal display, LCD) panel, Organic Light Emitting Diode show (organic light emitting diode display, OLED display) panel, electric slurry display panel (plasma display panel, PDP) and Field Emission Display (field emission display, FED) panel etc., owing to have thinner thickness, the main flow that becomes gradually on the market shows product.The problem that above-mentioned display floater can run into usually is: be positioned at the neighboring area and be used for the resistance of connection lead of transmission scan signal or data signals uneven and cause the not good problem of signal transmission quality.
Please refer to Fig. 1 and Fig. 2, Fig. 1 and Fig. 2 are the schematic diagram of the multiple substrate of known two-d display panel.As shown in Figure 1, the multiple substrate of known two-d display panel comprises a substrate 10, a plurality of signal line 16, a plurality of connection leads 18 and a plurality of driving chips 20.Substrate 10 comprises a viewing area 12 and a neighboring area 14.Signal line 16 is arranged in the viewing area 12 of substrate 10.Connects lead 18 and be arranged in the neighboring area 14 of substrate 10, and an end that respectively connects lead 18 is to electrically connect with signal line 16 respectively, the other end that respectively connects lead 18 then with drive chip 20 and electrically connect.By this, driving chip 20 can connect lead 18 and will drive signal and be sent to each signal line 16 via each.As shown in Figure 1, each connection lead 18 that drives chip 20 electric connections has symmetrical distribution, have an identical spacing t between the center c that namely respectively drives chip 20 and the connection lead 18 farthest of its electric connection, the distribution resistance that therefore respectively drives chip 20 presents the distribution of homogeneous and rule.Yet, as shown in Figure 2, if be subject to the design of display floater, the connection lead 18 that part drives chip 20 ' electric connection can't have symmetrical distribution because layout areas is not enough, that is the center c of driving chip 20 ' and the spacing t1 that is connected lead 18 farthest of its electric connection, t2 is also unequal, by the 2nd figure as can be known, spacing t1 is greater than spacing t2, therefore drive the distribution resistance distribution of chip 20 ' and drive the widely different of chip 20 ', make the transmission quality that drives signal not good, and then can produce the block inequality relative with the position that drives chip 20 ' on causing showing.
Summary of the invention
One of main purpose of the present invention is to provide a kind of multiple substrate of display floater, causes distribution resistance difference excessive and influence the problem of display quality with the driving chip that solves asymmetric configuration.
For reaching above-mentioned purpose, the invention provides a kind of multiple substrate of display floater, it comprises that a substrate, a plurality of signal line, a plurality of first connection leads, several second connection leads, at least one first drive chip, and at least one second drives chip.Substrate comprises a viewing area and a neighboring area.Signal line is arranged in the viewing area of substrate.First connects lead is arranged in the neighboring area of substrate, and each first end that connects lead is to electrically connect with signal line partly respectively.Second connects lead is arranged in the neighboring area of substrate, and each second end that connects lead is to electrically connect with signal line partly.First connects lead is connected lead and is defined by the patterned metal layer of different layers respectively with second, and the first connection lead partly with partly second to be connected lead overlapping on a upright projection direction top.First drives chip electrically connects with each first other end that is connected lead.Second drives chip electrically connects with each second other end that is connected lead.
In addition, the invention provides a kind of multiple substrate of display floater, it comprises that a substrate, a plurality of signal line, a plurality of first connection leads, a plurality of second connection leads, at least one first drive chip and at least one second and drive chip.Substrate comprises a viewing area and a neighboring area.Signal line is to be arranged in the viewing area of substrate, and each signal line is to be arranged in parallel with each other.First connects lead is arranged in the neighboring area of substrate, and each first end that connects lead is to electrically connect with signal line partly respectively.Second connects lead is arranged in the neighboring area of substrate, and each second end that connects lead is to electrically connect with signal line partly.First number that connects lead is not equal to the number of the second connection lead.First drives chip electrically connects with each first other end that is connected lead.Second drives chip electrically connects with each second other end that is connected lead.
Multiple substrate at display floater of the present invention, what utilization had that the patterned metal layer of the different layers of close sheet resistor defines first connects lead and second and connects the design of lead or change and respectively drive the connection lead number that chip electrically connects, and can avoid the driving chip of asymmetric configuration to cause the excessive problem of distribution resistance difference.
Description of drawings
Fig. 1 and Fig. 2 are the schematic diagram of the multiple substrate of known two-d display panel.
Fig. 3 A is the schematic diagram of multiple substrate of the two-d display panel of first embodiment of the invention.
Fig. 3 B is the local enlarged diagram of multiple substrate of the two-d display panel of Fig. 3 A.
Fig. 4 is the schematic diagram of the multiple substrate of another of the first embodiment of the invention two-d display panel of implementing aspect.
Fig. 5 is the schematic diagram of multiple substrate of the two-d display panel of second embodiment of the invention.
Fig. 6 is the schematic diagram of the multiple substrate of another of the second embodiment of the invention two-d display panel of implementing aspect.
[primary clustering symbol description]
10 substrates, 12 viewing areas
14 neighboring areas, 16 signal line
18 connect lead 20,20 ' drives chip
C drives the position t of chip center, t1, t2 spacing
31 substrates, 32 viewing areas
34 neighboring areas, 36 signal line
38a first connects lead 38b second and connects lead
40a first drives chip 40b second and drives chip
42 adapter assemblies, 44 gate drive chips
51 substrates, 52 viewing areas
54 neighboring areas, 56 signal line
58a first connects lead 58b second and connects lead
60a first drives chip 60b second and drives chip
62 gate drive chip C drive the center of chip
S, S1, S2 spacing M1 the first metal layer
The M2 second metal level DL data line
The GL scan line
The multiple substrate of 30,30 ' two-d display panel
The multiple substrate of 50,50 ' two-d display panel.
Embodiment
Please refer to Fig. 3 A and Fig. 3 B.Fig. 3 A is the schematic diagram of multiple substrate of the two-d display panel of first embodiment of the invention, and Fig. 3 B is the local enlarged diagram of multiple substrate of the two-d display panel of Fig. 3 A.As shown in Figure 3A, the multiple substrate 30 of the two-d display panel of present embodiment comprises that a substrate 31, a plurality of first connection leads 38a, a plurality of second connection leads 38b, at least one first drive chip 40a, at least one second and drive chip 40b and at least one the 3rd driving chip 44.Substrate 31 comprises a viewing area 32 and a neighboring area 34.Bar signal line 36 is arranged in the viewing area 32 of substrate 31.First connects lead 38a is arranged in the neighboring area 34 of substrate 31, and each first end that connects lead 38a is to electrically connect with signal line partly 36 respectively.Second connects lead 38b is arranged in the neighboring area 34 of substrate 31, and each second end that connects lead 38b is to electrically connect with signal line partly 36.First drives chip 40a electrically connects with each first other end that is connected lead 38a.Second drives chip 40b electrically connects with each second other end that is connected lead 38b.In the present embodiment, first drive chip 40a and the second driving chip 40b for example can be membrane of flip chip (chip on film, COF), but not as limit.
Shown in Fig. 3 B, the first connection lead 38a is connected lead 38b with part second overlapping on a upright projection direction top.First connects lead 38a, and be connected lead 38b with second be respectively by the patterned metal layer of different layers, for example the first connection lead 38a is defined by a first metal layer M1, and the second connection lead 38b is defined by one second metal level M2, and the first metal layer M1 and the second metal level M2 is preferable has close sheet resistor, but not as limit.In addition, signal line 36 can be connected lead 38b and be defined by the second metal level M2 equally with second, but not as limit.For example signal line 36 also can be connected lead 38a with first and defined by the first metal layer M1 equally.In the present embodiment, because signal line 36 is connected the lead that lead 38a is different layers with first, therefore first to connect lead 38a be through a plurality of adapter assemblies 42 and corresponding signal line 36 electric connections.
From the above, present embodiment is that the patterned metal layer definition first that utilizes different layers and have a close sheet resistor connects lead 38a and is connected lead 38b with second, and it is overlapping on a upright projection direction top to make the first connection lead 38a be connected lead 38b with part second.Overlapping distribution design on this vertical space, can overcome the not enough restriction in plane figure zone, make each first first connection lead 38a that drives chip 40a electric connection have symmetrical distribution simultaneously, first being connected lead 38a and having an equal interval S farthest of i.e. each first center C that drives chip 40a and its electric connection, and each second drive that chip 40b electrically connects second connect lead 38b and have symmetrical distribution, be i.e. second being connected lead 38b and also having an equal interval S farthest of each second center C that drives chip 40b and its electric connection.Therefore each first distribution resistance that drives chip 40a and each second driving chip 40b presents the distribution of homogeneous and rule.
Please continue the 3A with reference to figure, in the present embodiment, the signal line 36 in the viewing area 32 for example be data wire DL, and first drive chip 40a and second to drive chip 40b be source driving chip, and the 3rd driving chip 44 is the gate drive chip.The 3rd driving chip 44 is to be electrically connected at the end that a plurality of connect leads (not being shown among the figure), and the other end of connection lead is electrically connected at each scan line (not being shown among the figure).In the present embodiment, the 3rd driving chip 44 is to be arranged within the surrounding zone 34 of substrate 31, and it can have the design of gate driver on array (GOA), but is not limited thereto.
Please refer to Fig. 4, Fig. 4 is the schematic diagram of the multiple substrate of another of the first embodiment of the invention two-d display panel of implementing aspect.For the different differences of implementing aspect in the clear relatively first embodiment of the invention, below be primarily aimed at different part and be illustrated, and use the identical identical assembly of label mark.As shown in Figure 4, in this enforcement aspect, the signal line 36 of the multiple substrate 30 ' of two-d display panel is scan line GL.It is the gate drive chip that the first driving chip 36a and second drives chip 36b, and the 3rd driving chip 44 is source driving chip.First connects lead 38a is connected lead 38b and is defined by the patterned metal layer (please refer to Fig. 3 B) of different layers respectively with second, and is electrically connected at each signal line 36.And first connect lead 38a is connected lead 38b with second configuration mode with and effect as aforesaid embodiment, no longer this gives unnecessary details.In the multiple substrate of the two-d display panel of first embodiment of the invention, being defined first by the patterned metal layer of different layers connects lead 38a and is connected lead 38b with second and can be used for electrically connecting source driving chip and data wire, or electrically connect gate drive chip and scan line, also or simultaneously be used for electrically connecting source driving chip and data wire and electrically connect gate drive chip and scan line.
Please refer to Fig. 5, Fig. 5 is the schematic diagram of multiple substrate of the two-d display panel of second embodiment of the invention.As shown in Figure 5, the multiple substrate 50 of the two-d display panel of present embodiment comprises that a substrate 51, a plurality of signal line 56, a plurality of first connection leads 58a, a plurality of second connection leads 58b, at least one first drive chip 60a, at least one second and drive chip 60b and at least one the 3rd driving chip 62.Substrate 51 comprises a viewing area 52 and a neighboring area 54.Signal line 56 is to be arranged in the viewing area 52 of substrate 51, and each signal line 56 is to be arranged in parallel with each other.First connects lead 58a is arranged in the neighboring area 54 of substrate 51, and each first end that connects lead 58a is to electrically connect with signal line partly 56 respectively.Second connects lead 58b is arranged in the neighboring area 54 of substrate 51, and each second end that connects lead 58b is to electrically connect with signal line partly 56.It should be noted that first number that connects lead 58a is not equal to the number of the second connection lead 58b.
In the present embodiment, the first driving chip 60a is electrically connected at first to connect lead 58a, and second drives chip 60b is electrically connected at second to connect lead 58b, and first number that connects lead 58a is different from the number of the second connection lead 58b.Under the situation of layout areas deficiency, the first second connection lead 58b that connects lead 58a and the second driving chip 60b electric connection that the design of present embodiment still can make the first driving chip 60a electrically connect all can reach and have symmetrical distribution, first being connected lead 58a and having an interval S 1 that equates farthest of i.e. each first center C that drives chip 60a and its electric connection, and second being connected lead 58b and also having an equal interval S 2 farthest of the center C of each second driving chip 60b and its electric connection.
Please continue with reference to figure 5, in the present embodiment, the signal line 56 in the viewing area 52 for example is data wire DL.It is source driving chip that the first driving chip 60a and second drives chip 60b, and the 3rd driving chip 62 is the gate drive chip.The 3rd driving chip 62 is to be electrically connected at the end that a plurality of connect leads (not being shown among the figure), and the other end of connection lead is electrically connected at each scan line (not being shown among the figure).In the present embodiment, the 3rd driving chip 62 is to be arranged within the surrounding zone 54 of substrate 51, has the design of gate driver on array (GOA), but is not limited thereto.
Then, please refer to Fig. 6, Fig. 6 is the schematic diagram of the multiple substrate of another of the second embodiment of the invention two-d display panel of implementing aspect.For the different differences of implementing aspect in the clear relatively first embodiment of the invention, below be primarily aimed at different part and be illustrated, and use the identical identical assembly of label mark.As shown in Figure 6, implement in the aspect at this, the signal line 56 of the multiple substrate 50 ' of two-d display panel for example is scan line GL, and it is the gate drive chip that the first driving chip 60a and second drives chip 60b, and the 3rd driving chip 62 is source driving chip.The first driving chip 60a and second drives chip 60b and is electrically connected at first respectively to be connected lead 58a and the second connection lead 58b, and first number that connects lead 58a is not equal to the number of the second connection lead 58b.By above-mentioned configuration, the first second connection lead 58b that connects lead 58a and the second driving chip 60b electric connection that the first driving chip 60a electrically connects all can reach and have symmetrical distribution.In the multiple substrate of the two-d display panel of second embodiment of the invention, first connects lead 58a is connected data wire in the viewing area 52 that lead 58b can be used for electrically connecting substrate 51 with second, or electrically connect scan line in the viewing area 52 of substrate 51, also or simultaneously be used for electrically connecting data wire and the scan line of the viewing area 52 of substrate 51.
In sum, the multiple substrate of two-d display panel of the present invention, utilization has connection lead that the patterned metal layer of the different layers of close sheet resistor defines in the overlapping design in upright projection direction top, or change the connection lead number that respectively drives the chip electric connection, can make respectively to drive the connection lead that chip electrically connects and present symmetrical distribution, cause distribution resistance difference excessive and influence the problem of display quality with the driving chip that solves asymmetric configuration.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (4)
1. the multiple substrate of a two-d display panel is characterized in that, comprising:
One substrate comprises a viewing area and a neighboring area;
A plurality of signal line are arranged in this viewing area of this substrate;
A plurality of first connect leads, be arranged in this neighboring area of this substrate, and respectively this first end that connects lead are to electrically connect with this signal line of part respectively;
A plurality of second connection leads, be arranged in this neighboring area of this substrate, and respectively this second end that connects lead is that this signal line with part electrically connects, wherein this first connects lead and second is connected lead and is defined by the patterned metal layer of different layers respectively with this, and this first connection lead partly second to be connected lead overlapping on a upright projection direction top with partly this;
At least one first drives chip, with respectively this first other end electric connection that is connected lead; And
At least one second drives chip, with respectively this second other end electric connection that is connected lead.
2. the multiple substrate of two-d display panel according to claim 1, it is characterized in that: wherein this signal line comprises a plurality of scan lines.
3. the multiple substrate of two-d display panel according to claim 1, it is characterized in that: wherein this signal line comprises a plurality of data wires.
4. the multiple substrate of two-d display panel according to claim 1, it is characterized in that: more comprise a plurality of adapter assemblies, wherein first to be connected lead be that patterned metal layer by different layers is defined to this signal line with this, and respectively this first to connect lead be to see through this adapter assembly and corresponding this signal line electric connection respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110207051 CN102290416B (en) | 2011-07-23 | 2011-07-23 | Digit group substrate of plane display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110207051 CN102290416B (en) | 2011-07-23 | 2011-07-23 | Digit group substrate of plane display panel |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013101618721A Division CN103325331A (en) | 2011-07-23 | 2011-07-23 | Array substrate of flat display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102290416A CN102290416A (en) | 2011-12-21 |
| CN102290416B true CN102290416B (en) | 2013-07-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110207051 Expired - Fee Related CN102290416B (en) | 2011-07-23 | 2011-07-23 | Digit group substrate of plane display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109166870B (en) * | 2018-09-17 | 2020-04-28 | 武汉华星光电半导体显示技术有限公司 | Display panel circuit structure and display panel |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100432763C (en) * | 2005-07-15 | 2008-11-12 | 中华映管股份有限公司 | Display-device and thin-film packing structure |
| CN101427290B (en) * | 2006-07-20 | 2011-06-01 | 日立等离子显示器股份有限公司 | Plasma display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104345512A (en) * | 2009-02-16 | 2015-02-11 | 夏普株式会社 | Tft array substrate, and liquid crystal display panel |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100432763C (en) * | 2005-07-15 | 2008-11-12 | 中华映管股份有限公司 | Display-device and thin-film packing structure |
| CN101427290B (en) * | 2006-07-20 | 2011-06-01 | 日立等离子显示器股份有限公司 | Plasma display device |
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| Publication number | Publication date |
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| CN102290416A (en) | 2011-12-21 |
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Granted publication date: 20130717 Termination date: 20200723 |