CN104614887A - Array substrate, liquid crystal display panel and liquid crystal display device - Google Patents
Array substrate, liquid crystal display panel and liquid crystal display device Download PDFInfo
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- CN104614887A CN104614887A CN201510053835.8A CN201510053835A CN104614887A CN 104614887 A CN104614887 A CN 104614887A CN 201510053835 A CN201510053835 A CN 201510053835A CN 104614887 A CN104614887 A CN 104614887A
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- wire
- conductive layer
- array base
- base palte
- liquid crystal
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides an array substrate, a liquid crystal display panel and a liquid crystal display device. The array substrate comprises a display area and a plurality of drive chips, wherein the display area is formed by a plurality of data lines and a plurality of scanning lines in a staggered mode, and the drive chips are used for providing data signals for the data lines and providing scanning signals for the scanning lines and connected with the data lines and the scanning lines through wires. Conductive layers are arranged on the wires in the preset area, wherein the preset area is an area where the lengths of the wires are larger than a preset value. According to the array substrate, the liquid crystal display panel and the liquid crystal display device, the conductive layers are arranged on the wires with larger lengths, and therefore impedance differences between the wires are reduced, and the display effect is improved.
Description
Technical field
The present invention relates to field of display, particularly relate to array base palte, display panels and device.
Background technology
Along with display panels is from high definition to full HD, then arrive the development of Extra-low Dispersion, more and more higher to the requirement of display effect.But current display panels exists block aberration, illustrate the reason forming block aberration below in conjunction with accompanying drawing.Fig. 1 is the structural representation of the array base palte of prior art, and as shown in Figure 1, it comprises viewing area 10 and multiple driving chip 12, and viewing area 10 comprises a plurality of data lines 11 or multi-strip scanning line 14; Driving chip 12 can provide data-signal to described data line 11 and provide sweep signal to described sweep trace 14; Each described driving chip 12 is connected with described data line 11 and described sweep trace 14 by wire.
Under normal circumstances, the structure in the cross section of wire 13 is layer structure, and this layer structure as shown in Figure 2, comprises the first metal layer 18, insulation course 15, passivation layer 16, second metal level 17.Wire becomes fan row arrangement (Fanout), but such arrangement makes the length difference of the length of outer peripheral areas wire and zone line wire apart from increasing, impedance and RC delay difference also increasing, at the wire that two adjacent driven chip periphery regions are connected with viewing area, because impedance is comparatively large and RC delay is comparatively serious, therefore corresponding with the wire of outer peripheral areas viewing area easily forms block aberration.
Therefore, be necessary to provide a kind of array base palte, display panels and device, to solve the problem existing for prior art.
Summary of the invention
The object of the present invention is to provide a kind of array base palte, display panels and device, to solve the resistance difference of existing display panels due to wire, easily occur the technical matters of block aberration.
For solving the problem, the invention provides a kind of array base palte, it comprises:
Viewing area, is staggered to form by a plurality of data lines and multi-strip scanning line;
Multiple driving chip, for providing data-signal and providing sweep signal to described sweep trace to described data line; Each described driving chip is connected with described data line and described sweep trace by wire;
Wherein on the described wire of predeterminable area, be provided with conductive layer, described predeterminable area is the region that the length of described wire is greater than preset value.
In array base palte of the present invention, the material of described conductive layer is tin indium oxide or metal.
In array base palte of the present invention, described wire is provided with two-layer or two-layer above conductive layer.
In array base palte of the present invention, the number of plies of described conductive layer is set according to the difference between the length of described wire and preset value.
In array base palte of the present invention, the thickness of described conductive layer is arranged according to the length of described wire.
The present invention also provides a kind of display panels, and it comprises:
Color membrane substrates;
Liquid crystal layer, between described color membrane substrates and array base palte; And
Described array base palte, is oppositely arranged with described color membrane substrates; It comprises:
Viewing area, is staggered to form by a plurality of data lines and multi-strip scanning line;
Multiple driving chip, for providing data-signal and providing sweep signal to described sweep trace to described data line; Each described driving chip is connected with described data line and described sweep trace by wire;
Wherein on the described wire of predeterminable area, be provided with conductive layer, described predeterminable area is the region that the length of described wire is greater than preset value.
In display panels of the present invention, the material of described conductive layer is tin indium oxide or metal.
In display panels of the present invention, described wire is provided with two-layer or two-layer above conductive layer.
In display panels of the present invention, the number of plies of described conductive layer is set according to the difference between the length of described wire and described preset value.
The present invention also provides a kind of liquid crystal indicator, and it comprises backlight module and display panels;
Wherein display panels comprises:
Color membrane substrates;
Liquid crystal layer, between described color membrane substrates and array base palte; And
Described array base palte, is oppositely arranged with described color membrane substrates; It comprises:
Viewing area, is staggered to form by a plurality of data lines and multi-strip scanning line;
Multiple driving chip, for providing data-signal and providing sweep signal to described sweep trace to described data line; Each described driving chip is connected with described data line and described sweep trace by wire;
Wherein on the described wire of predeterminable area, be provided with conductive layer, described predeterminable area is the region that the length of described wire is greater than preset value.
Array base palte of the present invention, display panels and device, by arranging one deck conductive layer on the wire that length is longer, thus reducing the resistance difference between wire, reducing block aberration, improve display effect.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below:
Accompanying drawing explanation
Fig. 1 is the structural representation of the array base palte of prior art;
Fig. 2 is the cross-sectional view of the wire of prior art;
Fig. 3 is the structural representation of array base palte of the present invention;
Fig. 4 is the cross-sectional view of wire of the present invention.
Embodiment
The explanation of following embodiment is graphic with reference to what add, can in order to the specific embodiment implemented in order to illustrate the present invention.The direction term that the present invention mentions, such as " on ", D score, "front", "rear", "left", "right", " interior ", " outward ", " side " etc., be only the direction with reference to annexed drawings.Therefore, the direction term of use is in order to illustrate and to understand the present invention, and is not used to limit the present invention.
In the drawings, the unit that structure is similar represents with identical label.
Please refer to Fig. 3, Fig. 3 is the structural representation of array base palte of the present invention;
Array base palte of the present invention, as shown in Figure 3, it comprises viewing area 10 and multiple driving chip 12, and described viewing area 10 is staggered to form by a plurality of data lines 11 and multi-strip scanning line 14; Multiple driving chip 12, for providing data-signal and providing sweep signal to described sweep trace 14 to described data line 11; Each described driving chip is connected with described data line 11 and described sweep trace 14 by wire; The total number of described wire 13,20 is equal with the total number of described data line and described sweep trace.
Described viewing area 10 also can comprise thin film transistor (TFT) (not shown), and described thin film transistor (TFT) comprises grid, source electrode, drain electrode.The grid of described thin film transistor (TFT) connects described sweep trace 14, and the source electrode of described thin film transistor (TFT) connects described data line 11.Described viewing area also can comprise multiple pixel cell, and described pixel cell can comprise main pixel region or sub-pixel area.The brightness of described main pixel region is greater than the brightness of described sub-pixel area.Described viewing area also comprises pixel electrode.
The region that the length of described wire is greater than preset value is called predeterminable area, for example in all conducting, the length of described wire 20 is greater than preset value, the region be made up of described wire 20 is predeterminable area, described preset value can set according to the size of panel, preset value described in the panel of different size is different, the described wire 20 of described predeterminable area is provided with conductive layer, namely the structure in the cross section of described wire 20 is layer structure, this layer structure comprises the first metal layer 18, insulation course 15, passivation layer 16, second metal level 17 and conductive layer 21.
In described the first metal layer 18, the part corresponding with described viewing area may be used for the grid or the sweep trace 14 that form described thin film transistor (TFT).In described second metal level 17, the part corresponding with described viewing area may be used for being formed the source electrode of described thin film transistor (TFT) or drain electrode or data line 11.Described insulation course 15 may be used for making gate insulation layer.
Now described wire 20 comprises two metal layers and one deck conductive layer, be equivalent to 3 resistor coupled in parallel, thus the resistance of original wire can be reduced, the resistance of the wire of predeterminable area is reduced, the resistance difference (such as the resistance difference between wire 20 and wire 13) of further minimizing outer peripheral areas and inside region wire, avoids occurring block aberration.
Certainly, the described wire 20 of described predeterminable area also can arrange plurality of conductive layers.Also passivation layer is provided with between adjacent two conductive layers, now described wire 20 is equivalent to multiple resistor coupled in parallel, thus the resistance of described wire 20 can be reduced further, and the conductive layer of the different number of plies can be set according to the length difference of described wire, to make the resistance difference between each conductive layer less, length by described wire compares with described preset value, the wire that difference is larger, and the number of plies arranging conductive layer is more.
Preferably, the material of described conductive layer 21 can be metal.Now described wire 20 has three-layer metal structure, be equivalent to the resistance that 3 resistor coupled in parallel can reduce original wire, therefore the resistance of the wire of predeterminable area is made to reduce, further minimizing outer peripheral areas (length of outer peripheral areas wire is longer) and the resistance difference of zone line wire, avoid occurring block aberration.
Preferably, the material of described conductive layer 21 is tin indium oxide.Due at edge, described viewing area, the place that wire is connected with data line and sweep trace, also be provided with the via hole connecting described the first metal layer or described second metal level, so that described wire is electrically connected sweep trace or data line, in described via hole, be filled with transparency conducting layer, the material of described transparency conducting layer can be tin indium oxide, time therefore the material of conductive layer 21 is identical with the material of transparency conducting layer, just save processing procedure operation, thus reduce production cost.
Preferably, described driving chip 12 can be source drive chip or grid driving chip.When described driving chip 12 is grid driving chip, be connected with described sweep trace 14.When described driving chip 12 is source drive chip, be connected with described data line 11.Farthest reduce the difference of the input signal of every bar sweep trace or data line in viewing area, better display effect can be obtained.
Preferably, the thickness of described conductive layer 21 is arranged according to the length of described wire, because the conductor length the closer to the most edge of each driving chip in predeterminable area is longer, the resistance difference of wire is also larger, because resistance is relevant with thickness, the larger resistance of thickness is less, therefore the wire that length is longer, makes thicker conductive layer thereon, can reduce resistance difference better, also can avoid making plurality of conductive layers simultaneously, save processing procedure operation.
Array base palte of the present invention, by arranging conductive layer on the wire that length is longer, thus reducing the resistance difference between wire, reducing block aberration, improve display effect.
The present invention also provides a kind of display panels, and it comprises: color membrane substrates, liquid crystal layer, array base palte; Described liquid crystal layer is between described color membrane substrates and described array base palte; Described array base palte, is oppositely arranged with described color membrane substrates; The baseplate material of described array base palte and described color membrane substrates can be glass substrate or pliability plastic base, and described color membrane substrates can comprise red color film, green tint film, blue color film.Described color membrane substrates also can comprise black matrix" and public electrode.
Composition graphs 3, it comprises viewing area 10 and multiple driving chip 12, and described viewing area 10 is staggered to form by a plurality of data lines 11 and multi-strip scanning line 14; Multiple driving chip 12, for providing data-signal and providing sweep signal to described sweep trace 14 to described data line 11; Each described driving chip is connected with described data line 11 and described sweep trace 14 by wire; The total number of described wire 13,20 is equal with the total number of described data line and described sweep trace.
Described viewing area 10 also can comprise thin film transistor (TFT) (not shown), and described thin film transistor (TFT) comprises grid, source electrode, drain electrode.The grid of described thin film transistor (TFT) connects described sweep trace 14, and the source electrode of described thin film transistor (TFT) connects described data line 11.Described viewing area also can comprise multiple pixel cell, and described pixel cell can comprise main pixel region or sub-pixel area.The brightness of described main pixel region is greater than the brightness of described sub-pixel area.Described viewing area also comprises pixel electrode.
The region that the length of described wire is greater than preset value is called predeterminable area, for example in all conducting, the length of described wire 20 is greater than preset value, the region be made up of described wire 20 is predeterminable area, described preset value can set according to the size of panel, preset value described in the panel of different size is different, the described wire 20 of described predeterminable area is provided with conductive layer, namely the structure in the cross section of described wire 20 is layer structure, this layer structure comprises the first metal layer 18, insulation course 15, passivation layer 16, second metal level 17 and conductive layer 21.
In described the first metal layer 18, the part corresponding with described viewing area may be used for the grid or the sweep trace 14 that form described thin film transistor (TFT).In described second metal level 17, the part corresponding with described viewing area may be used for being formed the source electrode of described thin film transistor (TFT) or drain electrode or data line 11.Described insulation course 15 may be used for making gate insulation layer.
Now described wire 20 comprises two metal layers and one deck conductive layer, be equivalent to 3 resistor coupled in parallel, thus the resistance of original wire can be reduced, the resistance of the wire of predeterminable area is reduced, the resistance difference (such as the resistance difference between wire 20 and wire 13) of further minimizing outer peripheral areas and inside region wire, avoids occurring block aberration.
Certainly on the described wire 20 of described predeterminable area, plurality of conductive layers is provided with.Also passivation layer is provided with between adjacent two conductive layers, now described wire 20 is equivalent to multiple resistor coupled in parallel, thus the resistance of described wire 20 can be reduced further, and the conductive layer of the different number of plies can be set according to the length difference of described wire, to make the resistance difference between each conductive layer less, length by described wire compares with described preset value, the wire that difference is larger, and the number of plies of the conductive layer of setting is more.
Preferably, the material of described conductive layer 21 can be metal.Now described wire 20 has three-layer metal structure, be equivalent to the resistance that 3 resistor coupled in parallel can reduce original wire, therefore the resistance of the wire of predeterminable area is made to reduce, further minimizing outer peripheral areas (length of outer peripheral areas wire is longer) and the resistance difference of zone line wire, avoid occurring block aberration.
Preferably, the material of described conductive layer 21 is tin indium oxide.Due at edge, described viewing area, the place that wire is connected with data line and sweep trace, also be provided with the via hole connecting described the first metal layer or described second metal level, so that described wire is electrically connected sweep trace or data line, in described via hole, be filled with transparency conducting layer, the material of described transparency conducting layer can be tin indium oxide, time therefore the material of conductive layer 21 is identical with the material of transparency conducting layer, just save processing procedure operation, thus reduce production cost.
Preferably, described driving chip 12 can be source drive chip or grid driving chip.When described driving chip 12 is grid driving chip, be connected with described sweep trace 14.When described driving chip 12 is source drive chip, be connected with described data line 11.Farthest reduce the difference of the input signal of every bar sweep trace or data line in viewing area, better display effect can be obtained.
Preferably, the thickness of described conductive layer 21 is arranged according to the length of described wire, because the conductor length the closer to the most edge of each driving chip in predeterminable area is longer, the resistance difference of wire is also larger, because resistance is relevant with thickness, the larger resistance of thickness is less, therefore the wire that length is longer, makes thicker conductive layer thereon, can reduce resistance difference better, also can avoid making plurality of conductive layers simultaneously, save processing procedure operation.
Display panels of the present invention, by arranging conductive layer on the wire that length is longer, thus reducing the resistance difference between wire, reducing block aberration, improve display effect.
The present invention also provides a kind of liquid crystal indicator, and it comprises display panels and backlight module.Described display panels is arranged relative to backlight module, this backlight module can be side-light type (side Lighting) backlight module or straight-down negative light inlet (BottomLighting) backlight module, to provide backlight to display panels.The brightness of backlight module is adjustable.
Described display panels comprises: color membrane substrates, liquid crystal layer, array base palte; Described liquid crystal layer is between described color membrane substrates and described array base palte; Described array base palte, is oppositely arranged with described color membrane substrates; The baseplate material of described array base palte and described color membrane substrates can be glass substrate or pliability plastic base, and described color membrane substrates can comprise red color film, green tint film, blue color film.Described color membrane substrates also can comprise black matrix" and public electrode.
Described array base palte comprises:
Viewing area, is staggered to form by a plurality of data lines and multi-strip scanning line;
Multiple driving chip, for providing data-signal and providing sweep signal to described sweep trace to described data line; Each described driving chip is connected with described data line and described sweep trace by wire;
The described wire of predeterminable area is provided with conductive layer, and wherein said predeterminable area is the region that the length of described wire is greater than preset value.
Display panels of the present invention or liquid crystal indicator can adopt above-mentioned any one array base palte, in view of described array base palte describes existing above, not repeat them here.
Display panels of the present invention and device, by arranging conductive layer on the wire that length is longer, thus reducing the resistance difference between wire, reducing block aberration, improve display effect.
In sum; although the present invention discloses as above with preferred embodiment; but above preferred embodiment is also not used to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; all can do various change and retouching, the scope that therefore protection scope of the present invention defines with claim is as the criterion.
Claims (10)
1. an array base palte, is characterized in that, comprising:
Viewing area, is staggered to form by a plurality of data lines and multi-strip scanning line;
Multiple driving chip, for providing data-signal and providing sweep signal to described sweep trace to described data line; Each described driving chip is connected with described data line and described sweep trace by wire;
Wherein on the described wire of predeterminable area, be provided with conductive layer, described predeterminable area is the region that the length of described wire is greater than preset value.
2. array base palte according to claim 1, is characterized in that,
The material of described conductive layer is tin indium oxide or metal.
3. array base palte according to claim 1, is characterized in that,
Described wire is provided with two-layer or two-layer above conductive layer.
4. array base palte according to claim 3, is characterized in that,
The number of plies of described conductive layer is set according to the difference between the length of described wire and described preset value.
5. array base palte according to claim 1, is characterized in that,
The thickness of described conductive layer is arranged according to the length of described wire.
6. a display panels, is characterized in that, comprising:
Color membrane substrates;
Liquid crystal layer, between described color membrane substrates and array base palte; And
Described array base palte, is oppositely arranged with described color membrane substrates; It comprises:
Viewing area, is staggered to form by a plurality of data lines and multi-strip scanning line;
Multiple driving chip, for providing data-signal and providing sweep signal to described sweep trace to described data line; Each described driving chip is connected with described data line and described sweep trace by wire;
Wherein on the described wire of predeterminable area, be provided with conductive layer, described predeterminable area is the region that the length of described wire is greater than preset value.
7. display panels according to claim 6, is characterized in that,
The material of described conductive layer is tin indium oxide or metal.
8. display panels according to claim 6, is characterized in that,
Described wire is provided with two-layer or two-layer above conductive layer.
9. display panels according to claim 8, is characterized in that,
The number of plies of described conductive layer is set according to the difference between the length of described wire and described preset value.
10. a liquid crystal indicator, is characterized in that, comprises backlight module and display panels;
Wherein display panels comprises:
Color membrane substrates;
Liquid crystal layer, between described color membrane substrates and array base palte; And
Described array base palte, is oppositely arranged with described color membrane substrates; It comprises:
Viewing area, is staggered to form by a plurality of data lines and multi-strip scanning line;
Multiple driving chip, for providing data-signal and providing sweep signal to described sweep trace to described data line; Each described driving chip is connected with described data line and described sweep trace by wire;
Wherein on the described wire of predeterminable area, be provided with conductive layer, described predeterminable area is the region that the length of described wire is greater than preset value.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510053835.8A CN104614887A (en) | 2015-02-02 | 2015-02-02 | Array substrate, liquid crystal display panel and liquid crystal display device |
| PCT/CN2015/072423 WO2016123797A1 (en) | 2015-02-02 | 2015-02-06 | Array substrate, liquid crystal display panel and apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510053835.8A CN104614887A (en) | 2015-02-02 | 2015-02-02 | Array substrate, liquid crystal display panel and liquid crystal display device |
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| CN104614887A true CN104614887A (en) | 2015-05-13 |
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| CN201510053835.8A Pending CN104614887A (en) | 2015-02-02 | 2015-02-02 | Array substrate, liquid crystal display panel and liquid crystal display device |
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| WO (1) | WO2016123797A1 (en) |
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| CN106125429A (en) * | 2016-08-23 | 2016-11-16 | 深圳市华星光电技术有限公司 | Display panels and liquid crystal indicator |
| KR20180024687A (en) * | 2016-08-31 | 2018-03-08 | 엘지디스플레이 주식회사 | Display panel and display device using the same |
| CN107833908A (en) * | 2017-11-29 | 2018-03-23 | 武汉天马微电子有限公司 | Special-shaped display panel and liquid crystal display device and organic electroluminescence display device and method of manufacturing same |
| CN108474987A (en) * | 2017-04-21 | 2018-08-31 | 深圳市柔宇科技有限公司 | TFT array substrate, display panel and display device |
| CN111258132A (en) * | 2020-03-31 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
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