CN206619376U - Display panel and the device comprising it - Google Patents
Display panel and the device comprising it Download PDFInfo
- Publication number
- CN206619376U CN206619376U CN201621436456.3U CN201621436456U CN206619376U CN 206619376 U CN206619376 U CN 206619376U CN 201621436456 U CN201621436456 U CN 201621436456U CN 206619376 U CN206619376 U CN 206619376U
- Authority
- CN
- China
- Prior art keywords
- line
- display panel
- metal film
- film layer
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002184 metal Substances 0.000 claims description 121
- 239000000758 substrate Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 12
- 230000000875 corresponding effect Effects 0.000 description 9
- 230000008054 signal transmission Effects 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Device this application discloses display panel and comprising it.Display panel includes multiple data line groups, and each data line group includes a plurality of data lines；Multiple multi-channel gating devices, each multi-channel gating device is electrically connected with a data line group respectively；And a plurality of clock cable and drive circuit；Multi-channel gating device is electrically connected with a plurality of clock cable, for each data line transfer data-signal of the timesharing into data line group under the control of a plurality of clock cable；Wherein, every clock cable includes connecting line and the signal wire extended in a first direction, and signal wire and connecting line are electrically connected in intersection, and connecting line is electrically connected with drive circuit；Each signal wire is arranged at same metallic diaphragm, and at least one connecting line and the different layer of the signal wire being connected electrically are set.The display panel and device comprising it can reduce layout area, be conducive to the design of narrow frame.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device comprising the same.
Background
With the development of display technology, high resolution and narrow bezel have become the development trend of display devices. In general, a display panel includes a driving chip that transmits a data signal to each of subpixels through a data line, and the subpixels perform display according to the data signal. In the existing display panel design, each data line is electrically connected with a column of sub-pixels, and each data line transmits data signals to the sub-pixels in the same column and different rows in a time-sharing manner when a picture is displayed. In a high-resolution display panel, since the number of sub-pixels is large, the number of data lines is large, and the number of ports of a driver chip is limited, it is necessary to supply signals to a plurality of data lines at a time through one port of the driver chip by using a gate circuit. The time-sharing transmission of the data signal is generally controlled by a plurality of clock signals, and the gating circuit generally includes a plurality of clock signal lines for transmitting the plurality of clock signals.
The clock signal in the above-mentioned gate circuit is usually disposed on the left and right frames of the display panel in order not to affect the design of other circuit elements and traces. However, due to the limitations of the wiring process and the reliability of the electrostatic discharge protection, the plurality of clock signal lines in the gate circuit occupy a large wiring area, which is not favorable for the design of the narrow-frame display panel.
SUMMERY OF THE UTILITY MODEL
In order to solve the problems mentioned in the background section above, the present application provides a display panel and a display device including the same.
In one aspect, the present application provides a display panel including a plurality of data line groups, each data line group including a plurality of data lines; a plurality of multiplexers, each multiplexer electrically connected to a respective one of the data line sets; and a plurality of clock signal lines and a driving circuit; the multiplexer is electrically connected with the plurality of clock signal lines and is used for transmitting data signals to each data line in the data line group in a time-sharing manner under the control of the plurality of clock signal lines; each clock signal line comprises a connecting line and a signal line extending along a first direction, the signal line and the connecting line are electrically connected at the intersection, and the connecting line is electrically connected with the driving circuit; each signal line is arranged on the same metal film layer, and at least one connecting line and the signal line electrically connected with the connecting line are arranged in different layers.
In some embodiments, the display panel includes a display area and a non-display area surrounding the display area; the non-display area comprises a first frame area and a second frame area, the first frame area, the display area and the second frame area are sequentially arranged along a second direction, and the second direction is intersected with the first direction; the signal line is located in the first frame area and/or the second frame area.
In some embodiments, the plurality of connection lines includes at least one first connection line and at least one second connection line; each first connecting line and each signal line are arranged on the first metal film layer, and each second connecting line is arranged on the second metal film layer.
In some embodiments, the first connection lines and the second connection lines are alternately arranged in the first direction.
In some embodiments, the display panel includes a substrate base, the first connecting lines have a first orthographic projection on the substrate base, and the second connecting lines have a second orthographic projection on the substrate base; at least one first orthographic projection overlaps one second orthographic projection.
In some embodiments, the number of first connection lines and second connection lines is equal; each first orthographic projection is respectively overlapped with one second orthographic projection.
In some embodiments, a first insulating layer is disposed between the first metal film layer and the second metal film layer; the first insulating layer is provided with a first through hole at a position corresponding to a cross point of the second connecting line and a signal line electrically connected with the second connecting line; the signal line and the second connection line are electrically connected to each other through the first via hole.
In some embodiments, the display panel includes a scan line metal layer and a data line metal layer; the first metal film layer is a scanning line metal layer, and the second metal film layer is a data line metal layer; or the first metal film layer is a data line metal layer, and the second metal film layer is a scanning line metal layer.
In some embodiments, the connecting line is located in the first frame region and/or the second frame region; each connecting wire is positioned on the same metal film layer.
In some embodiments, each signal line is disposed on the third metal film layer, and each connection line is disposed on the fourth metal film layer; the third metal film layer and the fourth metal film layer are different film layers.
In some embodiments, a second insulating layer is provided between the third metal film layer and the fourth metal film layer; the second insulating layer is provided with a second through hole at the intersection of the signal line and the corresponding connecting line; the signal lines and the corresponding connecting lines are electrically connected with each other through the second through holes.
In some embodiments, the display panel includes a scan line metal layer and a touch signal line metal layer; the third metal film layer is a scanning line metal layer; the fourth metal film layer is a touch signal line metal layer.
In some embodiments, the first direction is perpendicular to the second direction.
In some embodiments, the number of clock signal lines is not less than 6.
In another aspect, the present application provides a display device including the above display panel.
The application provides a display panel and display device, including multichannel gate and with be used for controlling multichannel gate to transmit data signal's clock signal line to many data lines in the data line group time sharing, every clock signal line includes signal line and connecting wire, at least one connecting wire and the signal line different layer setting rather than the electricity connection can reduce clock signal line and walk line width, be favorable to the design of narrow frame.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings in which:
FIG. 1 is a schematic structural diagram of one embodiment of a display panel according to the present application;
FIG. 2 is a schematic structural diagram of another embodiment of a display panel according to the present application;
FIG. 3A is a schematic top view illustrating a routing manner of clock signal lines in the display panel shown in FIG. 2;
FIG. 3B is a cross-sectional view of the trace pattern shown in FIG. 3A taken along line BB';
FIG. 3C is a schematic cross-sectional view of the routing shown in FIG. 3A taken along section line CC';
FIG. 4A is a schematic top view illustrating another routing manner of clock signal lines in the display panel shown in FIG. 2;
FIG. 4B is a cross-sectional view of the trace pattern shown in FIG. 4A taken along line DD';
FIG. 4C is a cross-sectional view of the trace pattern shown in FIG. 4A taken along section line EE';
FIG. 5 is a schematic structural diagram of yet another embodiment of a display panel according to the present application;
FIG. 6A is a schematic top view illustrating a routing manner of clock signal lines in the display panel shown in FIG. 5;
FIG. 6B is a cross-sectional view of the trace pattern shown in FIG. 6A taken along line FF';
fig. 7 is a schematic diagram of a display device provided in the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not limiting of the invention. It should be noted that, for convenience of description, only the relevant portions of the related inventions are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Please refer to fig. 1, which shows a schematic structural diagram of an embodiment of a display panel according to the present application. As shown in fig. 1, the display panel 100 includes a plurality of data line groups 111, 112, 113, …, 11n, a plurality of multiplexers 121, 122, 123, …, 12n, a plurality of clock signal lines 13 and a driving circuit 14, where n is a positive integer. Each data line group 111, 112, 113, …, or 11n includes a plurality of data lines 101, each multiplexer 121, 122, 123, …, 12n is electrically connected to a plurality of clock signal lines 13, each multiplexer 121, 122, 123, …, or 12n is electrically connected to one data line group 111, 112, 113, …, or 11n, respectively, and each multiplexer 121, 122, 123, …, 12n is configured to time-share data signals to each data line in the data line group 111, 112, 113, …, 11n to which it is electrically connected, under the control of the plurality of clock signal lines 13.
In the present embodiment, each clock signal line 13 includes a connection line 131 and a signal line 132 extending along a first direction, at least a portion of the connection line 131 intersects with the extending direction of the signal line 132, the signal line 132 and the connection line 131 in the same clock signal line are electrically connected at the intersection, and the connection line 131 is electrically connected to the driving circuit 14. The signal lines 132 of each clock signal line 13 are disposed on the same metal film layer, and at least one connection line 131 and the signal line 132 electrically connected thereto are disposed in different layers. That is, in each clock signal line 13, the connection line 131 and the signal line 132 of at least one clock signal line are provided in different film layers.
The display panel includes a large number of data lines. Generally, the data signals required for the respective data lines are supplied from the driving circuit 14(IC), and the number of interfaces of the driving circuit 14 is limited, and the number of interfaces for supplying the data signals can be reduced by using the multiplexer. In some optional implementations of the present embodiment, the display panel 100 further includes a plurality of data signal transmission lines 15, and each of the multiplexers 121, 122, 123, …, 12n may be electrically connected to the driving circuit 14 through one data signal transmission line 15. Each data signal transmission line 15 may transmit data signals of a plurality of data lines in one data line group corresponding to the multiplexer connected thereto in a time-sharing manner, and the multiplexer may decompose the plurality of data signals under the control of a plurality of clock signal lines and transmit the decomposed data signals to the plurality of data lines in a time-sharing manner, respectively. Each data line in the data line group may be gated by one or more clock signal lines, and when one data line is gated, the data line receives a signal transmitted by the data signal transmission line, and the connection between the other data lines in the same data line group and the data signal transmission line is disconnected. That is, the number of clock signal lines is greater than or equal to the number of data lines to which one multiplexer is connected.
Specifically, assuming that the number of data lines in each data line group is the same, in an alternative implementation, each clock signal line is used for gating one data line in each data line group, and in this case, the number of clock signal lines included in the display panel is the same as the number of data lines connected to one multiplexer. In another alternative implementation, each data line is gated under the control of two clock signal lines, and the number of the clock signal lines included in the display panel is 2 times the number of the data lines connected to one multiplexer.
As can be seen from fig. 1, in order to reduce the frame area occupied by the data signal transmission lines 15, each of the multiplexers 121, 122, 123, …, 12n needs to connect a larger number of data lines, and the number of clock signal lines required by the display panel increases accordingly. In this embodiment, the signal lines and the connecting lines of at least one of the plurality of clock signal lines 13 are disposed in different layers, and an orthographic projection of the connecting lines in the clock signal lines to a plane where the signal lines are located may at least partially overlap the signal lines, so that a wiring area occupied by the clock signal lines may be reduced compared to a wiring manner in which the signal lines and the connecting lines are disposed in the same layer. On the other hand, the wiring area of the wires in the frame is reduced, and the design of a narrow frame is facilitated.
Further, please refer to fig. 2, which shows a schematic structural diagram of another embodiment of the display panel according to the present application. As shown in fig. 2, the display panel 200 includes a display area AA ' and a non-display area (an area other than AA ' in the display panel 100 shown in fig. 2) surrounding the display area AA '. The non-display area includes a first frame area a1 and a second frame area a2, and the first frame area a1, the display area AA', and the second frame area a2 are sequentially arranged along the second direction. The second direction intersects the first direction. Optionally, the first direction and the second direction are perpendicular to each other.
The first and second bezel areas a1 and a2 may be upper and lower bezels of the display panel 200. The non-display area further includes a third frame area A3 and a fourth frame area a4, wherein the third frame area A3, the display area AA', and the fourth frame area a4 are sequentially arranged along the first direction. The third and fourth frame regions A3 and a4 may be side frames of the display panel 200.
In the present embodiment, the display panel 200 includes a plurality of data line groups 111, 112, 113, …, 11n, a plurality of multiplexers 121, 122, 123, …, 12n, and a driving circuit 14, which are the same as those of the display panel shown in fig. 1. The display panel 200 further includes a plurality of clock signal lines 23, and each clock signal line 23 includes a connection line 231 and a signal line 232 extending in the first direction. The signal lines 232 of the respective clock signal lines 23 are located in the first frame area a1 and/or the second frame area a2, and the respective connection lines 231 are also located in the first frame area a1 and/or the second frame area a 2. The side frame area of each display panel 200 is positively correlated with the area occupied by the connection line in each clock signal line 23.
Referring further to fig. 3A, a schematic top view of a clock signal line in the display panel of fig. 2 is shown. That is, a specific structure diagram of the dashed line box 2A in the display panel 200 shown in fig. 2 is shown.
As shown in fig. 3A, in a specific structure diagram 300 of the clock signal line, the connection lines 231 include at least one first connection line 311 and at least one second connection line 321. The signal line 312 electrically connected to the first connection line 311 and the signal line 322 electrically connected to the second connection line 321 both extend along the first direction and are located in the same metal film layer.
In the present embodiment, each of the first connection lines 311 and each of the signal lines 312 and 322 are disposed on the first metal film layer, and each of the second connection lines 321 is disposed on the second metal film layer.
Referring to fig. 3B and 3C, a schematic cross-sectional view along the cross-sectional line BB 'shown in fig. 3A and a schematic cross-sectional view along the cross-sectional line CC' shown in fig. 3A are respectively shown. As shown in fig. 3B, the signal line 322 electrically connected to the second connection line 321 is disposed on the first metal film layer 301. The second connection line 321 is disposed on the second metal film layer 302. Further, a first insulating layer 303 is provided between the first metal film layer 301 and the second metal film layer 302, the first insulating layer 303 is provided with a first via hole 3031 at a position corresponding to a crossing point of the second connection line 321 and the signal line 322 electrically connected to the second connection line 321, and the signal line 322 and the second connection line 321 are electrically connected to each other through the first via hole 3031. As shown in fig. 3C, the first connection line 311 and the signal line 312 electrically connected to the first connection line 311 are disposed on the first metal film 301, and the second connection line 321 is disposed on the second metal film 302. That is, the first connection line 311 and the signal lines 312 and 322 are disposed on the first metal film 301, and the second connection line 321 is disposed on the second metal film 302. First metal layer 301 and second metal layer 302 have first insulating layer 303 therebetween.
In some optional implementations of the present embodiment, the number of the clock signal lines is even, the number of the first connection lines 311 is not equal to the number of the second connection lines 321, and an orthogonal projection of any one of the second connection lines 312 to the first metal film layer does not overlap with the first connection lines 311. When designing the routing, the distance between the first connecting line 311 and the second connecting line 312 adjacent to each other in the first direction can be reduced, so as to reduce the width of the frame occupied by the plurality of clock signal lines.
In other alternative implementations of the present embodiment, as shown in fig. 3A and 3C, the first connection lines 311 and the second connection lines 321 are alternately arranged in the first direction. If the number of the clock signal lines is even, the number of the first connection lines 311 and the second connection lines 321 is equal. At this moment, two adjacent connecting wires in the first direction are respectively located on different metal film layers, and then any two adjacent connecting wires are not easy to generate signal crosstalk, so that the distance between any two adjacent connecting wires can be reduced by wiring in design, and the frame width occupied by the connecting wires in the clock signal wire can be further reduced.
Referring to fig. 4A, a schematic top view illustrating another routing manner of clock signal lines in the display panel shown in fig. 2 is shown.
As shown in fig. 4A, in a specific structure diagram 400 of the clock signal lines, the connection lines 231 include at least one first connection line 411 and at least one second connection line 421. The signal line 412 electrically connected to the first connection line 411 and the signal line 422 electrically connected to the second connection line 421 both extend along the first direction and are located in the same metal film layer.
In the present embodiment, each of the first connection lines 411 and each of the signal lines 412 and 422 are disposed on the first metal film layer, and each of the second connection lines 421 is disposed on the second metal film layer.
Referring to fig. 4B and 4C, a schematic cross-sectional view along the section line DD 'shown in fig. 4A and a schematic cross-sectional view along the section line EE' shown in fig. 4A are respectively shown. As shown in fig. 4B, the signal line 422 electrically connected to the second connection line 421 is disposed on the first metal film layer 401. The second connection line 421 is disposed on the second metal film layer 402. Further, a first insulating layer 403 is provided between the first metal film layer 401 and the second metal film layer 402, the first insulating layer 403 is provided with a first via 4031 at a position corresponding to a crossing point of the second connection line 421 and the signal line 422 electrically connected to the second connection line 421, and the signal line 422 and the second connection line 421 are electrically connected to each other through the first via 4031. As shown in fig. 4C, the first connection line 411 and the signal line 412 electrically connected to the first connection line 411 are disposed on the first metal film 401, and the second connection line 421 is disposed on the second metal film 402. That is, the first connection line 411 and the signal lines 412 and 422 are disposed on the first metal film layer 401, and the second connection line 421 is disposed on the second metal film layer 402. A first insulating layer 403 is provided between the first metal layer 401 and the second metal layer 402.
Further, the display panel in this embodiment includes a base substrate. The orthographic projection of each connecting line and each signal line onto the substrate coincides with the top view shown in fig. 4A. The first connecting line 411 has a first orthographic projection on the substrate base, and the second connecting line 421 has a second orthographic projection on the substrate base. At least one first orthographic projection overlaps one second orthographic projection. That is to say, the sum of the length of the at least one first connecting line in the first direction and the length of the second connecting line in the first direction is greater than the width of the frame occupied by the first connecting line in the first direction. According to the wiring mode, the first connecting wire and the second connecting wire are arranged in different layers, so that signal crosstalk is not easily generated between the first connecting wire and the second connecting wire, the total width of the clock signal wire is further reduced, and the frame area of the display panel is reduced.
Further, in some optional implementation manners of this embodiment, as shown in fig. 4A, the number of the first connection lines 411 and the number of the second connection lines 421 are equal, and a first orthographic projection of each first connection line 411 to the substrate base is overlapped with a second orthographic projection of one second connection line 421 to the substrate base, so that a distance between any two adjacent connection lines along the first direction can be reduced, thereby further reducing a frame area occupied by the clock signal line.
The display panel including the clock signal line shown in fig. 3A or fig. 4A may include a scan line metal layer and a data line metal layer, where the scan line on the display panel is formed on the scan line metal layer and the data line is formed on the data line metal layer. In the two routing manners described above with reference to fig. 3A, 3B, 3C and 4A, 4B, 4C, the first metal film layer may be a scan line metal layer, and the second metal film layer may be a data line metal layer; alternatively, the first metal film layer may be a data line metal layer, and the second metal film layer may be a scan line metal layer. Since each connection line and each signal line are located in the first frame area a1 or the second frame area a2 shown in fig. 2, and the data line and the scan line are usually located in the display area AA', when each connection line or each signal line is disposed in the data line metal layer or the scan line metal layer, the data line and the scan line in the display area are not affected, and the display panel can be manufactured by using the existing manufacturing process without adding an additional metal layer.
It should be noted that each data line in the display panel may be controlled by one clock signal line or controlled by 2 clock signal lines. For example, the first connection line 311 shown in fig. 3A, 3B, and 3C may be a connection line included in any one of the clock signal lines, the second connection line 321 shown in fig. 3A, 3B, and 3C may be a connection line included in any one of the clock signal lines, the first connection line 411 shown in fig. 4A, 4B, and 4C may be a connection line included in any one of the clock signal lines, and the second connection line 421 shown in fig. 4A, 4B, and 4C may be a connection line included in any one of the clock signal lines. In other words, any number of clock signal lines including the first connection line and any number of clock signal lines including the second connection line may be present in the plurality of clock signal lines.
If the plurality of clock signal lines in the display panel include a plurality of first clock signal lines and a plurality of second clock signal lines, the number of the first clock signal lines and the number of the second clock signal lines are equal, and each data line is controlled by one first clock signal line and one second clock signal line to be gated. In another alternative trace design, the first connection line 311 or 411 in the above embodiment may be a connection line in a first clock signal line, or may be a connection line in a second clock signal line, and the second connection line 321 or 421 may be a connection line in a first clock signal line, or may be a connection line in a second clock signal line. In other words, the signal lines and the connecting lines of one part of the first clock signal lines are arranged in the same layer, and the signal lines and the connecting lines of the other part of the first clock signal lines are arranged in a different layer; the signal lines and the connecting lines of one part of the second clock signal lines are arranged in the same layer, and the signal lines and the connecting lines of the other part of the second clock signal lines are arranged in different layers.
If the plurality of clock signal lines in the display panel include a plurality of first clock signal lines and a plurality of second clock signal lines, and each data line is controlled by one first clock signal line and one second clock signal line, in an alternative routing design, the first connecting line 311 or 411 in the above embodiment may be a connecting line in the first clock signal line, and the second connecting line 321 or 421 may be a connecting line in the second clock signal line. Taking the routing manner shown in fig. 3A as an example, if the number of the first clock signal lines is the same as that of the second clock signal lines, the number of the first connecting lines 311 is the same as that of the second connecting lines 321, at this time, the signal lines and the connecting lines in the first clock signal lines are arranged in the same layer, and the signal lines and the connecting lines in the second clock signal lines are arranged in different layers. Therefore, the distance between the first clock signal line and the second clock signal line for gating the same data line is smaller, the wiring design of the clock signal lines can be simplified, and the wiring area is further reduced. Similarly, the routing manner shown in fig. 4A can also simplify the routing design of the clock signal lines and reduce the routing area, thereby providing a larger routing space for each of the traces in the non-display area and reducing the frame area.
Please refer to fig. 5, which shows a schematic structural diagram of a further embodiment of a display panel according to the present application.
As shown in fig. 5, unlike the embodiment shown in fig. 2, the present embodiment provides the display panel 500 in which each clock signal line 53 includes a connection line 531 and a signal line 532 extending in the first direction. Wherein each connection line 531 and each signal line 531 are disposed in the first frame area a1 and/or the second frame area a 2.
In this embodiment, the signal lines 532 are located on the same metal film layer, the connection lines 531 are located on the same metal film layer, and at least one connection line and the signal line connected thereto are disposed in different layers, so that each signal line 532 is disposed in different layers with respect to the connection line 531 connected thereto.
In order to further optimize the routing manner of the clock signal lines, a straight line passing through any end point of the extension direction of any one of the signal lines 532 and perpendicular to the signal line 532 does not intersect with the display area AA ', and in this case, the connection lines 531 may be designed to overlap with the signal lines, and for example, the connection lines may be disposed within the extension lines of two boundary lines a1b1 and a2b2 of the display area AA' parallel to the first direction, so that the frame width of the display panel along the first direction may be reduced.
Referring to fig. 6A, a top view of a trace of the clock signal lines in the display panel shown in fig. 5 is shown. That is, a specific structure diagram of the dashed line box 5A in the display panel 500 shown in fig. 5 is shown.
As shown in fig. 6A, in a specific structure diagram 600 of the clock signal lines, each clock signal line 53 includes a connection line 531 and a signal line 532, wherein the signal line 532 extends in a first direction. Each signal line 532 is electrically connected with a corresponding connection line 531 at a crossing position.
FIG. 6B is a cross-sectional view of the trace pattern shown in FIG. 6A taken along line FF'. As shown in fig. 6B, each signal line 532 is disposed on the third metal film layer 603, each connection line 531 is disposed on the fourth metal film layer 604, and the third metal film layer 603 and the fourth metal film layer 604 are different films. Further, a second insulating layer 605 is disposed between the third metal film layer 603 and the fourth metal film layer 604. The second insulating layer 605 is provided with a second via 6051 at a crossing point of the signal line 532 and the corresponding connection line 531, and the signal line 532 and the corresponding connection line 531 are electrically connected to each other through the second via 6051.
In some optional implementation manners of this embodiment, the display panel 500 is a touch display panel, and includes a scan line metal layer and a touch signal line metal layer, where the scan line metal layer is used to form scan lines, and the touch signal line metal layer is used to form touch signal lines. The third metal film layer 603 may be a scan line metal layer, and the fourth metal film layer 604 may be a touch signal line metal layer. The display panel 500 may further include a data line metal layer for forming a data line, and the touch signal line metal layer and the data line metal layer are different film layers. As can be seen from fig. 5, the routing direction of the data line 101 is the same as the routing direction of the connection line 531, and the data line may extend from the display area AA' to the second frame area a2, in order to avoid overlapping of the connection line and the data line, the connection line and the data line may be disposed in different layers, for example, the connection line is disposed in the touch signal line metal layer in this embodiment, so that the routing area occupied by the clock signal line may be reduced, the frame size may be narrowed, and it may be ensured that the connection line does not overlap with the data line in the non-display area, thereby avoiding signal interference between the two, and realizing stable transmission of signals.
It can be seen from the above that, compared with the scheme in the prior art in which the signal lines are always disposed on the same metal film layer, the display panel provided in the embodiments of the present application can effectively reduce the frame area occupied by the clock signal lines. Further, the larger the number of clock signal lines, the larger the frame area can be reduced. Alternatively, the number of the clock signal lines in the above embodiments is not less than 6, each multiplexer may transmit data signals to at least 3 or at least 6 data lines, and the number of the signal lines connected to the driving circuit for transmitting data signals may be reduced to about 1/3 or 1/6 of the number of the data lines, thereby greatly reducing the number of interfaces of the driving circuit.
The embodiment of the application also provides a display device, as shown in fig. 7. The display device 700 may be a liquid crystal display device or an organic light emitting display device, including the display panel 100, 200, or 500 described above.
It is to be understood that, when the display device 700 is a liquid crystal display device, the display device may further include a backlight, a light guide plate, a pixel electrode, a liquid crystal layer, a polarizing plate, a protective glass, and other known structures; when the display device 700 is an organic light emitting display device, the display device may further include a protective glass, an organic light emitting diode array, and other known structures, which are not described herein again.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be understood by those skilled in the art that the scope of the present invention is not limited to the specific combination of the above-mentioned features, but also covers other embodiments formed by any combination of the above-mentioned features or their equivalents without departing from the spirit of the present invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (15)
1. A display panel, comprising:
a plurality of data line groups, each of the data line groups including a plurality of data lines;
a plurality of multiplexers, each of which is electrically connected to one of the data line groups; and
a plurality of clock signal lines and a driving circuit;
the multiplexer is electrically connected with the plurality of clock signal lines and is used for transmitting data signals to each data line in the data line group in a time-sharing manner under the control of the plurality of clock signal lines; wherein,
each clock signal line comprises a connecting line and a signal line extending along a first direction, the signal line and the connecting line are electrically connected at the intersection, and the connecting line is electrically connected with the driving circuit;
each signal line is arranged on the same metal film layer, and at least one connecting line and the signal line electrically connected with the connecting line are arranged in different layers.
2. The display panel according to claim 1, wherein the display panel comprises a display area and a non-display area surrounding the display area;
the non-display area comprises a first frame area and a second frame area, the first frame area, the display area and the second frame area are sequentially arranged along a second direction, and the second direction is intersected with the first direction;
the signal line is located in the first frame area and/or the second frame area.
3. The display panel according to claim 2, wherein the plurality of connection lines includes at least one first connection line and at least one second connection line;
each first connecting line and each signal line are arranged on a first metal film layer, and each second connecting line is arranged on a second metal film layer.
4. The display panel according to claim 3, wherein the first connection lines and the second connection lines are alternately arranged in the first direction.
5. The display panel according to claim 3, wherein the display panel comprises a base substrate,
the first connecting line has a first orthographic projection on the substrate base plate, and the second connecting line has a second orthographic projection on the substrate base plate;
at least one of the first orthographic projections overlaps one of the second orthographic projections.
6. The display panel according to claim 5, wherein the first connection lines and the second connection lines are equal in number;
each of the first orthographic projections overlaps one of the second orthographic projections.
7. The display panel according to any one of claims 4 to 6, wherein a first insulating layer is provided between the first metal film layer and the second metal film layer;
the first insulating layer is provided with a first through hole at a position corresponding to a cross point of the second connecting line and the signal line electrically connected with the second connecting line;
the signal line and the second connection line are electrically connected to each other through the first via hole.
8. The display panel according to claim 7, wherein the display panel comprises a scan line metal layer and a data line metal layer;
the first metal film layer is the scanning line metal layer, and the second metal film layer is the data line metal layer; or
The first metal film layer is the data line metal layer, and the second metal film layer is the scanning line metal layer.
9. The display panel according to claim 2, wherein the connecting line is located in the first frame region and/or the second frame region;
each connecting wire is positioned on the same metal film layer.
10. The display panel according to claim 9, wherein each of the signal lines is disposed on a third metal film layer, and each of the connection lines is disposed on a fourth metal film layer;
the third metal film layer and the fourth metal film layer are different film layers.
11. The display panel according to claim 10, wherein a second insulating layer is provided between the third metal film layer and the fourth metal film layer;
the second insulating layer is provided with a second through hole at the intersection of the signal line and the corresponding connecting line;
the signal lines and the corresponding connecting lines are electrically connected with each other through the second through holes.
12. The display panel according to claim 10, wherein the display panel comprises a scan line metal layer and a touch signal line metal layer;
the third metal film layer is the scanning line metal layer;
the fourth metal film layer is the touch signal line metal layer.
13. The display panel according to claim 2, wherein the first direction is perpendicular to the second direction.
14. The display panel according to claim 1, wherein the number of the clock signal lines is not less than 6.
15. A display device characterized by comprising the display panel according to any one of claims 1 to 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621436456.3U CN206619376U (en) | 2016-12-26 | 2016-12-26 | Display panel and the device comprising it |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621436456.3U CN206619376U (en) | 2016-12-26 | 2016-12-26 | Display panel and the device comprising it |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206619376U true CN206619376U (en) | 2017-11-07 |
Family
ID=60229788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621436456.3U Active CN206619376U (en) | 2016-12-26 | 2016-12-26 | Display panel and the device comprising it |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206619376U (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109116644A (en) * | 2018-08-29 | 2019-01-01 | 上海天马微电子有限公司 | Display panel and display device |
| CN109300396A (en) * | 2018-10-23 | 2019-02-01 | Oppo（重庆）智能科技有限公司 | A kind of display panel, display screen component and electronic device |
| CN109375706A (en) * | 2018-10-09 | 2019-02-22 | Oppo（重庆）智能科技有限公司 | Display panel, display screen component and electronic device |
| US10490620B1 (en) | 2018-06-29 | 2019-11-26 | Xiamen Tianma Micro-Electronics Co., Ltd. | Array substrate, display panel and display device |
| CN110751924A (en) * | 2019-12-03 | 2020-02-04 | 深圳市思坦科技有限公司 | Micro-LED display screen controlled in split screen mode |
| CN110969943A (en) * | 2019-11-27 | 2020-04-07 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111489698A (en) * | 2020-04-24 | 2020-08-04 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN113781913A (en) * | 2021-09-10 | 2021-12-10 | 厦门天马显示科技有限公司 | Display panel and display device |
| CN114120905A (en) * | 2021-11-12 | 2022-03-01 | 合肥京东方卓印科技有限公司 | Display substrate, preparation method thereof and display device |
| CN114419996A (en) * | 2022-01-21 | 2022-04-29 | 武汉华星光电技术有限公司 | Display panel |
| CN114815420A (en) * | 2022-04-06 | 2022-07-29 | Tcl华星光电技术有限公司 | Liquid crystal display panel and display device |
| CN115428060A (en) * | 2021-02-22 | 2022-12-02 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2024087697A1 (en) * | 2022-10-25 | 2024-05-02 | 华为技术有限公司 | Layout scheme of data transmission wiring, and main board and electronic device |
| US12124661B2 (en) | 2021-02-22 | 2024-10-22 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display device |
-
2016
- 2016-12-26 CN CN201621436456.3U patent/CN206619376U/en active Active
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10490620B1 (en) | 2018-06-29 | 2019-11-26 | Xiamen Tianma Micro-Electronics Co., Ltd. | Array substrate, display panel and display device |
| CN109116644A (en) * | 2018-08-29 | 2019-01-01 | 上海天马微电子有限公司 | Display panel and display device |
| CN109375706A (en) * | 2018-10-09 | 2019-02-22 | Oppo（重庆）智能科技有限公司 | Display panel, display screen component and electronic device |
| CN109375706B (en) * | 2018-10-09 | 2020-06-05 | Oppo（重庆）智能科技有限公司 | Display panel, display screen assembly and electronic device |
| CN109300396B (en) * | 2018-10-23 | 2021-06-01 | Oppo（重庆）智能科技有限公司 | Display panel, display screen assembly and electronic device |
| CN109300396A (en) * | 2018-10-23 | 2019-02-01 | Oppo（重庆）智能科技有限公司 | A kind of display panel, display screen component and electronic device |
| CN110969943A (en) * | 2019-11-27 | 2020-04-07 | 厦门天马微电子有限公司 | Display panel and display device |
| CN110751924A (en) * | 2019-12-03 | 2020-02-04 | 深圳市思坦科技有限公司 | Micro-LED display screen controlled in split screen mode |
| CN111489698A (en) * | 2020-04-24 | 2020-08-04 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US11893935B2 (en) | 2020-04-24 | 2024-02-06 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display device |
| CN115428060A (en) * | 2021-02-22 | 2022-12-02 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN115428060B (en) * | 2021-02-22 | 2024-04-12 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US12124661B2 (en) | 2021-02-22 | 2024-10-22 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display device |
| CN113781913A (en) * | 2021-09-10 | 2021-12-10 | 厦门天马显示科技有限公司 | Display panel and display device |
| CN114120905A (en) * | 2021-11-12 | 2022-03-01 | 合肥京东方卓印科技有限公司 | Display substrate, preparation method thereof and display device |
| CN114419996A (en) * | 2022-01-21 | 2022-04-29 | 武汉华星光电技术有限公司 | Display panel |
| CN114815420A (en) * | 2022-04-06 | 2022-07-29 | Tcl华星光电技术有限公司 | Liquid crystal display panel and display device |
| WO2024087697A1 (en) * | 2022-10-25 | 2024-05-02 | 华为技术有限公司 | Layout scheme of data transmission wiring, and main board and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206619376U (en) | Display panel and the device comprising it | |
| US10509505B2 (en) | In-cell touch panel and display apparatus | |
| US9665222B2 (en) | In-cell touch panel and display device with self-capacitance electrodes | |
| US11139317B2 (en) | Array substrate, touch panel and manufacturing method of array substrate | |
| KR102579368B1 (en) | Display panel with external signal lines under gate drive circuit | |
| US9606390B2 (en) | Capacitive in-cell touch panel and display device | |
| US9524064B2 (en) | Display device with integrated touch screen | |
| US9626027B2 (en) | Touch sensor integrated type display device | |
| CN110391253B (en) | Wiring board and display device | |
| CN107390941B (en) | Touch substrate, touch panel, display substrate, display panel and display device | |
| KR102579383B1 (en) | Touch recognition enabled display panel with asymmetric black matrix pattern | |
| US11947760B2 (en) | Display device with position input function | |
| JP6869786B2 (en) | Display device and method | |
| CN109616481B (en) | Array substrate, display panel and display device | |
| JP2019184765A (en) | Display device with position input function | |
| KR20170076187A (en) | In-cell touch type display device | |
| US11500237B2 (en) | Array substrate and display device | |
| US11226694B2 (en) | Touch display substrate, touch display method and touch display device | |
| US11307701B2 (en) | Display device including position input function | |
| CN112698534B (en) | Display device with position input function | |
| US20200064667A1 (en) | Display device | |
| JP2019086575A (en) | Display device | |
| CN114356138B (en) | Touch display panel and display device | |
| CN112783366B (en) | Touch control display panel | |
| CN115220598A (en) | Touch display panel and touch display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |