CN114120905A

CN114120905A - Display substrate, preparation method thereof and display device

Info

Publication number: CN114120905A
Application number: CN202111339841.1A
Authority: CN
Inventors: 吴仲远; 袁志东; 李永谦; 徐攀; 袁粲
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-03-01

Abstract

The embodiment of the disclosure provides a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of pixel circuit areas and a plurality of grid circuit areas which are alternately arranged, each pixel circuit area comprises at least one unit row, each unit row comprises a plurality of circuit units, each circuit unit comprises a pixel driving circuit, a data signal line and a scanning signal line, the data signal line and the scanning signal line are connected with the pixel driving circuits, each grid circuit area comprises at least one stage of grid driving circuit, each grid driving circuit comprises at least one output transistor and a clock signal line, the clock signal lines are connected with the output transistors, orthographic projections of the data signal lines on the plane of the display substrate are not overlapped with orthographic projections of the clock signal lines on the plane of the display substrate, and the first direction and the second direction are crossed. This is disclosed through setting up pixel circuit region and grid circuit region in turn at the display area, has effectively reduced display device's frame width, realizes display device's narrow frame.

Description

Display substrate, preparation method thereof and display device

Technical Field

The present disclosure relates to, but not limited to, the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of display technology, a display device using an OLED or a QLED as a light emitting device and performing signal control by a Thin Film Transistor (TFT) has become a mainstream product in the display field at present.

With the development of display technology, consumers have higher and higher requirements for display quality of display products, and a very narrow frame is a new trend of display product development, so that frame narrowing is a technical problem to be solved urgently in the field.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The technical problem to be solved by the exemplary embodiments of the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, so as to implement a narrow bezel of the display device.

In one aspect, the present disclosure provides a display substrate, including a plurality of pixel circuit regions and a plurality of gate circuit regions alternately arranged along a second direction, at least one pixel circuit region includes at least one unit row, the unit row includes a plurality of circuit units sequentially arranged along a first direction, at least one circuit unit includes a pixel driving circuit and a data signal line and a scanning signal line connected to the pixel driving circuit, at least one gate circuit region includes at least one stage of gate driving circuit, the gate driving circuit includes at least one output transistor and a clock signal line connected to the output transistor, a forward projection of the data signal line on a display substrate plane does not overlap with a forward projection of the clock signal line on the display substrate plane, and the first direction and the second direction are crossed.

In an exemplary embodiment, in at least one gate circuit region, the gate driving circuit includes a plurality of transistors and a plurality of clock signal lines connected to the plurality of transistors, and orthographic projections of the plurality of clock signal lines on a display substrate plane do not overlap and are not connected to each other.

In an exemplary embodiment, at least one pixel circuit region includes k unit rows sequentially disposed along the second direction, at least one gate circuit region includes k gate driving circuits sequentially disposed along the second direction, and k is a positive integer greater than or equal to 2.

In an exemplary embodiment, at least one gate circuit region includes an nth stage gate driving circuit and an n +1 th stage gate driving circuit, which are sequentially arranged along the second direction, the pixel circuit region on a side of the nth stage gate driving circuit away from the n +1 th stage gate driving circuit includes at least an nth unit row, the pixel circuit region on a side of the n +1 th stage gate driving circuit away from the nth stage gate driving circuit includes at least an n +1 th unit row, the nth stage gate driving circuit is configured to drive the pixel driving circuit of the nth unit row, the n +1 th stage gate driving circuit is configured to drive the pixel driving circuit of the n +1 th unit row, and n is a positive integer greater than or equal to 1.

In an exemplary embodiment, the pixel driving circuits in the n-th cell row and the pixel driving circuits in the n + 1-th cell row are mirror-symmetric with respect to a first reference line which is a straight line bisecting the gate circuit region in the second direction and extending along the first direction.

In an exemplary embodiment, the at least one pixel circuit region includes an m-th cell row and an m + 1-th cell row sequentially arranged along the second direction, the gate circuit region of the m-th cell row on a side away from the m + 1-th cell row includes at least an m-th stage gate driving circuit, the gate circuit region of the m + 1-th cell row on a side away from the m-th cell row includes at least an m + 1-th stage gate driving circuit, the m-th stage gate driving circuit is configured to drive the pixel driving circuit of the m-th cell row, the m + 1-th stage gate driving circuit is configured to drive the pixel driving circuit of the m + 1-th cell row, and m is a positive integer greater than or equal to 2.

In an exemplary embodiment, the pixel driving circuits in the m-th cell row and the pixel driving circuits in the m + 1-th cell row are mirror-symmetric with respect to a second reference line, which is a straight line bisecting the pixel circuit regions in a second direction and extending along the first direction.

In an exemplary embodiment, at least one gate driving circuit includes a first output transistor group, a second output transistor group, and a third output transistor group sequentially arranged along the first direction, the first output transistor group being connected to a first lead of an input clock signal, the second output transistor group being connected to a second lead of the input clock signal, the third output transistor group being connected to a third lead of the input clock signal, orthographic projections of the first, second, and third leads on a plane of a display substrate do not overlap and are not connected to each other.

In an exemplary embodiment, the first output transistor group includes two first output transistors that are mirror-symmetric with respect to the first lead; the second output transistor group comprises two second output transistors, and the two second output transistors are in mirror symmetry relative to the second lead; the third output transistor group includes two third output transistors that are mirror-symmetric with respect to the third lead.

In an exemplary embodiment, the first, second and third output transistors are identical in structure and size.

In an exemplary embodiment, the at least one gate circuit region includes an nth stage gate driving circuit and an n +1 th stage gate driving circuit sequentially disposed along the second direction; in the nth stage gate driving circuit, an input end of a first output transistor group is connected with a first clock first lead for inputting a first clock signal, an input end of a second output transistor group is connected with a first clock second lead for inputting the first clock signal, and an input end of a third output transistor group is connected with a first clock third lead for inputting the first clock signal; in the (n +1) -th stage gate driving circuit, an input end of a first output transistor group is connected with a first lead of a second clock to which a second clock signal is input, an input end of a second output transistor group is connected with a second lead of the second clock to which the second clock signal is input, and an input end of a third output transistor group is connected with a third lead of the second clock to which the second clock signal is input.

In an exemplary embodiment, the first output transistor group of the n +1 th stage gate driving circuit is disposed at one side of the first direction of the first output transistor group of the n-th stage gate driving circuit, the second output transistor group of the nth stage gate driving circuit is disposed on one side of the first output transistor group of the (n +1) th stage gate driving circuit in the first direction, the second output transistor group of the (n +1) th stage gate drive circuit is disposed on one side of the second output transistor group of the nth stage gate drive circuit in the first direction, the third output transistor group of the nth stage gate driving circuit is disposed on one side of the second output transistor group of the (n +1) th stage gate driving circuit in the first direction, the third output transistor group of the (n +1) th stage gate drive circuit is arranged on one side of the third output transistor group of the nth stage gate drive circuit in the first direction.

In an exemplary embodiment, in the nth stage gate driving circuit, output terminals of the first, second, and third output transistor groups are connected to a scan signal line of an nth cell row in the pixel circuit region; in the (n +1) th stage gate drive circuit, the output ends of the first output transistor group, the second output transistor group and the third output transistor group are all connected with the scanning signal line of the (n +1) th unit row in the pixel circuit region.

In an exemplary embodiment, the display substrate includes a plurality of conductive layers sequentially disposed on a base on a plane perpendicular to the display substrate, and the data signal line and the clock signal line are disposed in the same layer.

On the other hand, the present disclosure also provides a display device, including the aforementioned display substrate.

In another aspect, the present disclosure also provides a method for manufacturing a display substrate. The display substrate comprises a plurality of pixel circuit areas and a plurality of grid circuit areas which are alternately arranged along a second direction; the preparation method comprises the following steps:

forming at least one unit row in the pixel circuit area, and forming at least one stage of grid driving circuit in the grid circuit area; the unit row comprises a plurality of circuit units which are sequentially arranged along a first direction, at least one circuit unit comprises a pixel driving circuit, a data signal line and a scanning signal line, the data signal line and the scanning signal line are connected with the pixel driving circuit, at least one grid circuit area comprises at least one stage of grid driving circuit, the grid driving circuit comprises at least one output transistor and a clock signal line, the clock signal line is connected with the output transistor, the orthographic projection of the data signal line on a display substrate plane is not overlapped with the orthographic projection of the clock signal line on the display substrate plane, and the first direction and the second direction are crossed.

The embodiment of the disclosure provides a display substrate, a preparation method thereof and a display device. By longitudinally arranging the plurality of clock signal lines, the plurality of clock signal lines are not overlapped with the data signal lines, so that the noise of the data signal lines is eliminated, the overall load of the clock signal lines is reduced, and the display quality is improved to the maximum extent.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic plan view of a display substrate;

FIG. 3 is a schematic cross-sectional view of a display region of a display substrate;

FIG. 4 is a schematic plane view of a driving structure layer in a display region;

FIG. 5 is a schematic plan view of a light emitting structure layer in a display region;

FIG. 6 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 7 is a schematic plan view of a frame region;

FIG. 8 is a schematic structural diagram of a gate driving device;

FIG. 9 is a schematic diagram of an equivalent circuit of a gate driving circuit;

fig. 10 is a schematic plan view illustrating a display region according to an exemplary embodiment of the present disclosure;

fig. 11 is a schematic layout diagram of a pixel driving circuit and a GOA circuit according to an embodiment of the disclosure;

fig. 12 is a schematic plan view illustrating a third area in a GOA circuit according to an embodiment of the disclosure;

fig. 13 is a schematic diagram of a planar structure of a pixel driving circuit according to an embodiment of the disclosure;

fig. 14a to 14d are schematic views illustrating a semiconductor layer pattern formed according to an embodiment of the present disclosure;

fig. 15a to 15d are schematic views illustrating a first conductive layer pattern formed according to the embodiment of the disclosure;

fig. 16a to 16d are schematic views illustrating a second conductive layer pattern formed according to the embodiment of the disclosure;

fig. 17a to 17d are schematic views illustrating a fourth insulation layer pattern formed according to the embodiment of the present disclosure;

fig. 18a to 18d are schematic views illustrating a third conductive layer pattern formed according to an embodiment of the disclosure.

Description of reference numerals:

11 — a first active layer; 12 — a second active layer; 13 — a third active layer;

14-a fourth active layer; 15-a fifth active layer; 21-a first scanning signal line;

22 — a second scanning signal line; 23-third scanning signal lines; 24-a light emission control line;

25-power connection line; 26-a first plate; 31-initial connecting line;

32-a second polar plate; 41-first connecting electrode; 42-a second connecting electrode;

43 — third connecting electrode; 44-fourth connecting electrode; 45-fifth connecting electrode;

46-a sixth connecting electrode; 47 — a first power line; 48 — data signal lines;

49 — reference signal line; 50-initial signal line; 100-a display area;

100A-pixel circuit area; 100B-gate circuit region; 101-a substrate;

102-driving the structural layer; 103-light emitting structure layer; 104-an encapsulation layer;

111-an eleventh active layer; 112 — a twelfth active layer; 113A — first output active layer;

113B — a second output active layer; 113C — a third output active layer; 114-a fourteenth active layer;

115-a fifteenth active layer; 116-a sixteenth active layer; 117 — a seventeenth active layer;

118 — an eighteenth active layer; 119 — a nineteenth active layer; 120-a twentieth active layer;

121-the twenty-first active layer; 200-a binding region; 211 — an eleventh gate electrode line;

212-a twelfth gate electrode line; 213 — a thirteenth gate electrode line; 214 — a fourteenth gate electrode line;

215-a fifteenth gate electrode line; 216-sixteenth gate electrode line; 217-seventeenth gate electrode line;

218 — an eighteenth gate electrode line; 219 — nineteenth gate line; 220-twentieth gate electrode line;

221-twenty first gate electrode line; 233 — third polar plate; 235-a fifth polar plate;

241-a first connecting line; 242 — second connecting line; 243-third connecting line;

244 — fourth connecting line; 300-a border area; 310-circuit area;

311-eleventh connecting line; 312 — a twelfth connecting line; 313 — a thirteenth connecting line;

314-a fourteenth connecting line; 315-fifteenth connecting line; 316-sixteenth connecting line;

317-a seventeenth connecting line; 320-a partition area; 324-a fourth plate;

326 — sixth polar plate; 330-a cutting area; 401 — first signal input line;

402 — a second signal input line; 403-reset signal line; 404-enable signal line;

405-low voltage power supply line; 406/408 — first control line; 407/409 — second control line;

421-the twenty-first connecting line; 422-twenty second connecting line; 423-twenty third connecting line;

424-twenty-fourth connecting line; 425-a twenty-fifth connecting line; 426-twenty-sixth connecting line;

427-a twenty-seventh connecting line; 428-twenty-eighth connecting line; 429-twenty-ninth connecting line;

430-thirtieth connecting line; 431-a thirty-first connecting line; 432-a thirty-second connecting line;

433 — a thirty-third connecting line; 434-thirty-fourth connecting line; 435-thirty-fifth connecting line;

436-thirty-sixth connecting line; 437-thirty-seventh connecting line; 438-thirty eighth connecting line;

439-thirty ninth connecting line; 440-a forty-th connecting line; 441-the forty-th connecting line;

451 — a first output electrode; 452 — a second output electrode; 453-third output electrode;

501/601 — first lead; 502/602 — second lead; 503/603-third lead.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

The drawing scale in this disclosure may be referenced in the actual process, but is not limited thereto. For example: the width-length ratio of the channel, the thickness and the interval of each film layer and the width and the interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in the present disclosure are only schematic structural views, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other, and "source terminal" and "drain terminal" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In this specification, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like is not strictly defined, and may be an approximate triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like, and some small deformations due to tolerances may exist, and a lead angle, a curved edge, deformation, or the like may exist.

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller connected to the data driver, the scan driver and the light emitting driver, respectively, the data driver connected to the plurality of data signal lines (D1 to Dn), respectively, the scan driver connected to the plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver connected to the plurality of light emitting signal lines (E1 to Eo), respectively, and a pixel array. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one pixel driving circuit connected to a scan signal line, a data signal line and a light emitting signal line, respectively. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may supply a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a GOA circuit, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number. The light emission driver may generate emission signals to be supplied to the light emission signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo. For example, the light emitting driver may be constructed in the form of a GOA circuit, and the emission signal may be generated in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, and o may be a natural number.

Fig. 2 is a schematic plan view of a display substrate. As shown in fig. 2, in an exemplary embodiment, the display substrate may include a display area 100 and an edge area located outside the display area 100, and the edge area may include a binding area 200 located at one side of the display area 100 and a bezel area 300 located at the other side of the display area 100. In an exemplary embodiment, the display region 100 may include a plurality of sub-pixels arranged in a matrix, the binding region 200 may include at least an isolation dam and a binding circuit connecting signal lines of the plurality of sub-pixels to an external driving device, the frame region 300 may include at least an isolation dam, a Gate Driver on Array (GOA) transmitting scan signals and emission signals to circuit units of the plurality of sub-pixels, and a power line transmitting voltage signals to the plurality of sub-pixels, and the isolation dam of the binding region 200 and the frame region 300 form a ring structure surrounding the display region 100.

Fig. 3 is a schematic cross-sectional view of a display region in a display substrate. As shown in fig. 3, the display substrate may include a driving structure layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate, in a plane perpendicular to the display substrate.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, at least one of the circuit units may include a pixel driving circuit and a plurality of signal lines connected to the pixel driving circuit, the pixel driving circuit may include a plurality of transistors and a storage capacitor, and only one circuit unit including one driving transistor 102A and one storage capacitor 102B is illustrated in fig. 3 as an example. The light emitting structure layer 103 may include a plurality of sub-pixels, and at least one of the sub-pixels may include an anode connected to the drain electrode of the driving transistor 102A through the via hole, a pixel defining layer connected to the anode, an organic light emitting layer connected to the cathode, and a cathode driven by the anode and the cathode to emit light of a corresponding color. The encapsulating layer 104 may include a first encapsulating layer, a second encapsulating layer and a third encapsulating layer which are stacked, the first encapsulating layer and the third encapsulating layer may be made of inorganic materials, the second encapsulating layer may be made of organic materials, and the second encapsulating layer is disposed between the first encapsulating layer and the third encapsulating layer, so that it is ensured that external water vapor cannot enter the light emitting structure layer 103.

In an exemplary embodiment, the organic light emitting layer may include an emission layer (EML), and any one or more of: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an electron injection layer (EIL for short). In an exemplary embodiment, the hole injection layer, the hole transport layer, and the electron blocking layer of all the sub-pixels may be common layers connected together, the hole blocking layer, the electron transport layer, and the electron injection layer of all the sub-pixels may be common layers connected together, and the light emitting layer and the electron blocking layer of adjacent sub-pixels may have a small amount of overlap or may be isolated.

Fig. 4 is a schematic plan view of a driving structure layer in a display region. As shown in fig. 4, in a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units Q, at least one of the circuit units Q may include a scan signal line, a data signal line, a light emitting signal line, and a pixel driving circuit, the pixel driving circuit may be connected to the scan signal line, the data signal line, and the light emitting signal line, respectively, and the pixel driving circuit may be configured to receive a data voltage transmitted from the data signal line and output a corresponding current under the control of the scan signal line and the light emitting signal line. In an exemplary embodiment, a plurality of circuit cells Q sequentially arranged along a first direction X may be referred to as a cell row, a plurality of circuit cells Q sequentially arranged along a second direction Y may be referred to as a cell column, and the plurality of cell rows and the plurality of cell columns constitute a circuit cell array arranged in a matrix manner, the first direction X crossing the second direction Y.

Fig. 5 is a schematic plan view of a light emitting structure layer in a display region. As shown in fig. 5, the light emitting structure layer may include a first light emitting device P1 emitting light of a first color, a second light emitting device P2 emitting light of a second color, and a third light emitting device P3 emitting light of a third color in a plane parallel to the display substrate. In an exemplary embodiment, the first light emitting device P1 may be a red light emitting device emitting red light, forming a red sub-pixel (R), the second light emitting device P2 may be a blue light emitting device emitting blue light, forming a blue sub-pixel (B), and the third light emitting device P3 may be a green light emitting device emitting green light, forming a green sub-pixel (G).

In an exemplary embodiment, the red, blue, and green sub-pixels may constitute one pixel unit P. The shape of the sub-pixels can be rectangular, rhombic, pentagonal or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel mode, a vertical parallel mode or a delta-shaped mode. In an exemplary embodiment, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a square shape, a diamond shape, or the like, and the disclosure is not limited thereto.

In an exemplary embodiment, a plurality of light emitting devices sequentially arranged along the first direction X may be referred to as a pixel row, a plurality of light emitting devices sequentially arranged along the second direction Y may be referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in a matrix manner.

In an exemplary embodiment, the sub-pixel in the present disclosure refers to a region divided by a light emitting device, and the circuit unit in the present disclosure refers to a region divided by a pixel driving circuit. In an exemplary embodiment, the positions of both the sub-pixel and the circuit unit may be corresponding, or the positions of both the sub-pixel and the circuit unit may not be corresponding, and the disclosure is not limited herein.

Fig. 6 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in fig. 6, the pixel driving circuit may include 5 transistors (a first transistor T1 to a fifth transistor T5) and 1 storage capacitor C, and the pixel driving circuit is connected to 9 signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a light emitting signal line E, an initial signal line INIT, a reference voltage line REF, a first power supply line VDD, and a second power supply line VSS), respectively.

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the first node N1, a second terminal of the storage capacitor C is connected to the second node N2, and the storage capacitor C is configured to maintain a voltage of the first node N1 during one frame lighting period.

A control electrode of the first transistor T1 is connected to the first node N1, a first electrode of the first transistor T1 is connected to a second electrode of the second transistor T2, and a second electrode of the first transistor T1 is connected to the second node N2.

A control electrode of the second transistor T2 is connected to the emission control line E, a first electrode of the second transistor T2 is connected to the first power supply line VDD, and a second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1.

A control electrode of the third transistor T3 is connected to the second scan signal line S2, a first electrode of the third transistor T3 is connected to the reference voltage line REF, and a second electrode of the third transistor T3 is connected to the first node N1.

A control electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1.

A control electrode of the fifth transistor T5 is connected to the third scan signal line S3, a first electrode of the fifth transistor T5 is connected to the initial signal line INIT, a first electrode of the fifth transistor T5 is connected to the second node N2, and the fifth transistor T5 is configured to initialize the light emitting device.

A first pole of the light emitting device is connected to the second node N2, and a second pole of the light emitting device is connected to the second power line VSS. The light emitting device OLED is configured to emit light of a corresponding brightness in response to a current of the second pole of the first transistor T1. In an exemplary embodiment, the light emitting device may be an OLED, or may be a QLED.

The first node N1 is respectively connected to the control electrode of the first transistor T1, the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first terminal of the storage capacitor C, and the second node N2 is respectively connected to the second electrode of the fifth transistor T5, the second terminal of the storage capacitor C, and the first electrode of the light emitting device OLED.

In an exemplary embodiment, the signal of the first power line VDD is a signal continuously supplying a high level, and the signal of the second power line VSS is a signal of a low level.

In an exemplary embodiment, the first to fifth transistors T1 to T5 may be P-type transistors, or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to fifth transistors T1 to T5 may include P-type transistors and N-type transistors. The first transistor T1 is a driving transistor, and the other transistors except the first transistor T1 are switching transistors.

In an exemplary embodiment, the first to fifth transistors T1 to T5 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ both a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The Low-Temperature Polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, the Oxide thin film transistor has the advantages of Low leakage current and the like, the Low-Temperature Polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate to form a Low-Temperature Polycrystalline Oxide (LTPO) display substrate, the advantages of the Low-Temperature Polycrystalline Oxide and the LTPO can be utilized, Low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In an exemplary embodiment, the operation of the pixel driving circuit shown in fig. 6 may include:

in the first stage (initialization stage), the third scanning signal line S3 receives an on signal, and the first scanning signal line S1, the second scanning signal line S2, and the light-emitting signal line E receive off signals. The on signal of the third scan signal line S3 turns on the fifth transistor T5, the potential of the second node N2 is the initial voltage input by the initial signal line INIT, the first electrode of the OLED is initialized (reset), the pre-stored voltage in the OLED is cleared, the initialization is completed, and it is ensured that the OLED does not emit light.

In the second stage (compensation stage), the second scanning signal line S2 receives the on signal, and the first scanning signal line S1, the third scanning signal line S3, and the light emitting signal line E receive the off signal. The on signal of the second scan signal line S2 turns on the third transistor T3, and the potential of the first node N1 is the reference voltage V inputted by REF_refThe storage capacitor C maintains a difference between voltage values of the first node N1 and the second node N2. Due to V_refThe first transistor T1 is turned on at a high level, and the first transistor T1 is turned on at the beginning of the next stage due to the difference between the voltages at the first node N1 and the second node N2 maintained by the first capacitor C1, so that the threshold compensation is performed.

In the third stage (writing stage), the first scanning signal line S1 receives an on signal, and the second scanning signal line S2, the third scanning signal line S3, and the light-emitting signal line E receive off signals. The turn-on signal of the first scan signal line S1 turns on the fourth transistor T4, the data signal line D supplies the data voltage Vdata to the first node N1, the voltage value of the first node N1 jumps from Vref to Vdata, and the voltage value of the second node N2 jumps to Vref-Vth + (Vdata-Vref) × a under the bootstrap action of the storage capacitor, where a is a constant depending on the capacitance value of the storage capacitor.

In the fourth stage (light emission stage), the light emission control line E receives an on signal, and the first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 receive off signals. The turn-on signal of the light emission control line E turns on the second transistor T2, and the power voltage inputted from the first power line VDD is outputted to the first electrode of the light emitting device OLED through the turned-on second transistor T2 and first transistor T1, thereby driving the OLED to emit light.

The driving current I flowing through the light emitting element OLED can be obtained from the current formula when the driving transistor T1 is saturated_OLEDSatisfy the requirement of

I_OLED＝K(V_GS–V_th)²

＝K(Vdata-(Vref-Vth+(Vdata-Vref)*a)–V_th)²

＝K((1-a)*(V_data-V_ref))²

Where K is a fixed constant related to the process parameters and the geometry of the first transistor T1.

As can be seen from the derivation result of the current formula, in the light emitting phase, the driving current output by the first transistor T1 is related to the signal on the data signal terminal and is not affected by the threshold voltage of the first transistor T1 and the anode voltage of the organic light emitting diode OLED, so that the influence of the threshold voltage of the first transistor T1 and the anode voltage of the organic light emitting diode OLED on the driving current is eliminated, the display luminance of the display device is ensured to be uniform, and the display effect of the entire display device is improved.

Fig. 7 is a schematic plan view of a frame region, which is an enlarged view of a region C in fig. 2. As shown in fig. 7, in a plane parallel to the display substrate, the display substrate may include a display area 100 and a frame area 300 located on at least one side of the display area 100, and the frame area 300 may include a circuit area 310, a partition area 320, and a cutting area 330 sequentially arranged in a direction away from the display area.

In an exemplary embodiment, the display region 100 may include a plurality of circuit units each having a pixel driving circuit disposed therein and a plurality of light emitting devices connected to the pixel driving circuits in the plurality of circuit units, the pixel driving circuits being configured to output a current to the connected light emitting devices to cause the light emitting devices to emit light of corresponding luminance.

In an exemplary embodiment, the circuit region 310 may include at least a gate driving device, and the gate driving device may be connected to the pixel driving circuits of the plurality of circuit units in the display region 100 to output a scan signal and a light emission control signal to the display region.

In an exemplary embodiment, the blocking region 320 may include at least a power line, which may extend in a direction parallel to an edge of the display region to be connected to the second power line VSS of the circuit unit in the display region, a barrier dam, which may extend in a direction parallel to the edge of the display region, configured to block an organic layer in the encapsulation layer to prevent the organic layer from flowing toward the cutting region, a crack dam, and the like, configured to prevent the cutting process from affecting a film structure of the display substrate.

In an exemplary embodiment, the cutting zone 330 may include at least a cutting groove configured to allow the cutting device to cut along the cutting groove after all the film layers are prepared.

In an exemplary embodiment, the gate driving apparatus may include a plurality of cascaded GOA circuits, the GOA circuits convert a clock signal into on/off voltages, and output the on/off voltages to the display area, respectively, each stage of the GOA circuits is generally connected to a scan signal line and a light emitting signal line in one circuit unit, and the on voltages are sequentially output by the respective GOA circuits in turn, so that a plurality of unit rows in the display area are scanned line by line.

Fig. 8 is a schematic structural diagram of a gate driving device. In an exemplary embodiment, the gate driving apparatus may include a plurality of gate driving circuits (GOA circuits) cascaded in cascade. As shown in fig. 8, the gate driving apparatus may include a first stage GOA circuit, a second stage GOA circuit, and a third stage GOA circuit … …, and the first stage GOA circuit may generate a scan signal OUT1 supplied to the pixel driving circuits in the first unit row of the display region according to an initial signal supplied from an initial signal line STV, a clock signal supplied from a clock signal line CLK/CLKB, and a voltage signal supplied from a signal input line CN/CNB, etc. The i-th stage GOA circuit may generate the scan signal OUTi, i being a positive integer greater than 1, supplied to the pixel driving circuits in the i-th unit row of the display region according to the scan signal OUTi-1 generated by the i-1-th stage GOA circuit, the clock signal supplied from the clock signal line CLK/CLKB, the voltage signal supplied from the signal input line CN/CNB, and the like.

Fig. 9 is an equivalent circuit diagram of a GOA circuit. In an exemplary embodiment, the GOA circuit can include a plurality of transistors and a plurality of capacitors. As shown in fig. 9, the GOA circuit may include 11 transistors (an eleventh transistor T11 through a twenty-first transistor T21) and 2 capacitors C1 and C2, and is connected to 10 signal lines (an enable signal line EN, a low voltage power source line VGL, and a signal output line OUT), respectively.

In an exemplary embodiment, taking the nth stage GOA circuit as an example, a first terminal of the first capacitor C1 is connected to the pull-up node PU, a second terminal of the first capacitor C1 is connected to the present stage signal output terminal OUT _ n, a first terminal of the second capacitor C2 is connected to the pull-down node PD, and a second terminal of the second capacitor C2 is connected to the low voltage power line VGL.

A control electrode of the eleventh transistor T11 is connected to the output signal line OUT _ n-1 of the previous stage, a first electrode of the eleventh transistor T11 is connected to the first signal input line CN, a second electrode of the eleventh transistor T11 is connected to the pull-up node PU, and the output signal line OUT _ n-1 of the previous stage may be used as a first control line of the GOA circuit of the current stage.

A control electrode of the twelfth transistor T12 is connected to the next-stage output signal line OUT _ n +1, a first electrode of the twelfth transistor T12 is connected to the pull-up node PU, a second electrode of the twelfth transistor T12 is connected to the second signal input line CNB, and the next-stage output signal line OUT _ n +1 may serve as a second control line of the GOA circuit of this stage.

A control electrode of the thirteenth transistor T13 is connected to the pull-up node PU, a first electrode of the thirteenth transistor T13 is connected to the first clock signal line CLK, a second electrode of the thirteenth transistor T13 is connected to the current-stage signal output terminal OUT _ n, and the current-stage signal output terminal OUT _ n may serve as a signal output line of the current-stage GOA circuit.

A control electrode of the fourteenth transistor T14 is connected to the pull-down node PD, a first electrode of the fourteenth transistor T14 is connected to the present-stage signal output terminal OUT _ n, and a second electrode of the fourteenth transistor T14 is connected to the low voltage power supply line VGL.

A control electrode of the fifteenth transistor T15 is connected to the pull-down node PD, a first electrode of the fifteenth transistor T15 is connected to the pull-up node PU, and a second electrode of the fifteenth transistor T15 is connected to the low voltage power supply line VGL.

A control electrode of the sixteenth transistor T16 is connected to the pull-up node PU, a first electrode of the sixteenth transistor T16 is connected to the pull-down node PD, and a second electrode of the sixteenth transistor T16 is connected to the low voltage power supply line VGL.

A control electrode and a first electrode of the seventeenth transistor T17 are connected to the second clock signal line CLKB, and a second electrode of the seventeenth transistor T17 is connected to the pull-down node PD.

A control electrode of the eighteenth transistor T18 is connected to the present-stage signal output terminal OUT _ n, a first electrode of the eighteenth transistor T18 is connected to the pull-down node PD, and a second electrode of the eighteenth transistor T18 is connected to the low voltage power supply line VGL.

A control electrode and a first electrode of the nineteenth transistor T19 are connected to the enable signal line EN, and a second electrode of the nineteenth transistor T19 is connected to the present-stage signal output line OUT _ n.

A control electrode of the twentieth transistor T20 is connected to the enable signal line EN, a first electrode of the twentieth transistor T20 is connected to the pull-down node PD, and a second electrode of the twentieth transistor T20 is connected to the low voltage power supply line VGL.

A control electrode of the twenty-first transistor T21 is connected to the reset signal line RST, a first electrode of the twenty-first transistor T21 is connected to the pull-up node PU, and a second electrode of the twenty-first transistor T21 is connected to the low voltage power supply line VGL.

In an exemplary embodiment, when the level of the first clock signal line CLK is an active level, the level of the second clock signal line CLKB is an inactive level, and when the level of the second clock signal line CLKB is an active level, the level of the first clock signal line CLK is an inactive level, and the low-voltage power line VGL continuously supplies a low-level signal.

In an exemplary embodiment, the pulse duration of the first clock signal line CLK active level signal and the pulse duration of the second clock signal line CLKB active level signal may be equal.

In an exemplary embodiment, the eleventh to twenty-first transistors T11 to T21 may be all N-type thin film transistors or all P-type thin film transistors, which may unify process flows, reduce process processes, and help to improve product yield. Considering that the low-temperature polysilicon thin film transistor has a small leakage current, the eleventh to twenty-first transistors T11 to T21 may be low-temperature polysilicon thin film transistors, and the thin film transistors may have a bottom gate structure or a top gate structure as long as a switching function can be implemented.

Taking the nth GOA circuit shown in fig. 9 including the eleventh to twenty-first transistors T11 to T21 of N-type as an example, the working process of the GOA circuit may include a display stage and a touch stage.

In the display stage, the operation process of the nth stage GOA circuit may include:

in the first stage (input stage), the input signals of the output signal line OUT _ n-1 (first control line), the first signal input line CN, and the second clock signal line CLKB of the previous stage are high level signals, and the input signal of the first clock signal line CLK is a low level signal. The eleventh transistor T11 is turned on by a high-level signal inputted to the output signal line OUT _ n-1 of the previous stage, and the first capacitor C1 is charged by pulling up the level of the pull-up node PU. Since the input signal of the first clock signal line CLK is a low level signal, the signal output terminal OUT _ n of this stage does not output any signal at this stage. Although the seventeenth transistor T17 is turned on and the pull-down node PD is pulled high by the high level signal of the input signal of the second clock signal line CLKB, the sixteenth transistor T16 is turned on and the potential of the pull-down node PD is pulled low by the low voltage power supply line VGL as the pull-up node PU rises. Since the level of the output signal of the present stage signal output terminal OUT _ n is low, the eighteenth transistor T18 is turned off, and the level of the pull-down node PD maintains low.

In the second stage (output stage), the input signal of the first clock line CLK is a high level signal, and the input signals of the output signal line OUT _ n-1 (first control line) and the second clock line CLKB of the previous stage are low level signals. The eleventh transistor T11 is turned off by a low level signal input from the output signal line OUT _ n-1 of the previous stage, and under the bootstrap action of the first capacitor C1, the level of the pull-up node PU is continuously pulled high, the thirteenth transistor T13 is turned on by the high level of the pull-up node PU, and the signal output end OUT of the current stage outputs a high level signal of the first clock signal line CLK, so that the output signal of the signal output end OUT _ n of the current stage is at a high level, and the level of the pull-up node PU is raised, thereby improving the turn-on capability of the thirteenth transistor T13 and ensuring the pixel charging capability. The seventeenth transistor T17 is turned off by a low level signal inputted from the second clock signal line CLKB, the sixteenth transistor T16 is still turned on by a high level of the pull-up node PU, the eighteenth transistor T18 is turned on by a high level of the present-stage signal output terminal OUT _ n, and thus the pull-down node PD is pulled down to a low level of the low voltage power supply line VGL. The low level of the pull-down node PD turns off the fourteenth transistor T14 and the fifteenth transistor T15, and the levels of the signals of the pull-up node PU and the signal output terminal OUT _ n of the current stage are not pulled down, so that the normal output of the current stage GOA circuit can be ensured.

In the third stage (reset stage), the input signals of the output signal line OUT _ n +1 (second control line), the reset signal line RST and the second clock signal line CLKB of the next stage are high level signals, and the input signals of the second signal input line CNB and the first clock signal line CLK are low level signals. The twelfth transistor T12 is turned on by a high level signal inputted to the next-stage output signal line OUT _ n +1, and the level of the pull-up node PU is pulled down to the low level of the second signal input line CNB. The twenty-first transistor T21 is turned on by a high level signal input from the reset signal line RST, and the level of the pull-up node PU is pulled down to the low level of the low voltage power supply line VGL. Since the level of the pull-up node PU is pulled low, the thirteenth transistor T13 and the sixteenth transistor T16 are turned off, and the present-stage signal output terminal OUT _ n does not output. The seventeenth transistor T17 is turned on by a high level signal inputted through the second clock signal line CLKB, the pull-down node PD is pulled high, the second capacitor C2 is charged, and the level of the pull-down node PD is high. Since the sixteenth transistor T16 and the eighteenth transistor T18 are turned off by the low level of the present stage signal output terminal OUT _ n and the low level of the pull-up node PU, the level of the pull-down node PD is not pulled down. Due to the high level of the pull-down node PD, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, and the levels of the pull-up node PU and the present stage signal output terminal OUT _ n can be further pulled down to reduce noise.

In the touch phase, the enable signal line EN inputs a continuous high level signal, the nineteenth transistor T19 and the twentieth transistor T20 are continuously turned on, the signal of VGL is written into the pull-down node PD, and the fourteenth transistor T14 and the fifteenth transistor T15 are turned off, so that the signals of the pull-up node PU and the present-stage signal output terminal OUT _ n are not affected.

Currently, as the resolution of a display device is gradually improved, and in order to ensure reliability and functionality of a frame region, the frame width of a conventional display device is about 1 mm. The resolution (Pixels Per inc, abbreviated as PPI) refers to the number of Pixels in a unit area, and may be referred to as pixel density, and a higher PPI value indicates that the display device can display a picture with higher density, and the details of the picture are richer. Because resolution ratio improves not only needs to increase the quantity of gate drive circuit in the frame region, and then increases gate drive circuit's area occupied, need increase the width of power cord in the frame region moreover to reduce the impedance and the pressure drop of power cord, guarantee to show luminance homogeneity, therefore it is very big to reduce the degree of difficulty of frame in the regional structure that sets up gate drive circuit of frame.

In order to effectively reduce the frame width of the display device and achieve a narrow frame of the display device, exemplary embodiments of the present disclosure provide a display substrate In which a Gate Driver In AA (Gate Driver In AA, or GIA for short) is disposed In a display region. In an exemplary embodiment, the display substrate may include a display region, the display region may include a plurality of pixel circuit regions and a plurality of gate circuit regions alternately arranged along the second direction, at least one of the pixel circuit regions may include at least one cell row, the cell row may include a plurality of circuit cells sequentially arranged along the first direction, the at least one circuit cell may include a pixel driving circuit and a data signal line and a scan signal line connected to the pixel driving circuit, the at least one gate circuit region may include at least one stage of gate driving circuit, the gate driving circuit may include at least one output transistor and a clock signal line connected to the output transistor, a forward projection of the data signal line on a plane of the display substrate does not overlap a forward projection of the clock signal line on the plane of the display substrate, and the first direction and the second direction cross.

In an exemplary embodiment, in the at least one gate circuit region, the gate driving circuit may include a plurality of transistors and a plurality of clock signal lines correspondingly connected to the plurality of transistors, and orthographic projections of the plurality of clock signal lines on the display substrate plane do not overlap and are not connected to each other.

In an exemplary embodiment, the at least one pixel circuit region may include k unit rows sequentially disposed along the second direction, and the at least one gate circuit region may include k gate driving circuits sequentially disposed along the second direction, k being a positive integer greater than or equal to 2. For example, k may be equal to 2, forming a structure of 2 cell rows +2 level gate driving circuits. As another example, k may be equal to 4, forming a structure of 4 cell rows +4 levels of gate driving circuits.

In an exemplary embodiment, the at least one gate circuit region may include an nth stage gate driving circuit and an n +1 th stage gate driving circuit sequentially arranged along the second direction, the pixel circuit region on a side of the nth stage gate driving circuit away from the n +1 th stage gate driving circuit includes at least an nth unit row, the pixel circuit region on a side of the n +1 th stage gate driving circuit away from the nth stage gate driving circuit includes at least an n +1 th unit row, the nth stage gate driving circuit is configured to drive the pixel driving circuits of the nth unit row, the n +1 th stage gate driving circuit is configured to drive the pixel driving circuits of the n +1 th unit row, and n is a positive integer greater than or equal to 1.

In an exemplary embodiment, the at least one pixel circuit region may include an m-th cell row and an m + 1-th cell row sequentially arranged along the second direction, the gate circuit region of the m-th cell row on a side away from the m + 1-th cell row includes at least an m-th stage gate driving circuit, the gate circuit region of the m + 1-th cell row on a side away from the m-th cell row includes at least an m + 1-th stage gate driving circuit, the m-th stage gate driving circuit is configured to drive the pixel driving circuit of the m-th cell row, the m + 1-th stage gate driving circuit is configured to drive the pixel driving circuit of the m + 1-th cell row, and m is a positive integer greater than or equal to 2.

Fig. 10 is a schematic plan view of a display region according to an exemplary embodiment of the present disclosure. As shown in fig. 10, in an exemplary embodiment, the display region may include M pixel circuit regions 100A and M-1 gate circuit regions 100B, each of the pixel circuit regions 100A and each of the gate circuit regions 100B may be in a bar shape extending along the first direction X, and the plurality of pixel circuit regions 100A and the plurality of gate circuit regions 100B may be alternately disposed along the second direction Y.

In an exemplary embodiment, the first and mth pixel circuit regions may include one cell row, and the second to (M-1) th pixel circuit regions may each include two cell rows.

In an exemplary embodiment, the first pixel circuit region may include a first cell row, the second pixel circuit region may include a second cell row and a third cell row sequentially arranged along the second direction Y, the third pixel circuit region may include a fourth cell row and a fifth cell row sequentially arranged along the second direction Y, … …, the (M-1) th pixel circuit region may include a [ (2M-1) -2] th cell row and a [ (2M-1) -1] th cell row sequentially arranged along the second direction Y, and the mth pixel circuit region may include a (2M-2) th cell row.

In an exemplary embodiment, each of the gate circuit regions 100B may include two stages of GOA circuits, the first gate circuit region may include a first stage GOA circuit and a second stage GOA circuit sequentially arranged along the second direction Y, the second gate circuit region may include a third stage GOA circuit and a fourth stage GOA circuit sequentially arranged along the second direction Y, the third gate circuit region may include a fifth stage GOA circuit and a sixth stage GOA circuit sequentially arranged along the second direction Y, … …, and the (M-1) th gate circuit region may include a [ (2M-1) -1] th stage GOA circuit and a (2M-1) th stage GOA circuit sequentially arranged along the second direction Y.

In an exemplary embodiment, the two-stage GOA circuits of the first gate circuit region are configured to output scan signals to the circuit cells of the first and second pixel circuit regions, respectively, the two-stage GOA circuits of the second gate circuit region are configured to output scan signals to the circuit cells of the second and third pixel circuit regions, respectively, … …, and the two-stage GOA circuits of the (M-1) th gate circuit region are configured to output scan signals to the circuit cells of the (M-1) th and mth pixel circuit regions, respectively.

In an exemplary embodiment, the first stage GOA circuits in the first gate circuit region are configured to output the scan signals to the pixel driving circuits of the first unit row in the first pixel circuit region, and the second stage GOA circuits in the first gate circuit region are configured to output the scan signals to the pixel driving circuits of the second unit row in the second pixel circuit region; the third stage GOA circuit in the second gate circuit region is configured to output the scan signal to the pixel driving circuits of the third unit row in the second pixel circuit region, and the fourth stage GOA circuit in the second gate circuit region is configured to output the scan signal to the pixel driving circuits of the fourth unit row in the third pixel circuit region; … …, respectively; the [ (2M-1) -1] th stage GOA circuit in the (M-1) th gate circuit region is configured to output a scan signal to the pixel driving circuit of the [ (2M-1) -1] th unit row in the (M-1) th pixel circuit region, and the (2M-1) th stage GOA circuit in the (M-1) th gate circuit region is configured to output a scan signal to the pixel driving circuit of the (2M-2) th unit row in the M pixel circuit region.

Fig. 11 is a schematic layout diagram of a pixel driving circuit and a GOA circuit according to an exemplary embodiment of the disclosure, which illustrates a structure in which an n-1 unit row, an n-th GOA circuit, an n +1 unit row, and an n +2 unit row are sequentially disposed along a second direction Y. As shown in fig. 11, the gate circuit region including the nth and n +1 th GOA circuits may be located between two pixel circuit regions, the pixel circuit region on the side of the gate circuit region in the second direction Y may include an n-1 th cell row and an n +2 th cell row, and the pixel circuit region on the side of the gate circuit region opposite to the second direction Y may include an n +1 th cell row and an n +2 th cell row, forming a structure in which the two stages of GOA circuits are disposed between two cell rows.

In an exemplary embodiment, each of the GOA circuits may have a bar shape extending along the first direction X, each of the cell rows may include a plurality of circuit cells sequentially disposed along the first direction X, and the circuit cells may include a pixel driving circuit and a scan signal line, a data signal line, and a light emitting signal line connected to the pixel driving circuit.

In an exemplary embodiment, the nth cell row is adjacent to the nth-stage GOA circuit in the gate circuit region, the (n-1) th cell row is located on a side of the nth cell row away from the gate circuit region, and the nth-stage GOA circuit is configured to drive the plurality of pixel driving circuits in the nth cell row, i.e., the nth-stage GOA circuit outputs the nth-stage scan signal to the plurality of pixel driving circuits in the nth cell row.

In an exemplary embodiment, the (n +1) th cell row is adjacent to the (n +1) th stage GOA circuit in the gate circuit region, the (n + 2) th cell row is located at a side of the (n +1) th cell row away from the gate circuit region, and the (n +1) th stage GOA circuit is configured to drive the plurality of pixel driving circuits in the (n +1) th cell row, that is, the (n +1) th stage GOA circuit outputs the (n +1) th stage scan signal to the plurality of pixel driving circuits in the (n +1) th cell row.

In an exemplary embodiment, the pixel driving circuits in the pixel circuit regions on both sides of the gate circuit region in the second direction Y may be arranged in a mirror symmetry with respect to a first reference line X1, which is a straight line bisecting the gate circuit regions in the second direction Y and extending along the first direction X, the first reference line X1. For example, the arrangement of the plurality of pixel driving circuits in the nth cell row on the side of the second direction Y of the gate circuit region and the arrangement of the plurality of pixel driving circuits in the (n +1) th cell row on the side of the opposite direction of the second direction Y of the gate circuit region may be mirror-symmetric with respect to the first reference line X1. For another example, the arrangement of the plurality of pixel driving circuits in the (n-1) th cell row on the side of the second direction Y of the gate circuit region and the arrangement of the plurality of pixel driving circuits in the (n + 2) th cell row on the side of the opposite direction Y of the second direction Y of the gate circuit region may be mirror-symmetric with respect to the first reference line X1.

In an exemplary embodiment, in one pixel circuit region, the plurality of pixel driving circuits in two unit rows may be arranged in a mirror symmetry with respect to a second reference line X2, which is a straight line bisecting the pixel circuit region in the second direction and extending along the first direction X, the second reference line X2. For example, the arrangement of the plurality of pixel driving circuits in the n-1 th cell row and the arrangement of the plurality of pixel driving circuits in the n-th cell row may be mirror-symmetrical with respect to the second reference line X2. For another example, the arrangement of the plurality of pixel driving circuits in the (n +1) th cell row and the arrangement of the plurality of pixel driving circuits in the (n + 2) th cell row may be mirror-symmetrical with respect to the second reference line X2.

In an exemplary embodiment, the arrangement of the pixel driving circuit may include any one or more of: the shape and position of the first scanning signal line, the shape and position of the second scanning signal line, the shape and position of the third scanning signal line, and the shape and position of the storage capacitor.

In an exemplary embodiment, the strip-shaped GOA circuit may include a first region, a second region and a third region sequentially arranged along the first direction X, and circuit structures in the three regions together constitute a complete one-stage GOA circuit.

In an exemplary embodiment, the circuit structure of the first region may include at least the present-stage signal output line OUT _ n, the previous-stage output signal line OUT _ n-1, the next-stage output signal line OUT _ n +1, the first signal input line CN, the second signal input line CNB, the first clock signal line CLK, the second clock signal line CLKB, the reset signal line RST, the second capacitor C2, the eleventh transistor T11, the twelfth transistor T12, the sixteenth transistor T16, the eighteenth transistor T18, and the twenty-first transistor T21, the circuit structure of the second region may include at least an enable signal line EN, a fourteenth transistor T14, a nineteenth transistor T19, and a twentieth transistor T20, and the circuit structure of the third region may include at least a low voltage power supply line VGL, a plurality of first clock signal lines CLK, a first capacitor C1, and a plurality of output transistors (third transistors T13).

Fig. 12 is a schematic plan view of a third area in a GOA circuit according to an exemplary embodiment of the disclosure, which illustrates a structure of 3 sets of output transistors. As shown in fig. 12, in an exemplary embodiment, the nth-stage GOA circuit may include a first output transistor group, a second output transistor group, and a third output transistor group, which are sequentially disposed along the first direction X. In an exemplary embodiment, the first output transistor group may include 2 first output transistors T13A, and the 2 first output transistors T13A are each connected to the first clock first lead 501 to which the first clock signal is input. The second output transistor group may include 2 second output transistors T13B, and the 2 second output transistors T13B are each connected to the first clock second lead 502 to which the first clock signal is input. The third output transistor group may include 2 third output transistors T13C, and the 2 third output transistors T13C are each connected to the first clock third lead 503 to which the first clock signal is input.

In the exemplary embodiment, the first clock first lead 501, the first clock second lead 502, and the first clock third lead 503, to which the first clock signal is input, are each in a line shape extending along the second direction Y, extending from the gate circuit region to the pixel circuit region, or extending from the pixel circuit region to the gate circuit region, where the first lead 501, the first clock second lead 502, and the first clock third lead 503 are located between adjacent pixel driving circuits. The orthographic projections of the first clock first lead 501, the first clock second lead 502 and the first clock third lead 503 on the plane of the display substrate are not overlapped, and areas where the gate circuit areas are located are not connected with each other, and the fact that the three leads are not directly connected with each other or connected through connecting lines means that the three leads are not connected with each other.

In an exemplary embodiment, in the nth-stage GOA circuit, the 2 first output transistors T13A may be mirror-symmetrical with respect to the first clock first lead 501, the 2 second output transistors T13B may be mirror-symmetrical with respect to the first clock second lead 502, and the 2 third output transistors T13C may be mirror-symmetrical with respect to the first clock third lead 503.

In an exemplary embodiment, the n +1 th-stage GOA circuit may include a first output transistor group, a second output transistor group, and a third output transistor group sequentially arranged along the first direction X. The first output transistor group may include 2 first output transistors T13A, and the 2 first output transistors T13A are each connected to the second clock first lead 601 to which the second clock signal is input. The second output transistor group may include 2 second output transistors T13B, and the 2 second output transistors T13B are each connected to the second clock second lead 602 to which the second clock signal is input. The third output transistor group may include 2 third output transistors T13C, and the 2 third output transistors T13C are each connected to the second clock third lead 603 to which the second clock signal is input.

In an exemplary embodiment, the second clock first, second and

third leads

601, 602 and 603 inputting the second clock signal may be in the shape of a line extending along the second direction Y, extending from the gate circuit region to the pixel circuit region where the second clock first, second and

third leads

601, 602 and 603 are located between adjacent pixel driving circuits, or extending from the pixel circuit region to the gate circuit region. Orthographic projections of the second clock first lead 601, the second clock second lead 602 and the second clock third lead 603 on the plane of the display substrate do not overlap, and are not connected with each other in the area where the gate circuit area is located.

In an exemplary embodiment, in the n +1 th stage GOA circuit, the 2 first output transistors T13A may be mirror-symmetrical with respect to the second clock first lead 601, the 2 second output transistors T13B may be mirror-symmetrical with respect to the second clock second lead 602, and the 2 third output transistors T13C may be mirror-symmetrical with respect to the second clock third lead 603.

In an exemplary embodiment, the first output transistor T13A, the second output transistor T13B, and the third output transistor T13C may be identical in structure and size, and the identical in structure and size may include any one or more of: the width-to-length ratios of the 3 transistors are the same, the positions, shapes and sizes of active layers in the 3 transistors are the same, the positions, shapes and sizes of gate electrodes in the 3 transistors are the same, the positions, shapes and sizes of source electrodes in the 3 transistors are the same, the positions, shapes and sizes of drain electrodes in the 3 transistors are the same, and the connection structures of the 3 transistors and the leads are the same.

In an exemplary embodiment, the first output transistor group of the n +1 th-stage gate driving circuit is disposed on one side of the first direction X of the first output transistor group of the n +1 th-stage gate driving circuit, the second output transistor group of the n +1 th-stage gate driving circuit is disposed on one side of the first direction X of the second output transistor group of the n +1 th-stage gate driving circuit, the third output transistor group of the n +1 th-stage gate driving circuit is disposed on one side of the first direction X of the second output transistor group of the n +1 th-stage gate driving circuit, and the third output transistor group of the n +1 th-stage gate driving circuit is disposed on one side of the first direction X of the third output transistor group of the n +1 th-stage gate driving circuit.

In an exemplary embodiment, in the nth stage gate driving circuit, the output terminals of the 2 first output transistors T13A, the 2 second output transistors T13B, and the 2 third output transistors T13C are all directly connected to the first scan signal line in the nth cell row, outputting nth stage scan signals to the plurality of pixel driving circuits in the nth cell row. In the (n +1) th stage gate driving circuit, the output terminals of the 2 first output transistors T13A, the 2 second output transistors T13B, and the 2 third output transistors T13C are all directly connected to the first scan signal line in the (n +1) th cell row, outputting the (n +1) th stage scan signal to the plurality of pixel driving circuits in the (n +1) th cell row.

In an exemplary embodiment, the pixel circuit region includes therein a plurality of data lines 48, and the plurality of data lines 48 are each in a line shape extending along the second direction Y, extending from the pixel circuit region to the gate circuit region, or extending from the gate circuit region to the pixel circuit region. In the grid circuit area, orthographic projections of the data lines on the plane of the display substrate do not overlap orthographic projections of the lead wires for transmitting the clock signals on the plane of the display substrate. In an exemplary embodiment, the plurality of data lines and the plurality of lead lines may be parallel to each other.

Fig. 13 is a schematic plan structure diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure, which illustrates a plan structure of one repeating unit (12 circuit units of 2 unit rows and 6 unit columns). As shown in fig. 13, in an exemplary embodiment, at least one circuit unit may include a pixel driving circuit, which may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a storage capacitor C, and a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emission control line 24, a first power supply line 47, a data signal line 48, a reference signal line 49, and an initial signal line 50 connected to the pixel driving circuit.

In an exemplary embodiment, main portions of the first, second, and third

scan signal lines

21, 22, and 23 may extend in the first direction X, and main portions of the first power line 47, the data signal line 48, the initial signal line 50, and the reference signal line 49 may extend in the second direction Y. In the present disclosure, a extending along the B direction means that a may include a main portion and a secondary portion connected to the main portion, the main portion being a line, a line segment or a bar-shaped body, the main portion extending along the B direction, and the length of the main portion extending along the B direction being greater than the length of the secondary portion extending along other directions.

In an exemplary embodiment, the pixel driving circuit may further include a power connection line 25 having a body portion extending in the first direction X, the power connection line 25 being connected with the first power line 47 through a via hole such that the first power line 47 transmits a power voltage to the plurality of circuit cells in one cell row through the power connection line 25. In an exemplary embodiment, the first power lines 47 may be disposed at both sides of the repeating unit first direction X, forming a one-to-three structure in which one first power line 47 transmits a power voltage to three unit columns.

In an exemplary embodiment, the pixel driving circuit may further include an initial connection line 31 having a body portion extending in the first direction X, the initial connection line 31 being connected with the initial signal line 50 through a via hole such that the initial signal line 50 transmits an initial voltage to the plurality of circuit cells in one cell row through the initial connection line 31. In an exemplary embodiment, the initial signal line 50 may be disposed at the middle of the repeating unit first direction X, forming a six-by-six structure in which one initial signal line 50 transmits an initial voltage to six unit columns.

In an exemplary embodiment, 2 reference signal lines 49 may be disposed in each repeating unit, and 2 reference signal lines 49 may be disposed at both sides of the initial signal line 50, forming a one-to-three structure in which one reference signal line 49 transmits a reference voltage to three unit columns.

In an exemplary embodiment, a data signal line 48 may be disposed in each cell column, transmitting a data voltage to a plurality of circuit cells in one cell column.

In an exemplary embodiment, 2 cell rows may share the light emission control line 24 and the power connection line 25 in one repeating unit, the light emission control line 24 may be positioned at a side of the n-1 th cell row adjacent to the n-1 th cell row, and the power connection line 25 may be positioned at a side of the n-1 th cell row adjacent to the n-1 th cell row.

In an exemplary embodiment, in one repeating unit, the pixel driving circuits in the 3 unit columns at one side of the initial signal line 50 and the pixel driving circuits in the 3 unit columns at the other side of the initial signal line 50 may be mirror-symmetrical with respect to a repeating unit center line, which is a straight line bisecting the repeating unit in the first direction X and extending along the second direction Y.

In an exemplary embodiment, the pixel driving circuits in two unit columns adjacent in the first direction X may be mirror-symmetrical with respect to a unit column center line, which is a straight line located between the two unit columns and extending along the second direction Y.

In an exemplary embodiment, in one repeating unit, the pixel driving circuits in the n-1 th unit row and the pixel driving circuits in the n-th unit row may be substantially mirror-symmetrical with respect to the second reference line X2.

In an exemplary embodiment, in one repeating unit, a blank region may be disposed between the pixel driving circuits in two unit columns adjacent in the first direction X, and the blank region may serve as a routing region to dispose the first signal input line CN, the second signal input line CNB, the reset signal line RST, the enable signal line EN, the low voltage power line VGL, the plurality of first clock signal lines, and the plurality of second clock signal lines extending in the second direction Y in the GOA circuit.

In an exemplary embodiment, the first direction X may be an extending direction of the scan signal lines, the second direction Y may be an extending direction of the data signal lines, and the plurality of first clock signal lines and the plurality of second clock signal lines are parallel to the data signal lines.

In an exemplary embodiment, the display substrate may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, and a third conductive layer sequentially disposed on the base in a plane perpendicular to the display substrate.

In an exemplary embodiment, the semiconductor layer may include active layers of a plurality of transistors of the pixel driving circuit and the GOA circuit.

In an exemplary embodiment, the first conductive layer may include the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light emission control line 24, the first plate, and gate electrodes of a plurality of transistors of the pixel driving circuit, and a plurality of control lines, a plurality of connection lines, a third plate, and a fifth plate of the GOA circuit.

In an exemplary embodiment, the second conductive layer may include a second plate of the pixel driving circuit, and a plurality of connection lines, a fourth plate, and a sixth plate of the GOA circuit. The first polar plate and the second polar plate form a storage capacitor of the pixel driving circuit, the third polar plate and the fourth polar plate form a first capacitor of the GOA circuit, and the fifth polar plate and the sixth polar plate form a second capacitor of the GOA circuit.

In an exemplary embodiment, the third conductive layer may include the first power line 47, the data signal line 48, the initialization signal line 50, the reference signal line 49, and a plurality of connection electrodes of the pixel driving circuit, and the first signal input line 401, the second signal input line 402, the reset signal line 403, the enable signal line 404, the low voltage power line 405, the plurality of first clock signal lines, the plurality of second clock signal lines, the plurality of control lines, and the plurality of connection lines of the GOA circuit.

In an exemplary embodiment, the GOA circuits of the gate circuit region may be formed together in a plurality of pixel driving circuits forming the pixel circuit region.

The following is an exemplary description through a process of manufacturing a display substrate. The "patterning process" referred to in the present disclosure includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist, and the like, for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, development, and the like, for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, the term "a and B are disposed in the same layer" means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the forward projection of B is located within the range of the forward projection of a" or "the forward projection of a includes the forward projection of B" means that the boundary of the forward projection of B falls within the boundary range of the forward projection of a, or the boundary of the forward projection of a overlaps with the boundary of the forward projection of B.

In an exemplary embodiment, taking 12 circuit cells (2 cell rows and 6 cell columns) and a 2-level GOA circuit as an example, the process of manufacturing the display substrate may include the following operations.

(1) A semiconductor layer pattern is formed. In an exemplary embodiment, the forming of the semiconductor layer pattern may include: a first insulating film and a semiconductor film are sequentially deposited on a substrate, and the semiconductor film is patterned by a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern disposed on the first insulating layer, where the semiconductor layer pattern may include a pixel semiconductor layer disposed in a pixel circuit region and a gate semiconductor layer disposed in a gate circuit region, as shown in fig. 14a to 14d, fig. 14a is a schematic view of the pixel semiconductor layer in the pixel circuit region, fig. 14b is a schematic view of the gate semiconductor layer in the first region of the gate circuit region, fig. 14c is a schematic view of the gate semiconductor layer in the second region of the gate circuit region, and fig. 14d is a schematic view of the gate semiconductor layer in the third region of the gate circuit region.

Fig. 14a illustrates a planar structure of one repeating unit (12 pixel driving circuits) in the pixel circuit region, and as shown in fig. 14a, the pixel semiconductor layer in the pixel circuit region may include, in an exemplary embodiment: the first active layer 11 of the first transistor T1 to the fifth active layer 15 of the fifth transistor T5.

In an exemplary embodiment, the first active layer 11 may have a shape of a "zigzagging", the second and fourth active layers 12 and 14 may have a shape of an "I", the third active layer 13 may have a shape of an "n", and the fifth active layer 15 may have a shape of an "L".

In an exemplary embodiment, the circuit cells of the (n-1) th cell row and the circuit cells of the (n) th cell row may share the second active layer 12 in one cell column.

In an exemplary embodiment, the fifth active layer 15 in the n-1 th cell row may be positioned on a side of the second active layer 12 away from the n-th cell row, the first active layer 11 in the n-1 th cell row may be positioned on a side of the fifth active layer 15 away from the n-th cell row, the fourth active layer 14 in the n-1 th cell row may be positioned on a side of the first active layer 11 away from the n-th cell row, and the third active layer 13 in the n-1 th cell row may be positioned on a side of the fourth active layer 14 away from the n-th cell row. The fifth active layer 15 in the nth cell row may be positioned at a side of the second active layer 12 away from the (n-1) th cell row, the first active layer 11 in the nth cell row may be positioned at a side of the fifth active layer 15 away from the (n-1) th cell row, the fourth active layer 14 in the nth cell row may be positioned at a side of the first active layer 11 away from the (n-1) th cell row, and the third active layer 13 in the nth cell row may be positioned at a side of the fourth active layer 14 away from the (n-1) th cell row.

In an exemplary embodiment, in one cell row, the third active layers 13 in the circuit cells of the m-th, m + 1-th and m + 2-th cell columns may be integrally connected to each other, and the third active layers 13 in the circuit cells of the m + 3-th, m + 4-th and m + 5-th cell columns may be integrally connected to each other.

In an exemplary embodiment, the first, third, fourth, and fifth

active layers

11, 13, 14, and 15 in the n-1 th cell row and the first, third, fourth, and fifth

active layers

11, 13, 14, and 15 in the n-1 th cell row may be mirror-symmetrical with respect to the second reference line X2.

In an exemplary embodiment, the pixel semiconductor layers in adjacent cell columns may be mirror-symmetrical with respect to the cell column center line. For example, the pixel semiconductor layer of the circuit cell in the m-th cell column and the pixel semiconductor layer of the circuit cell in the m + 1-th cell column are mirror-symmetrical with respect to the cell column center line. For another example, the pixel semiconductor layer of the circuit unit in the m +1 th unit column and the pixel semiconductor layer of the circuit unit in the m +2 th unit column are mirror-symmetric with respect to the center line of the unit column.

In an exemplary embodiment, in one repeating unit, the pixel semiconductor layers in the plurality of unit columns on both sides of the center line of the repeating unit may be mirror-symmetrical with respect to the center line of the repeating unit.

In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. The first and second regions 11-1 and 11-2 of the first active layer 11 may be located at both sides of the first active layer 11 in the second direction Y, the first and second regions 12-1 and 12-2 of the second active layer 12 may be located at both sides of the second active layer 12 in the first direction X, the first and second regions 14-1 and 14-2 of the fourth active layer 14 may be located at both sides of the fourth active layer 14 in the first direction X, and the first and second regions 15-1 and 15-2 of the fifth active layer 15 may be located at both sides of the fifth active layer 15 in the second direction Y.

In an exemplary embodiment, the third active layers 13 in the circuit cells of the m-th, m + 1-th and m + 2-th cell columns have the same first region 13-1, and the second region 13-2 of the third active layer 13 is located in each circuit cell, respectively.

Fig. 14b, 14c, and 14d respectively illustrate the planar structures of the gate semiconductor layers of the first region, the second region, and the third region in one gate circuit region, where the gate semiconductor layers in the three regions together form a complete gate semiconductor layer of the GOA circuit, the nth GOA circuit may be above the first reference line X1, and the (n +1) th GOA circuit may be below the first reference line X1. As shown in fig. 14b, 14c and 14d, in an exemplary embodiment, the gate semiconductor layer in the gate circuit region may include: the first active layer 111 of the eleventh transistor T11 through the twenty-first active layer 121 of the twenty-first transistor T21.

In an exemplary embodiment, the eleventh active layer 111 of the eleventh transistor T11 may have a bar shape extending along the second direction Y, and the eleventh active layer 111 may be located at an end portion of the gate circuit region opposite to the first direction X.

In an exemplary embodiment, the twelfth active layer 112 of the twelfth transistor T12 may have a bar shape extending along the second direction Y, and the twelfth active layer 112 may be located at one side of the eleventh active layer 111 in the first direction X.

In an exemplary embodiment, the twenty-first active layer 121 of the twenty-first transistor T21 may have a shape of a stripe extending along the second direction Y, and the twenty-first active layer 121 may be located at one side of the twelfth active layer 112 in the first direction X. In an exemplary embodiment, the position and shape of the twenty-first active layer 121 in the nth-stage GOA circuit and the n + 1-stage GOA circuit may be substantially mirror-symmetrical with respect to the first reference line X1.

In an exemplary embodiment, the fifteenth active layer 115 of the fifteenth transistor T15 may have a bar shape extending along the first direction X, and the fifteenth active layer 115 may be positioned at one side of the twenty-first active layer 121 in the first direction X. In an exemplary embodiment, the position and shape of the fifteenth active layer 115 in the nth-order GOA circuit and the (n +1) th-order GOA circuit may be substantially mirror-symmetrical with respect to the first reference line X1.

In an exemplary embodiment, the sixteenth active layer 116 of the sixteenth transistor T16 may have a shape of a bar extending along the first direction X, and the sixteenth active layer 116 may be positioned at one side of the fifteenth active layer 115 in the first direction X. In an exemplary embodiment, each level of the GOA circuit may include two sixteenth active layers 116, and the two sixteenth active layers 116 may be sequentially disposed along the first direction X. In an exemplary embodiment, the position and shape of the sixteenth active layer 116 in the nth-order GOA circuit and the (n +1) th-order GOA circuit may be substantially mirror-symmetrical with respect to the first reference line X1.

In an exemplary embodiment, the shape of the eighteenth active layer 118 of the eighteenth transistor T11 may be a stripe shape extending along the first direction X, and the eighteenth active layer 118 may be located at one side of the sixteenth active layer 116 in the first direction X. In an exemplary embodiment, the position and shape of the eighteenth active layer 118 in the nth-stage GOA circuit and the (n +1) th-stage GOA circuit may be substantially mirror-symmetrical with respect to the first reference line X1.

In an exemplary embodiment, the seventeenth active layer 117 of the seventeenth transistor T17 may have a shape of a bar extending along the first direction X, and the seventeenth transistor T17 may be positioned at one side of the eighteenth active layer 118 in the first direction X. In an exemplary embodiment, a distance between the seventeenth active layer 117 and the eighteenth active layer 118 in the nth-level GOA circuit may be greater than a distance between the seventeenth active layer 117 and the eighteenth active layer 118 in the n + 1-level GOA circuit, i.e., the seventeenth active layer 117 in the two-level GOA circuit is staggered in position so that they are connected to different clock signal lines.

In an exemplary embodiment, the fourteenth active layer 114 of the fourteenth transistor T14 may have a rectangular shape, and the fourteenth active layer 114 may be positioned at one side of the seventeenth active layer 117 in the first direction X. In an exemplary embodiment, each of the GOA circuits may include a plurality of fourteenth active layers 114, and the plurality of fourteenth active layers 114 may be sequentially disposed along the first direction X. For example, each level of the GOA circuit may include 6 fourteenth active layers 114. In an exemplary embodiment, the position and shape of the fourteenth active layer 114 in the nth-stage GOA circuit and the n +1 th-stage GOA circuit may be substantially mirror-symmetrical with respect to the first reference line X1.

In an exemplary embodiment, the twentieth active layer 120 of the twentieth transistor T20 may have a shape of a bar extending along the first direction X, and the twentieth active layer 120 may be located at one side of the fourteenth active layer 114 in the first direction X. In an exemplary embodiment, the position and shape of the twentieth active layer 120 in the nth-stage GOA circuit and the (n +1) th-stage GOA circuit may be substantially mirror-symmetrical with respect to the first reference line X1.

In an exemplary embodiment, the nineteenth active layer 119 of the nineteenth transistor T19 may have a shape of a stripe extending along the first direction X, and the nineteenth active layer 119 may be located at one side of the twentieth active layer 120 in the first direction X. In an exemplary embodiment, the position and shape of the nineteenth active layer 119 in the nth-order GOA circuit and the n + 1-order GOA circuit may be substantially mirror-symmetrical with respect to the first reference line X1.

In an exemplary embodiment, each stage of the GOA circuit may include a plurality of thirteenth transistors T13 as output transistors, and thus may include a plurality of output active layers, which may be located at one side of the nineteenth active layer 119 in the first direction X and sequentially arranged along the first direction X.

In an exemplary embodiment, each stage of the GOA circuit may include a first output active layer group, a second output active layer group, and a third output active layer group sequentially arranged along the first direction X.

In an exemplary embodiment, a distance between the first output active layer group and the twentieth active layer 120 in the nth-level GOA circuit may be smaller than a distance between the first output active layer group and the twentieth active layer 120 in the n + 1-level GOA circuit, a distance between the second output active layer group and the twentieth active layer 120 in the nth-level GOA circuit may be smaller than a distance between the second output active layer group and the twentieth active layer 120 in the n + 1-level GOA circuit, a distance between the third output active layer group and the twentieth active layer 120 in the nth-level GOA circuit may be smaller than a distance between the third output active layer group and the twentieth active layer 120 in the n + 1-level GOA circuit, namely, the first output active layer group, the second output active layer group and the third output active layer group in the two-stage GOA circuit are staggered in position, so that the first output active layer group, the second output active layer group and the third output active layer group are conveniently connected with different clock signal lines.

In an exemplary embodiment, a first output active layer group of the nth-stage GOA circuit may be located at one side of the twentieth active layer 120 in the first direction X, a first output active layer group of the (n +1) th-stage GOA circuit may be located at one side of the first output active layer group of the nth-stage GOA circuit in the first direction X, a second output active layer group of the nth-stage GOA circuit may be located at one side of the first output active layer group of the (n +1) th-stage GOA circuit in the first direction X, a second output active layer group of the (n +1) th-stage GOA circuit may be located at one side of the second output active layer group of the nth-stage GOA circuit in the first direction X, a third output active layer group of the nth-stage GOA circuit may be located at one side of the second output active layer group of the (n +1) th-stage GOA circuit in the first direction X, and a third output active layer group of the (n +1) th-stage GOA circuit in the first direction X.

In an exemplary embodiment, the first output active layer group may include 2 first output active layers 113A sequentially disposed along the first direction X, the second output active layer group may include 2 second output active layers 113B sequentially disposed along the first direction X, and the third output active layer group may include 2 third output active layers 113C sequentially disposed along the first direction X.

(2) A first conductive layer pattern is formed. In an exemplary embodiment, the forming of the first conductive layer pattern may include: a second insulating film and a first conductive film are sequentially deposited on the substrate on which the patterns are formed, and the first conductive film is patterned by a patterning process to form a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, where the first conductive layer pattern may include a first pixel conductive layer disposed in the pixel circuit region and a first gate conductive layer disposed in the gate circuit region, as shown in fig. 15a to 15d, fig. 15a is a schematic diagram of the first pixel conductive layer in the pixel circuit region, fig. 15b is a schematic diagram of the first gate conductive layer in the first gate circuit region, fig. 15c is a schematic diagram of the first gate conductive layer in the second gate circuit region, and fig. 15d is a schematic diagram of the first gate conductive layer in the third gate circuit region. In an exemplary embodiment, the first conductive layer may be referred to as a first GATE metal (GATE1) layer.

Fig. 15a illustrates a planar structure of one repeating unit (12 pixel driving circuits) in the pixel circuit region, and as shown in fig. 15a, in an exemplary embodiment, the first pixel conductive layer in the pixel circuit region may include at least: a first scanning signal line 21, a second scanning signal line 22, a third scanning signal line 23, a light emission control line 24, a power connection line 25, and a first plate 26.

In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23, the light emission control line 24, and the power connection line 25 may be in a line shape in which the body portion extends in the first direction X, the light emission control line 24 and the power connection line 25 may be shared by the nth cell row and the n-1 th cell row, the light emission control line 24 may be located at a side of the n-1 th cell row adjacent to the nth cell row, and the power connection line 25 may be located at a side of the nth cell row adjacent to the n-1 th cell row.

In an exemplary embodiment, the third scan signal line 23 in the n-1 th cell row may be positioned at a side of the light emission control line 24 away from the n-th cell row, and the third scan signal line 23 in the n-1 th cell row may be positioned at a side of the power connection line 25 away from the n-1 th cell row. A third gate block may be disposed on the third scan signal line 23 of each circuit unit, the third gate block extending toward a direction close to the light emission control line 24, and a region where the third scan signal line 23 and the third gate block overlap with the fifth active layer as a gate electrode of the fifth transistor T5, forming a fifth transistor T5 of a double gate structure.

In an exemplary embodiment, the first plate 26 in the n-1 th cell row may be positioned at a side of the third scan signal line 23 away from the n-1 th cell row, and the first plate 26 in the n-1 th cell row may be positioned at a side of the third scan signal line 23 away from the n-1 th cell row. The orthographic projection of the first plate 26 of each circuit unit on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the first plate 26 can simultaneously serve as one plate of the storage capacitor and the gate electrode of the first transistor T1.

In an exemplary embodiment, the first electrode plate 26 may have a rectangular shape, corners of the rectangular shape may be provided with chamfers, one side of the first electrode plate 26 in the first direction X or the opposite side of the first direction X may be provided with a first opening, and the first opening may expose the second region of the first active layer.

In an exemplary embodiment, the first scan signal line 21 in the n-1 th cell row may be positioned at a side of the first plate 26 away from the n-1 th cell row, and the first scan signal line 21 in the n-1 th cell row may be positioned at a side of the first plate 26 away from the n-1 th cell row. Two first gate blocks may be disposed on the first scan signal line 21 of each circuit unit, the two first gate blocks extend toward the first electrode plate 26, and a region where the two first gate blocks overlap the fourth active layer serves as a gate electrode of the fourth transistor T4, forming a fourth transistor T4 of a double gate structure.

In an exemplary embodiment, the second scan signal line 22 in the n-1 th cell row may be positioned at a side of the first scan signal line 21 away from the n-1 th cell row, and the second scan signal line 22 in the n-1 th cell row may be positioned at a side of the first scan signal line 21 away from the n-1 th cell row. Two second gate blocks may be disposed on the second scan signal line 22 of each circuit unit, the two second gate blocks extending in a direction away from the first scan signal line 21, and a region where the two second gate blocks overlap the third active layer as a gate electrode of the third transistor T3, forming a third transistor T3 of a dual gate structure.

In an exemplary embodiment, the emission control line 24 may be provided with a fourth gate block extending in a direction of the power connection line 25, and a region where the fourth gate block overlaps the second active layer as a gate electrode of the second transistor T2, forming a second transistor T2 of a single gate structure.

In an exemplary embodiment, a power connection protrusion may be disposed on the power connection line 25, the power connection protrusion extends toward the light-emitting control line 24, the power connection line 25 is configured to be connected to a first power line formed subsequently, and the power connection protrusion is configured to be connected to a first pole of a second transistor T2 formed subsequently, so that the first power line supplies the same power voltage to the plurality of pixel driving circuits in one unit row through the power connection line 25, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

In an exemplary embodiment, the first, second, third and first

scan signal lines

21, 22, 23 and the first plate 26 in the (n-1) th cell row and the (n) th cell row may be mirror-symmetrical with respect to the first direction reference line X1.

In an exemplary embodiment, the first pixel conductive layer in the adjacent cell column may be mirror-symmetrical with respect to the cell column center line. For example, the first pixel conductive layer of the circuit cell in the m-th cell column and the first pixel conductive layer of the circuit cell in the m + 1-th cell column are mirror-symmetric with respect to the cell column center line. For another example, the first pixel conductive layer of the circuit unit in the (m +1) th unit column and the first pixel conductive layer of the circuit unit in the (m + 2) th unit column are mirror-symmetric with respect to the center line of the unit column.

In an exemplary embodiment, in one repeating unit, the first pixel conductive layers in the plurality of unit columns on both sides of the repeating unit center line may be mirror-symmetrical with respect to the repeating unit center line.

Fig. 15b, 15c, and 15d respectively illustrate the planar structures of the first gate conductive layers in the first region, the second region, and the third region of one gate circuit region, where the first gate conductive layers in the three regions together form a complete first gate conductive layer of a GOA circuit, an nth-level GOA circuit may be above the first reference line X1, and an n + 1-level GOA circuit may be below the first reference line X1. As shown in fig. 15b, 15c and 15d, in an exemplary embodiment, the first gate conductive layer in the gate circuit region may include: an eleventh gate electrode line 211, a twelfth gate electrode line 212, a thirteenth gate electrode line 213, a fourteenth gate electrode line 214, a fifteenth gate electrode line 215, a sixteenth gate electrode line 216, a seventeenth gate electrode line 217, an eighteenth gate electrode line 218, a nineteenth gate electrode line 219, a twentieth gate electrode line 220, a twenty-first gate electrode line 221, a third plate 233, a fifth plate 235, a first connecting line 241, a second connecting line 242, a third connecting line 243, and a fourth connecting line 244.

In an exemplary embodiment, an orthogonal projection of a first end of the eleventh gate electrode line 211 on the substrate at least partially overlaps an orthogonal projection of the eleventh active layer on the substrate, a region of the overlap serves as a gate electrode of the eleventh transistor T11 of the double gate structure, a second end of the eleventh gate electrode line 211 extends to a side of the twelfth active layer in the second direction Y along the first direction X, and the second end of the eleventh gate electrode line 211 is configured to be connected to a first control line (an output signal line of a previous stage GOA circuit) to be formed later.

In an exemplary embodiment, an orthographic projection of a first end of the twelfth gate electrode line 212 on the substrate and an orthographic projection of the twelfth active layer on the substrate at least partially overlap, a region of the overlap serves as a gate electrode of the twelfth transistor T12 of the double gate structure, a second end of the twelfth gate electrode line 212 extends along the first direction X to between the twelfth active layer and the twenty-first active layer, and the second end of the twelfth gate electrode line 212 is configured to be connected to a second control line (an output signal line of a next-stage GOA circuit) to be formed later.

In an exemplary embodiment, the thirteenth gate electrode line 213 may be in a line shape having a body portion extending in the first direction X, and a plurality of control blocks may be disposed on the thirteenth gate electrode line 213, and the plurality of control blocks may include 2 first control blocks, 2 second control blocks, and 2 third control blocks. The orthographic projection of the thirteenth gate electrode line 213 and the first control block on the substrate at least partially overlaps the orthographic projection of the first output active layer on the substrate, and the overlapped region serves as the gate electrode of the first output transistor T13A of the double gate structure. The orthographic projection of the thirteenth gate electrode line 213 and the second control block on the substrate at least partially overlaps with the orthographic projection of the second output active layer on the substrate, and the overlapped region serves as the gate electrode of the second output transistor T13B of the double gate structure. The orthographic projection of the thirteenth gate electrode line 213 and the third control block on the substrate at least partially overlaps the orthographic projection of the third output active layer on the substrate, and the overlapped region serves as the gate electrode of the third output transistor T13C of the double gate structure.

In an exemplary embodiment, each of the first control block, the second control block, and the third control block may include a first sub-block and a second sub-block, a first end of the first sub-block is connected to the thirteenth gate electrode line 213, a second end of the first sub-block extends in the second direction Y or the opposite direction of the second direction Y and then is connected to a first end of the second sub-block, and a second end of the second sub-block extends in the first direction X or the opposite direction of the first direction X to form an "L" shaped structure.

In an exemplary embodiment, a first end of the fourteenth gate electrode line 214 is connected to the fifth electrode plate 235, a second end of the fourteenth gate electrode line 214 extends to a side opposite to the first direction X of the twentieth active layer 120 along the first direction X, and a forward projection of the fourteenth gate electrode line 214 on the substrate at least partially overlaps with forward projections of the fourteenth active layers on the substrate, and an overlapped region serves as a gate electrode of the fourteenth transistors T14. In an exemplary embodiment, the fourteenth gate electrode line 214 is configured to be a pull-down node line (PD).

In an exemplary embodiment, a first end of the fifteenth gate electrode line 215 may be provided with a fifth control block, an orthogonal projection of the fifth control block on the substrate at least partially overlaps an orthogonal projection of the fifteenth active layer on the substrate, an overlapped region serves as a gate electrode of the fifteenth transistor T15, and a second end of the fifteenth gate electrode line 215 is connected to the fifth electrode plate 235 after extending along the first direction X.

In an exemplary embodiment, a first end of the sixteenth gate electrode line 216 may be positioned at one side of the twenty-first active layer first direction X, and a second end of the sixteenth gate electrode line 216 may extend to one side of the sixteenth active layer first direction X along the first direction X. The sixteenth gate electrode line 216 may have 2 groups of sixth control blocks disposed thereon, each group of sixth control blocks may include 2 sixth control blocks, an orthographic projection of the 2 sixth control blocks on the substrate at least partially overlaps with an orthographic projection of the sixteenth active layer on the substrate, and an overlapped region serves as a gate electrode of the sixteenth transistor T16 of the dual-gate structure. In an exemplary embodiment, the sixteenth gate electrode line 216 is configured to be connected with a subsequently formed pull-up node line (PU).

In an exemplary embodiment, the first end of the seventeenth gate electrode line 217 may be provided with 2 seventh control blocks, an orthographic projection of the 2 seventh control blocks on the substrate may at least partially overlap with an orthographic projection of the seventeenth active layer 117 on the substrate, an overlapped region may serve as a gate electrode of the seventeenth transistor T17 of the dual gate structure, and the second end of the seventeenth gate electrode line 217 may extend along the first direction X to one side of the seventeenth active layer first direction X. In an exemplary embodiment, the second end of the seventeenth gate electrode line 217 in the nth-stage GOA circuit is configured to be connected to a subsequently formed second clock signal line (CLKB), and the second end of the seventeenth gate electrode line 217 in the n +1 th-stage GOA circuit is configured to be connected to a subsequently formed first clock signal line (CLK).

In an exemplary embodiment, the eighteenth gate electrode line 218 may be a strip shape having a main portion extending along the first direction X, and 2 eighth control blocks may be disposed on the eighteenth gate electrode line 218, and an orthogonal projection of the 2 eighth control blocks on the substrate at least partially overlaps an orthogonal projection of the eighteenth active layer on the substrate, and an overlapped region serves as a gate electrode of the eighteenth transistor T18 of the double gate structure. In an exemplary embodiment, the eighteenth gate electrode line 218 is configured to be connected to the output line of the current stage to be formed subsequently, that is, the eighteenth gate electrode line 218 in the nth-stage GOA circuit is configured to be connected to the output line of the nth stage (OUT _ n) to be formed subsequently, and the eighteenth gate electrode line 218 in the (n +1) th-stage GOA circuit is configured to be connected to the output line of the (n +1) th stage (OUT _ n +1) to be formed subsequently.

In an exemplary embodiment, the nineteenth gate electrode line 219 may be a strip shape having a body portion extending along the first direction X, and 2 ninth control blocks may be disposed on the nineteenth gate electrode line 219, and an orthogonal projection of the 2 ninth control blocks on the substrate at least partially overlaps an orthogonal projection of the nineteenth active layer on the substrate, and an overlapped region serves as a gate electrode of the nineteenth transistor T19 of the dual gate structure.

In an exemplary embodiment, the twentieth gate electrode line 220 may have a strip shape with a main portion extending along the first direction X, and 2 tenth control blocks may be disposed on the twentieth gate electrode line 220, an orthogonal projection of the 2 tenth control blocks on the substrate may at least partially overlap an orthogonal projection of the twentieth active layer on the substrate, and an overlapping region may serve as a gate electrode of the twentieth transistor T20 of the dual gate structure.

In an exemplary embodiment, the nineteenth and twentieth

gate electrode lines

219 and 220 may be an integral structure connected to each other, and a connection end at which the nineteenth and twentieth

gate electrode lines

219 and 220 are connected to each other is configured to be connected to an enable signal line (EN) formed later.

In an exemplary embodiment, an orthographic projection of a first end of the twenty-first gate electrode line 221 on the substrate at least partially overlaps an orthographic projection of the twenty-first active layer 121 on the substrate, an overlapping region serves as a gate electrode of the twenty-first transistor T21 of the double gate structure, a second end of the twenty-first gate electrode line 221 extends along the first direction X to between the fifteenth active layer and the sixteenth active layer, and the second end of the twenty-first gate electrode line 221 is configured to be connected to a reset signal line (RST) to be formed subsequently.

In an exemplary embodiment, the third plate 233 may include a plurality of rectangular plates connected to each other, and the third plate 233 is configured to serve as one plate of the first capacitor. A first end of the third plate 233 may be connected to the thirteenth gate electrode line 213, and a second end of the third plate 233 is configured to be connected to a subsequently formed pull-up node line (PU). In an exemplary embodiment, the thirteenth gate electrode line 213 and the third electrode plate 233 may be an integral structure connected to each other.

In an exemplary embodiment, the fifth plate 235 may have a rectangular shape, and the fifth plate 235 is configured to be one plate of the second capacitor. A first end of the fifth plate 235 may be connected to the fifteenth gate electrode line 215, and a second end of the third plate 230 may be connected to the fourteenth gate electrode line 214. In an exemplary embodiment, the fourteenth gate electrode line 214, the fifteenth gate electrode line 215, and the fifth electrode plate 235 may be an integral structure connected to each other.

In an exemplary embodiment, the first end of the first connection line 241 may be positioned at one side of the eleventh active layer first direction X, the second end of the first connection line 241 may extend along the first direction X to one side of the twelfth active layer opposite to the first direction X, and the first connection line 241 is configured as a connection line between the second pole of the eleventh transistor T11 and the second pole of the twelfth transistor T12.

In an exemplary embodiment, a plurality of second connection lines 242 may be positioned between the adjacent fourteenth active layers 114, the plurality of second connection lines 242 being configured as connection lines between the second poles of the plurality of fourteenth transistors T14.

In an exemplary embodiment, a first end of the third connection line 243 may be located at one side of the fourteenth active layer 114 in the first direction X, a second end of the third connection line 243 may extend along the first direction X to one side of the third plate 233 opposite to the first direction X, and the third connection line 243 is configured as a low voltage connection line, and may be connected to a subsequently formed low voltage power supply line (VGL).

In an exemplary embodiment, a first end of the fourth connection line 244 may be positioned at one side of the twelfth active layer first direction X, a second end of the fourth connection line 244 may extend along the first direction X to one side of the twenty-first active layer opposite to the first direction X, and the fourth connection line 244 is configured as a connection line between the second pole of the twelfth transistor T12 and the first pole of the twenty-first transistor T21.

In an exemplary embodiment, the first scanning signal line 21 in the pixel circuit region may be configured to be connected to a second pole of a subsequently formed present-stage output transistor (thirteenth transistor T13) and a first pole of a fourteenth transistor T14 as a signal output line of the GOA circuit. For the nth stage GOA circuit, the first scanning signal line 21 may serve as a signal output line (OUT _ n) of the nth stage GOA circuit, and may be located on a side of the nth stage GOA circuit remote from the (n +1) th stage GOA circuit. For the n +1 th-stage GOA circuit, the first scan signal line 21 may serve as a signal output line (OUT _ n +1) of the n +1 th-stage GOA circuit, and may be located on a side of the n +1 th-stage GOA circuit away from the n-th-stage GOA circuit.

In an exemplary embodiment, after the first conductive layer pattern is formed, a semiconductor layer may be subjected to a semiconductor process using the first conductive layer as a mask, channel regions of the plurality of transistors may be formed in the semiconductor layer in a region masked by the first conductive layer, and the semiconductor layer in a region not masked by the first conductive layer may be subjected to a semiconductor process, that is, both the first region and the second region of the plurality of active layers may be subjected to a semiconductor process.

(3) Forming a second conductive layer pattern. In an exemplary embodiment, the forming of the second conductive layer pattern may include: a third insulating film and a second conductive film are sequentially deposited on the substrate with the patterns formed thereon, and the second conductive film is patterned by a patterning process to form a third insulating layer covering the first conductive layer and a second conductive layer pattern disposed on the third insulating layer, where the second conductive layer pattern may include a second pixel conductive layer disposed in the pixel circuit region and a second gate conductive layer disposed in the gate circuit region, as shown in fig. 16a to 16d, fig. 16a is a schematic diagram of the second pixel conductive layer in the pixel circuit region, fig. 16b is a schematic diagram of the second gate conductive layer in the first gate circuit region, fig. 16c is a schematic diagram of the second gate conductive layer in the second gate circuit region, and fig. 16d is a schematic diagram of the second gate conductive layer in the third gate circuit region. In an exemplary embodiment, the second conductive layer may be referred to as a second GATE metal (GATE2) layer.

Fig. 16a illustrates a planar structure of one repeating unit (12 pixel driving circuits) in the pixel circuit region, and as shown in fig. 16a, in an exemplary embodiment, the second pixel conductive layer in the pixel circuit region may include at least: an initial connection line 31 and a second plate 32.

In an exemplary embodiment, the initial connection line 31 may be a line shape in which the body portion extends in the first direction X, the initial connection line 31 of the n-1 th cell row may be located between the third scan signal line 23 and the light emission control line 24, the initial connection line 31 of the n-th cell row may be located between the third scan signal line 23 and the power supply connection line 25, and an initial connection bump is provided on the initial connection line 31 of each circuit unit, the initial connection bump extending toward the third scan signal line 23. The initial connection line 31 is configured to be connected to an initial signal line formed subsequently, and the initial connection protrusion is configured to be connected to a first pole of a fifth transistor T5 formed subsequently, so that the initial signal line provides the same initial voltage to the plurality of pixel driving circuits in one unit row through the initial connection line 31, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

In an exemplary embodiment, the second plate 32 is positioned between the first scanning signal line 21 and the third scanning signal line 23 as another plate of the storage capacitor, an orthogonal projection of the second plate 32 on the substrate at least partially overlaps an orthogonal projection of the first plate 26 on the substrate, and the first plate 26 and the second plate 32 constitute a storage capacitor of the pixel driving circuit.

In an exemplary embodiment, the second plate 32 may have a rectangular shape, and corners of the rectangular shape may be provided with chamfers. A second opening is disposed on a side of the second plate 32 facing the first scanning signal line 21, and the second opening exposes the second region of the first active layer. A side of the second plate 32 facing the third scanning signal line 23 is provided with a plate connection protrusion extending in a direction of the third scanning signal line 23, the plate connection protrusion being configured to be connected with a second pole of a fifth transistor T5 to be formed later.

In an exemplary embodiment, the second pixel conductive layer in the n-1 th cell row and the n-th cell row may be mirror-symmetrical with respect to the first direction reference line X1.

In an exemplary embodiment, the second pixel conductive layer in the adjacent cell column may be mirror-symmetrical with respect to the cell column center line.

In an exemplary embodiment, in one repeating unit, the second pixel conductive layers in the plurality of unit columns on both sides of the repeating unit center line may be mirror-symmetrical with respect to the repeating unit center line.

Fig. 16b, fig. 16c, and fig. 16d respectively illustrate the planar structures of the second gate conductive layers of the first region, the second region, and the third region in one gate circuit region, where the second gate conductive layers in the three regions together form a complete second gate conductive layer of the GOA circuit, the nth GOA circuit may be above the first reference line X1, and the (n +1) th GOA circuit may be below the first reference line X1. As shown in fig. 16b, 16c and 16d, in an exemplary embodiment, the second gate conductive layer in the gate circuit region may include: an eleventh connection line 311, a twelfth connection line 312, a thirteenth connection line 313, a fourteenth connection line 314, a fifteenth connection line 315, a sixteenth connection line 316, a seventeenth connection line 317, a fourth plate 324, and a sixth plate 326.

In an exemplary embodiment, a first end of the eleventh connection line 311 may be positioned at a side opposite to the eleventh active layer first direction X, and a second end of the eleventh connection line 311 extends along the first direction X to a side opposite to the twelfth active layer first direction X. In an exemplary embodiment, a first end of the eleventh connection line 311 is configured to be connected to a subsequently formed second signal input line (CNB), and a second end of the eleventh connection line 311 is configured to be connected to a first pole of a subsequently formed twelfth transistor T12.

In an exemplary embodiment, a first end of the twelfth connection line 312 may be positioned at one side of the eleventh gate electrode line 211 in the first direction X, and a second end of the twelfth connection line 312 may extend along the first direction X to one side of the eighteenth gate electrode line 218 opposite to the first direction X. A first end of the twelfth connection line 312 is configured to be connected to a signal output line of a subsequently formed GOA circuit of this stage, a second end of the twelfth connection line 312 is configured to be connected to the eighteenth gate electrode line 218 through a subsequently formed connection electrode, and the twelfth connection line 312 may be configured to serve as an output connection line. For the nth-stage GOA circuit, the first end of the twelfth connection line 312 is configured to be connected with the subsequently formed nth-stage output line (OUT _ n), and for the (n +1) th-stage GOA circuit, the first end of the twelfth connection line 312 is configured to be connected with the subsequently formed (n +1) th-stage output line (OUT _ n + 1).

In an exemplary embodiment, a first end of the thirteenth connection line 313 may be positioned at one side of the twenty-first active layer 121 in the first direction X, and a second end of the thirteenth connection line 313 may extend along the first direction X to near the fourth electrode plate 324. A first end of the thirteenth connection line 313 is configured to be connected to a second pole of the twenty-first transistor T21 that is formed subsequently, a second end of the thirteenth connection line 313 is configured to be connected to a low voltage power supply line (VGL) that is formed subsequently, and the thirteenth connection line 313 may be configured to be a low voltage connection line. In an exemplary embodiment, the thirteenth connection line 313 of the nth stage GOA circuit and the (n +1) th stage GOA circuit may be an integrated structure connected to each other.

In an exemplary embodiment, a first end of the fourteenth connection line 314 may be located at one side of the first direction X of the sixteenth gate electrode line 216, and a second end of the fourteenth connection line 314 may extend along the first direction X to be adjacent to the fourth plate 324. A first end of the fourteenth connection line 314 is configured to be connected to the sixteenth gate electrode line 216 through a subsequently formed connection electrode, a second end of the fourteenth connection line 314 is configured to be connected to the third plate 233 through a subsequently formed connection electrode, and the fourteenth connection line 314 may be configured to be a pull-up node line (PU).

In an exemplary embodiment, a plurality of fifteenth connection lines 315 may be positioned between the adjacent fourteenth active layers 114, the plurality of fifteenth connection lines 315 being configured as connection lines between the first poles of the plurality of fourteenth transistors T14.

In an exemplary embodiment, a first end of the sixteenth connection line 316 may be located at one side of the fourteenth active layer in the first direction X, and a second end of the sixteenth connection line 316 may extend along the first direction X and then be connected to the fourth plate 324. The first end of the sixteenth connection line 316 is configured to be connected to the first pole of the fourteenth transistor T14, and the connection of the fourth plate 324 to the first pole of the fourteenth transistor T14 is realized.

In an exemplary embodiment, a first end of the seventeenth connection line 317 may be positioned at one side of the eighteenth gate electrode line 218 in the first direction X, and a second end of the seventeenth connection line 317 may be positioned at one side of the fourteenth active layer 114 in the opposite direction to the first direction X. A first end of the seventeenth connection line 317 is configured to be connected to the eighteenth gate electrode line 218 through a subsequently formed connection electrode, and a second end of the seventeenth connection line 317 is configured to be connected to a first pole of a subsequently formed fourteenth transistor T14, so that connection of the gate electrode of the eighteenth transistor T18 to the first pole of the fourteenth transistor T14 is achieved.

In an exemplary embodiment, the fourth plate 324 may include a plurality of rectangular plates connected to each other, and the fourth plate 324 is configured to serve as another plate of the first capacitor. The orthographic projection of the fourth plate 324 on the substrate at least partially overlaps the orthographic projection of the third plate 233 on the substrate such that the third plate 233 and the fourth plate 324 form a first capacitance (C1).

In an exemplary embodiment, the sixth plate 326 may have a rectangular shape, and the sixth plate 326 is configured to serve as the other plate of the second capacitor. The orthographic projection of the sixth plate 326 on the substrate at least partially overlaps the orthographic projection of the fifth plate 235 on the substrate such that the fifth plate 235 and the sixth plate 326 form a second capacitance (C2). Since the fifth plate 235 is connected to the fourteenth gate electrode line 214 that is a pull-down node line (PD), and the sixth plate 326 is connected to the thirteenth connection line 313 that is a low voltage connection line, the potential of the fifth plate 235 is the voltage of the pull-down node line, and the potential of the sixth plate 326 is the voltage of the low voltage power supply line.

(4) A fourth insulating layer pattern is formed. In an exemplary embodiment, the forming of the fourth insulation layer pattern may include: depositing a fourth insulating film on the substrate on which the pattern is formed, patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the second conductive layer, and forming a plurality of via holes, as shown in fig. 17a to 17d, where fig. 17a is a schematic diagram of a plurality of via holes in the pixel circuit region, fig. 17b is a schematic diagram of a plurality of via holes in the first region of the gate circuit region, fig. 17c is a schematic diagram of a plurality of via holes in the second region of the gate circuit region, and fig. 17d is a schematic diagram of a plurality of via holes in the third region of the gate circuit region.

Fig. 17a illustrates a planar structure of one repeating unit (12 pixel driving circuits) in the pixel circuit region, and as shown in fig. 17a, in an exemplary embodiment, the plurality of vias in the pixel circuit region include at least: the first to seventeenth vias V1 to V17.

In an exemplary embodiment, an orthographic projection of the first via V1 on the substrate is within an orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via V1 are etched away to expose a surface of the first region of the first active layer, and the first via V1 is configured to connect a first pole of the subsequently formed first transistor T1 with the first region of the first active layer through the via.

In an exemplary embodiment, an orthographic projection of the second via V2 on the substrate is within an orthographic projection of the second region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away to expose a surface of the second region of the first active layer, and the second via V2 is configured to connect the second pole of the subsequently formed first transistor T1 with the second region of the first active layer through the via.

In an exemplary embodiment, an orthographic projection of the third via V3 on the substrate is within an orthographic projection of the first region of the second active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away to expose a surface of the first region of the second active layer, and the third via V3 is configured to connect a first electrode of the subsequently formed second transistor T2 with the first region of the second active layer through the via.

In an exemplary embodiment, an orthographic projection of the fourth via V4 on the substrate is within an orthographic projection of the second region of the second active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away to expose a surface of the second region of the second active layer, and the fourth via V4 is configured to connect the second pole of the subsequently formed second transistor T2 with the second region of the second active layer through the via.

In an exemplary embodiment, an orthographic projection of the fifth via hole V5 on the substrate is within an orthographic projection of the first region of the third active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via hole V5 are etched away to expose a surface of the first region of the third active layer, and the fifth via hole V5 is configured such that a reference signal line to be subsequently formed is connected to the first region of the third active layer through the via hole.

In an exemplary embodiment, an orthographic projection of the sixth via V6 on the substrate is within an orthographic projection of the second region of the third active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away to expose a surface of the second region of the third active layer, and the sixth via V6 is configured to connect the second pole of the subsequently formed third transistor T3 with the second region of the third active layer through the via. In an exemplary embodiment, the fifth via V5 and the sixth via V6 are provided in the circuit cell in which the reference signal line is provided in one repeating unit, and the other circuit cells are provided with only the sixth via V6. For example, the fifth via hole V is provided in the circuit cells of the m +2 th cell column and the m +3 th cell column, and the fifth via hole V is not provided in the circuit cells of the m +1 th cell column, the m +4 th cell column, and the m +5 th cell column.

In an exemplary embodiment, an orthographic projection of the seventh via V7 on the substrate is within an orthographic projection of the first region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away to expose a surface of the first region of the fourth active layer, and the seventh via V7 is configured to connect a first pole of a subsequently formed fourth transistor T4 with the first region of the fourth active layer through the via.

In an exemplary embodiment, an orthographic projection of the eighth via V8 on the substrate is within an orthographic projection of the second region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eighth via V8 are etched away to expose a surface of the second region of the fourth active layer, and the eighth via V8 is configured to connect the second pole of the subsequently formed fourth transistor T4 with the second region of the fourth active layer through the via.

In an exemplary embodiment, an orthographic projection of the ninth via V9 on the substrate is within an orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the ninth via V9 are etched away to expose a surface of the first region of the fifth active layer, and the ninth via V9 is configured to connect a first pole of the subsequently formed fifth transistor T5 with the first region of the fifth active layer through the via.

In an exemplary embodiment, an orthographic projection of the tenth via V10 on the substrate is within an orthographic projection of the second region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the tenth via V10 are etched away to expose a surface of the second region of the fifth active layer, and the tenth via V10 is configured to connect the second pole of the subsequently formed fifth transistor T5 with the second region of the fifth active layer through the via.

In an exemplary embodiment, an orthographic projection of the eleventh via V11 on the substrate is within an orthographic projection of the first plate 26 on the substrate, the fourth insulating layer and the third insulating layer within the eleventh via V11 are etched away to expose a surface of the first plate 26, and the eleventh via V11 is configured to connect the second pole of the subsequently formed fourth transistor T4 with the first plate 26 through the via.

In an exemplary embodiment, an orthographic projection of the twelfth via V12 on the substrate is within an orthographic projection of the second plate 32 on the substrate, the fourth insulating layer within the twelfth via V12 is etched away to expose a surface of the second plate 32, and the twelfth via V12 is configured to connect the second pole of the subsequently formed first transistor T1 with the second plate 32 through the via.

In an exemplary embodiment, an orthogonal projection of the thirteenth via V13 on the substrate is within an orthogonal projection of the plate connection protrusion of the second plate 32 on the substrate, the fourth insulating layer in the thirteenth via V13 is etched away to expose a surface of the plate connection protrusion of the second plate 32, and the thirteenth via V13 is configured to connect the second pole of the subsequently formed fifth transistor T5 with the second plate 32 through the via.

In an exemplary embodiment, an orthographic projection of the fourteenth via V14 on the substrate is within an orthographic projection of the power connection protrusion of the power connection line 25 on the substrate, the fourth insulating layer and the third insulating layer within the fourteenth via V14 are etched away to expose a surface of the power connection protrusion of the power connection line 25, and the fourteenth via V14 is configured such that a first pole of the subsequently formed second transistor T2 is connected to the power connection line 25 through the via.

In an exemplary embodiment, an orthographic projection of the fifteenth via V15 on the substrate is within an orthographic projection of the initial connection bump of the initial connection line 31 on the substrate, the fourth insulating layer within the fifteenth via V15 is etched away to expose a surface of the initial connection bump of the initial connection line 31, and the fifteenth via V15 is configured to connect a first pole of a subsequently formed fifth transistor T5 with the initial connection line 31 through the via.

In an exemplary embodiment, an orthographic projection of the sixteenth via V16 on the substrate is within an orthographic projection of the power connection line 25 on the substrate, the fourth insulating layer and the third insulating layer within the sixteenth via V16 are etched away to expose a surface of the power connection line 25, and the sixteenth via V16 is configured to connect a subsequently formed first power line to the power connection line 25 through the via. In an exemplary embodiment, a sixteenth via V16 is provided in a circuit unit in which the first power supply line is provided in one repeating unit. For example, the sixteenth via V16 is provided in the circuit cells of the m-th cell column and the m + 5-th cell column, and the sixteenth via is not provided in the circuit cells of the m + 1-th to m + 4-th cell columns.

In an exemplary embodiment, an orthographic projection of the seventeenth via V17 on the substrate is within an orthographic projection of the initial connection line 31 on the substrate, the fourth insulating layer within the seventeenth via V17 is etched away to expose a surface of the initial connection line 31, and the seventeenth via V17 is configured to connect a subsequently formed initial signal line to the initial connection line 31 through the via. In an exemplary embodiment, a seventeenth via V17 is provided in a circuit unit in which an initial signal line is provided in one repeating unit. For example, the seventeenth via V17 may be disposed between the m +2 th cell column and the m +3 th cell column, and the circuit cells of the other cell columns are not disposed with the seventeenth via.

In an exemplary embodiment, the plurality of vias in the n-1 th cell row and the n-th cell row may be mirror-symmetrical with respect to the first direction reference line X1.

In an exemplary embodiment, the plurality of vias in adjacent cell columns may be mirror symmetric with respect to the cell column center line.

In an exemplary embodiment, in one repeating unit, the plurality of vias in the plurality of unit columns on both sides of the repeating unit center line may be mirror-symmetrical with respect to the repeating unit center line.

Fig. 17b, 17c, and 17d respectively illustrate a planar structure of a plurality of vias in the first region, the second region, and the third region of one gate circuit region, where the plurality of vias in the three regions together form a complete via pattern of the GOA circuit, the nth GOA circuit may be above the first reference line X1, and the (n +1) th GOA circuit may be below the first reference line X1. As shown in fig. 17b, 17c and 17d, in an exemplary embodiment, the plurality of vias in the gate circuit region may include: the thirty-first to fifty-second vias V31 to V52, the fifty-fourth to seventy-seventh vias V54 to V77, and the eighty-first to ninety-sixth vias V81 to V96.

In an exemplary embodiment, an orthographic projection of the thirty-first via V31 on the substrate is within an orthographic projection of the first region of the eleventh active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the thirty-first via V31 are etched away to expose a surface of the first region of the eleventh active layer, and the thirty-first via V31 is configured to connect a subsequently formed first signal input line (CN) with the first region of the eleventh active layer through the via.

In an exemplary embodiment, an orthographic projection of the thirty-second via V32 on the substrate is within an orthographic projection of the second region of the eleventh active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the thirty-second via V32 are etched away to expose a surface of the second region of the eleventh active layer, and the thirty-second via V32 is configured to connect the second pole of the subsequently formed eleventh transistor T11 with the second region of the eleventh active layer through the via.

In an exemplary embodiment, an orthographic projection of the thirty-third via V33 on the substrate is within an orthographic projection of the first region of the twelfth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the thirty-third via V33 are etched away to expose a surface of the first region of the twelfth active layer, and the thirty-third via V33 is configured to connect the first pole of the subsequently formed twelfth transistor T12 with the first region of the twelfth active layer through the via.

In an exemplary embodiment, an orthographic projection of the thirty-fourth via V34 on the substrate is within an orthographic projection of the second region of the twelfth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the thirty-fourth via V34 are etched away to expose a surface of the second region of the twelfth active layer, and the thirty-fourth via V34 is configured to connect the second pole of the subsequently formed twelfth transistor T12 with the second region of the twelfth active layer through the via.

In an exemplary embodiment, an orthographic projection of the plurality of fifteenth third via holes V35 on the substrate is within an orthographic projection of a first region of the plurality of output active layers (the first output active layer, the second output active layer, and the third output active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the thirty-fifth via holes V35 are etched away to expose a surface of the first region of the output active layer, and the thirty-fifth via holes V35 are configured such that the subsequently formed clock signal lines (the first clock signal line CLK and the second clock signal line CLKB) are connected to the first region of the output active layer through the via holes. In an exemplary embodiment, the thirty-fifth via hole V35 may be plural for each output active layer.

In an exemplary embodiment, an orthographic projection of the plurality of thirty-sixth vias V36 on the substrate is within an orthographic projection of the second region of the plurality of output active layers on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the thirty-sixth vias V36 are etched away to expose a surface of the second region of the output active layers, and the thirty-sixth vias V36 are configured to connect the second pole of the subsequently formed output transistor with the second region of the output active layers through the vias. In an exemplary embodiment, the thirty-sixth via V36 may be plural for each output active layer, and may be respectively located at both sides of the thirty-fifth via V35 in the second direction Y.

In an exemplary embodiment, an orthographic projection of the plurality of thirty-seventh vias V37 on the substrate is within an orthographic projection of the first region of the plurality of fourteenth active layers on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the thirty-seventh vias V37 are etched away to expose a surface of the first region of the fourteenth active layer, and the thirty-seventh vias V37 are configured to connect the first pole of the subsequently formed fourteenth transistor T14 with the first region of the fourteenth active layer through the vias. In an exemplary embodiment, the thirty-seventh via V37 may be plural for each fourteenth active layer.

In an exemplary embodiment, an orthographic projection of the plurality of thirty-eighth vias V38 on the substrate is within an orthographic projection of the second region of the plurality of fourteenth active layers on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the thirty-eighth vias V38 are etched away to expose a surface of the second region of the fourteenth active layer, and the thirty-eighth vias V38 are configured to connect the second pole of the subsequently formed fourteenth transistor T14 with the second region of the fourteenth active layer through the vias. In an exemplary embodiment, the thirty-eighth via V38 may be plural for each fourteenth active layer.

In an exemplary embodiment, an orthographic projection of the thirty-ninth via V39 on the substrate is within an orthographic projection of the first region of the fifteenth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the thirty-ninth via V39 are etched away to expose a surface of the first region of the fifteenth active layer, and the thirty-ninth via V39 is configured to connect the first pole of the subsequently formed fifteenth transistor T15 with the first region of the fifteenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-first via V40 on the substrate is within an orthographic projection of the second region of the fifteenth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the forty-first via V40 are etched away to expose a surface of the second region of the fifteenth active layer, and the forty-first via V40 is configured to connect the second pole of the subsequently formed fifteenth transistor T15 with the second region of the fifteenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-first via V41 on the substrate is within an orthographic projection of the first region of the sixteenth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the forty-first via V41 are etched away to expose a surface of the first region of the sixteenth active layer, and the forty-first via V41 is configured to connect the first pole of the subsequently formed sixteenth transistor T16 with the first region of the sixteenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-second via V42 on the substrate is within an orthographic projection of the second region of the sixteenth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the forty-second via V42 are etched away to expose a surface of the second region of the sixteenth active layer, and the forty-second via V42 is configured to connect the second pole of the subsequently formed sixteenth transistor T16 with the second region of the sixteenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-third via V43 on the substrate is within an orthographic projection of the first region of the seventeenth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the forty-third via V43 are etched away to expose a surface of the first region of the seventeenth active layer, and the forty-third via V43 is configured such that a subsequently formed clock signal line is connected to the first region of the seventeenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-fourth via V44 on the substrate is within an orthographic projection of a second region of the seventeenth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the forty-fourth via V44 are etched away to expose a surface of the second region of the seventeenth active layer, and the forty-fourth via V44 is configured to connect a second pole of a subsequently formed seventeenth transistor T17 with the second region of the seventeenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-fifth via V45 on the substrate is within an orthographic projection of the first region of the eighteenth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the forty-fifth via V45 are etched away to expose a surface of the first region of the eighteenth active layer, and the forty-fifth via V45 is configured such that the first pole of the subsequently formed eighteenth transistor T18 is connected to the first region of the eighteenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-sixth via V46 on the substrate is within an orthographic projection of the second region of the eighteenth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the forty-sixth via V46 are etched away to expose a surface of the second region of the eighteenth active layer, and the forty-sixth via V46 is configured to connect the second pole of the subsequently formed eighteenth transistor T18 with the second region of the eighteenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-seventh via V47 on the substrate is located within an orthographic projection of the first region of the nineteenth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the forty-seventh via V47 are etched away to expose a surface of the first region of the nineteenth active layer, and the forty-seventh via V47 is configured to connect a subsequently formed enable signal line (EN) with the first region of the nineteenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-eighth via V48 on the substrate is within an orthographic projection of the second region of the nineteenth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the forty-eighth via V48 are etched away to expose a surface of the second region of the nineteenth active layer, and the forty-eighth via V48 is configured to connect the second pole of the subsequently formed nineteenth transistor T19 with the second region of the nineteenth active layer through the via.

In an exemplary embodiment, an orthographic projection of the forty-ninth via V49 on the substrate is within an orthographic projection of the first region of the twentieth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the forty-ninth via V49 are etched away to expose a surface of the first region of the twentieth active layer, and the forty-ninth via V49 is configured to connect the first pole of the subsequently formed twentieth transistor T20 with the first region of the twentieth active layer through the via.

In an exemplary embodiment, an orthographic projection of the fifty-th via V50 on the substrate is within an orthographic projection of a second region of the twentieth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifty-th via V50 are etched away exposing a surface of the second region of the twentieth active layer, and the fifty-th via V50 is configured to connect a second pole of the twenty-th transistor T20, which is subsequently formed, with the second region of the twentieth active layer through the via.

In an exemplary embodiment, an orthographic projection of the fifty-first via V51 on the substrate is within an orthographic projection of a first region of the twenty-first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifty-first via V51 are etched away to expose a surface of the first region of the twenty-first active layer, and the fifty-first via V51 is configured to connect a first pole of a subsequently formed twenty-first transistor T21 with the first region of the twenty-first active layer through the via.

In an exemplary embodiment, an orthographic projection of the fifty-second via V52 on the substrate is within an orthographic projection of a second region of the twenty-first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifty-second via V52 are etched away to expose a surface of the second region of the twenty-first active layer, and the fifty-second via V52 is configured to connect a second pole of the subsequently formed twenty-first transistor T21 with the second region of the twenty-first active layer through the via.

In an exemplary embodiment, an orthographic projection of the fifty-fourth via V54 on the substrate is within an orthographic projection of the second end of the twenty-first gate electrode line 221 on the substrate, the fourth insulating layer and the third insulating layer within the fifty-fourth via V54 are etched away to expose a surface of the second end of the twenty-first gate electrode line 221, and the fifty-fourth via V54 is configured to connect a subsequently formed reset signal line (RST) with the twenty-first gate electrode line 221 through the via.

In an exemplary embodiment, an orthographic projection of the fifty-fifth via hole V55 on the substrate is located within an orthographic projection of the first end of the first connection line 241 on the substrate, the fourth and third insulating layers within the fifty-fifth via hole V55 are etched away to expose a surface of the first end of the first connection line 241, and the fifty-fifth via hole V55 is configured to connect the second pole of the subsequently formed eleventh transistor T11 with the first connection line 241 through the via hole.

In an exemplary embodiment, an orthographic projection of the fifty-sixth via V56 on the substrate is within an orthographic projection of the second end of the first connection line 241 on the substrate, the fourth insulating layer and the third insulating layer within the fifty-sixth via V56 are etched away to expose a surface of the second end of the first connection line 241, and the fifty-sixth via V56 is configured to connect the second pole of the subsequently formed twelfth transistor T12 with the first connection line 241 through the via.

In an exemplary embodiment, an orthogonal projection of the fifty-seventh via V57 on the substrate is located within an orthogonal projection of the second end of the eleventh gate electrode line 211 on the substrate, the fourth insulating layer and the third insulating layer in the fifty-seventh via V57 are etched away to expose a surface of the second end of the eleventh gate electrode line 211, and the fifty-seventh via V57 is configured to be connected to a first control line (an output signal line of a previous stage GOA circuit) to be formed later. For the nth stage GOA circuit, the fifty-seventh via V57 is configured to be connected to the output signal line OUT _ n-1 of the nth-1 stage GOA circuit. For the n +1 th-stage GOA circuit, the fifty-seventh via V57 is configured to be connected to the output signal line OUT _ n of the nth-stage GOA circuit.

In an exemplary embodiment, an orthogonal projection of the fifty-eighth via V58 on the substrate is located within an orthogonal projection of the second end of the twelfth gate electrode line 212 on the substrate, the fourth insulating layer and the third insulating layer in the fifty-eighth via V58 are etched away to expose a surface of the second end of the twelfth gate electrode line 212, and the fifty-eighth via V58 is configured to connect a second control line (an output signal line of a next-stage GOA circuit) to be formed later with the second end of the twelfth gate electrode line 212 through the via. For the nth-stage GOA circuit, the fifty-eighth via V58 is configured to be connected to the output signal line OUT _ n +1 of the subsequently formed (n +1) th-stage GOA circuit. For the n +1 th-stage GOA circuit, the fifty-eighth via V58 is configured to be connected to the output signal line OUT _ n +2 of the subsequently formed n +2 th-stage GOA circuit.

In an exemplary embodiment, an orthographic projection of the fifty-ninth via V59 on the substrate is within an orthographic projection of the first end of the fourth link line 244 on the substrate, the fourth insulating layer and the third insulating layer within the fifty-ninth via V59 are etched away to expose a surface of the first end of the fourth link line 244, and the fifty-ninth via V59 is configured to connect the second pole of the subsequently formed twelfth transistor T12 with the first end of the fourth link line 244 through the via.

In an exemplary embodiment, an orthographic projection of the sixty via V60 on the substrate is located within an orthographic projection of the second end of the fourth connection line 244 on the substrate, the fourth insulating layer and the third insulating layer within the sixty via V60 are etched away to expose a surface of the second end of the fourth connection line 244, and the sixty via V60 is configured to connect the first pole of the subsequently formed twenty-first transistor T21 with the second end of the fourth connection line 244 through the via.

In an exemplary embodiment, an orthographic projection of the sixty-first via V61 on the substrate is located within an orthographic projection of the first end of the sixteenth gate electrode line 216 on the substrate, the fourth insulating layer and the third insulating layer within the sixty-first via V61 are etched away to expose a surface of the first end of the sixty-first gate electrode line 216, and the sixty-first via V61 is configured to connect the first pole of the subsequently formed twenty-first transistor T21 with the sixty-first gate electrode line 216 through the via.

In an exemplary embodiment, an orthographic projection of the sixty-second via V62 on the substrate is located within an orthographic projection of the second end of the sixteenth gate electrode line 216 on the substrate, the fourth insulating layer and the third insulating layer in the sixty-second via V62 are etched away to expose a surface of the second end of the sixty-second gate electrode line 216, and the sixty-second via V62 is configured to connect the fourteenth connection line 314 and the sixty-second gate electrode line 216 through a subsequently formed connection electrode.

In an exemplary embodiment, an orthographic projection of the sixty-third via V63 on the substrate is located within an orthographic projection of the sixty-third gate electrode line 216 on the substrate and between the sixty-first via V61 and the sixty-second via V62, the fourth insulating layer and the third insulating layer within the sixty-third via V63 are etched away to expose a surface of the sixty-gate electrode line 216, and the sixty-third via V63 is configured to connect the first pole of the subsequently formed fifteenth transistor T15 with the sixty-gate electrode line 216 through the via.

In an exemplary embodiment, an orthographic projection of the sixty-fourth via V64 on the substrate is within an orthographic projection of the fifteenth gate electrode line 215 on the substrate, the fourth insulating layer and the third insulating layer within the sixty-fourth via V64 are etched away to expose a surface of the fifteenth gate electrode line 215, and the sixty-fourth via V64 is configured such that a first pole of a subsequently formed sixteenth transistor T16 is connected to the fifteenth gate electrode line 215 through the via. In an exemplary embodiment, since the 2 sixteenth transistors T16 are included in the GOA circuit, the number of the sixty-four vias V64 may be 2.

In an exemplary embodiment, orthographic projections of the sixty-fifth via V65 and the sixty-sixth via V66 on the substrate are located within an orthographic projection of the eighteenth gate electrode line 218 on the substrate, the fourth insulating layer and the third insulating layer in the sixty-fifth via V65 and the sixty-sixth via V66 are etched away to expose surfaces of the first end and the second end of the eighteenth gate electrode line 218, respectively, the sixty-fifth via V65 is configured to connect the eighteenth gate electrode line 218 and the twelfth connecting line 312 through a subsequently formed connecting electrode, and the sixty-sixth via V66 is configured to connect the eighteenth gate electrode line 218 and the seventeenth connecting line 317 through a subsequently formed connecting electrode.

In an exemplary embodiment, an orthogonal projection of the sixty-seventh via V67 on the substrate is located within an orthogonal projection of the second end of the seventeenth gate electrode line 217 on the substrate, the fourth insulating layer and the third insulating layer in the sixty-seventh via V67 are etched away to expose a surface of the second end of the seventeenth gate electrode line 217, and the sixty-seventh via V675 is configured to connect a subsequently formed clock signal line to the seventeenth gate electrode line 217 through the via. For the nth stage GOA circuit, the sixty-seventh via V67 is configured to connect the subsequently formed second clock signal line (CLKB) with the seventeenth gate electrode line 217 through the via. For the n +1 th grade GOA circuit, the sixty-seventh via V67 is configured to connect the first clock signal line (CLK) formed subsequently therethrough with the seventeenth gate electrode line 217.

In an exemplary embodiment, orthographic projections of sixty-eight vias V68 and sixty-nine vias V69 on the substrate are located within an orthographic projection of the fourteenth gate electrode line 214 on the substrate, fourth and third insulating layers within sixty-eight vias V68 and sixty-nine vias V69 are etched away to expose a surface of the fourteenth gate electrode line 214, respectively, sixty-eight vias V68 are configured to connect the second pole of the seventeenth transistor T17 to be subsequently formed with the fourteenth gate electrode line 214 through the vias, and sixty-nine vias V69 are configured to connect the first pole of the eighteenth transistor T18 to the fourteenth gate electrode line 214 through the vias.

In an exemplary embodiment, orthographic projections of the plurality of seventy-fourth and seventy-fourth vias V70 and V71 on the substrate are within an orthographic projection range of the plurality of second connection lines 242 on the substrate, the fourth and third insulating layers within the seventy-fourth and seventy-fourth vias V70 and V71 are etched away to expose surfaces at both ends of the second connection lines 242, respectively, and the plurality of seventy-fourth and seventy-first vias V70 and V71 are configured such that second poles of the plurality of fourteenth transistors T14 formed later connect the plurality of second connection lines 242 through the vias.

In an exemplary embodiment, an orthographic projection of the seventy-second via V72 on the substrate is located within an orthographic projection of the second end of the fourteenth gate electrode line 214 on the substrate, the fourth insulating layer and the third insulating layer in the seventy-second via V72 are etched away to expose a surface of the second end of the fourteenth gate electrode line 214, and the seventy-second via V72 is configured to connect the first pole of the twenty-second transistor T20, which is formed subsequently, with the fourteenth gate electrode line 214 through the via.

In an exemplary embodiment, an orthogonal projection of the seventy-third via V73 on the substrate is within an orthogonal projection range of the connection ends of the nineteenth and twentieth

gate electrode lines

219 and 220 of the integrated structure on the substrate, the fourth and third insulating layers within the seventy-third via V73 are etched away to expose surfaces of the connection ends, and the seventy-third via V73 is configured such that a subsequently formed enable signal line (EN) is simultaneously connected to the nineteenth and twentieth

gate electrode lines

219 and 220 through the via.

In an exemplary embodiment, an orthographic projection of the seventy-fourth via V74 on the substrate is within an orthographic projection of the first end of the third connection line 243 on the substrate, the fourth insulating layer and the third insulating layer within the seventy-fourth via V74 are etched away to expose a surface of the first end of the third connection line 243, and the seventy-fourth via V74 is configured to connect the second pole of the fourteenth transistor T14, which is formed later, with the third connection line 243 through the via.

In an exemplary embodiment, an orthogonal projection of the seventy-fifth via V75 on the substrate is located within an orthogonal projection of the second end of the third link line 243 on the substrate, the fourth and third insulating layers within the seventy-fifth via V75 are etched away to expose a surface of the second end of the third link line 243, and the seventy-fifth via V75 is configured to connect a subsequently formed low voltage power supply line (VGL) to the third link line 243 through the via.

In an exemplary embodiment, an orthographic projection of the seventy-sixth via V76 on the substrate is within an orthographic projection of the second end of the third plate 233 on the substrate, the fourth insulating layer and the third insulating layer in the seventy-sixth via V76 are etched away to expose a surface of the second end of the third plate 233, and the seventy-sixth via V76 is configured to connect the third plate 233 and the fourteenth connection line 314 through a subsequently formed connection electrode.

In an exemplary embodiment, an orthogonal projection of the plurality of seventy-seventh vias V77 on the substrate is located within an orthogonal projection of the first scan signal line 21 on the substrate, the fourth and third insulating layers within the plurality of seventy-seventh vias V77 are etched away to expose surfaces of the first scan signal line 21, respectively, and the plurality of seventy-seventh vias V77 are configured to connect a first pole of a fourteenth transistor T14, which is formed later, and a second pole of the output transistor.

In an exemplary embodiment, an orthographic projection of the eighty-first via V81 on the substrate is located within an orthographic projection of the first end of the eleventh connection line 311 on the substrate, the fourth insulating layer within the eighty-first via V81 is etched away to expose a surface of the first end of the eleventh connection line 311, and the eighty-first via V81 is configured to connect a subsequently formed second signal input line (CNB) to the eleventh connection line 311 through the via.

In an exemplary embodiment, an orthographic projection of the eighty-two via V82 on the substrate is located within an orthographic projection of the second end of the eleventh connection line 311 on the substrate, the fourth insulating layer in the eighty-two via V82 is etched away to expose a surface of the second end of the eleventh connection line 311, and the eighty-two via V82 is configured such that the first pole of the subsequently formed twelfth transistor T12 is connected to the eleventh connection line 311 through the via.

In an exemplary embodiment, an orthographic projection of the eighty-three via V83 on the substrate is located within an orthographic projection of the first end of the twelfth connection line 312 on the substrate, the fourth insulating layer in the eighty-three via V83 is etched away to expose a surface of the first end of the twelfth connection line 312, and the eighty-three via V83 is configured to connect a signal output line of a subsequently formed present-stage GOA circuit to the twelfth connection line 312 through the via. For the nth-stage GOA circuit, the eighty-third via V83 is configured to connect a subsequently formed nth-stage output line (OUT _ n) with the twelfth connection line 312 through the via. For the n +1 th-stage GOA circuit, the eighty-third via V83 is configured to connect the subsequently formed n +1 th-stage output line (OUT _ n +1) with the twelfth connection line 312 through the via.

In an exemplary embodiment, an orthographic projection of the eighty-fourth via V84 on the substrate is located within an orthographic projection of the second end of the twelfth link line 312 on the substrate, the fourth insulating layer in the eighty-fourth via V84 is etched away to expose a surface of the second end of the twelfth link line 312, and the eighty-fourth via V84 is configured to connect the twelfth link line 312 and the eighteenth gate electrode line 218 through a subsequently formed connection electrode.

In an exemplary embodiment, an orthogonal projection of the eighty-fifth via V85 on the substrate is within an orthogonal projection of the first end of the thirteenth connection line 313 on the substrate, the fourth insulating layer within the eighty-fifth via V85 is etched away to expose a surface of the first end of the thirteenth connection line 313, and the eighty-fifth via V85 is configured such that the second pole of the subsequently formed twenty-first transistor T21 is connected to the thirteenth connection line 313 through the via.

In an exemplary embodiment, orthographic projections of the eighty-sixth via V86 and the plurality of eighty-seventh vias V87 on the substrate are located within an orthographic projection of the thirteenth connection line 313 on the substrate, the fourth insulating layers within the eighty-sixth via V86 and the plurality of eighty-seventh vias V87 are etched away to expose a surface of the thirteenth connection line 313, respectively, the eighty-sixth via V86 is configured to connect the second pole of the subsequently formed fifteenth transistor T15 with the thirteenth connection line 313 through the via, and the plurality of eighty-seventh vias V87 is configured to connect the second pole of the subsequently formed sixteenth transistor T16, the second pole of the eighteenth transistor T18, and the second pole of the twentieth transistor T20 with the thirteenth connection line 313 through the vias.

In an exemplary embodiment, an orthographic projection of the eighty-eight via V88 on the substrate is within an orthographic projection of the first end of the fourteenth connection line 314 on the substrate, the fourth insulating layer in the eighty-eight via V88 is etched away to expose a surface of the first end of the fourteenth connection line 314, and the eighty-eight via V88 is configured to connect the fourteenth connection line 314 and the sixteenth gate electrode line 216 through a subsequently formed connection electrode.

In an exemplary embodiment, an orthographic projection of the eighty-nine via V89 on the substrate is located within an orthographic projection of the second end of the fourteenth connection line 314 on the substrate, the fourth insulating layer in the eighty-nine via V89 is etched away to expose a surface of the second end of the fourteenth connection line 314, and the eighty-nine via V89 is configured to connect the fourteenth connection line 314 and the third plate 233 through a subsequently formed connection electrode.

In an exemplary embodiment, an orthogonal projection of the ninety via V90 on the substrate is located within an orthogonal projection of the first end of the seventeenth connection line 317 on the substrate, the fourth insulating layer within the ninety via V90 is etched away to expose a surface of the first end of the seventeenth connection line 317, and the ninety via V90 is configured to connect the seventeenth connection line 317 and the eighteenth gate electrode line 218 through a subsequently formed connection electrode.

In an exemplary embodiment, an orthogonal projection of the ninety first via V91 on the substrate is located within an orthogonal projection of the second end of the seventeenth connection line 317 on the substrate, the fourth insulating layer within the ninety first via V91 is etched away to expose a surface of the second end of the seventeenth connection line 317, and the ninety first via V91 is configured to connect the first pole of the subsequently formed fourteenth transistor T14 with the seventeenth connection line 317 through the via.

In an exemplary embodiment, the orthographic projection of the plurality of ninety-second vias V92 and the plurality of ninety-third vias V93 on the substrate is within the orthographic projection of the plurality of fifteenth connection lines 315 on the substrate, the fourth insulating layer within the ninety-second vias V92 and the ninety-third vias V93 is etched away exposing the surfaces at both ends of the fifteenth connection line 315, and the plurality of ninety-second vias V92 and the plurality of ninety-third vias V93 are configured to connect the first poles of the subsequently formed plurality of fourteenth transistors T14 with the plurality of fifteenth connection lines 315 through the vias.

In an exemplary embodiment, an orthographic projection of the ninety-fourth via V94 on the substrate is within an orthographic projection of the first end of the sixteenth connection line 316 on the substrate, the fourth insulating layer within the ninety-fourth via V94 is etched away to expose a surface of the first end of the sixteenth connection line 316, and the ninety-fourth via V94 is configured to connect the first pole of the subsequently formed fourteenth transistor T14 with the sixteenth connection line 316 through the via.

In an exemplary embodiment, an orthogonal projection of the ninety-fifth via V95 on the substrate is within an orthogonal projection of the sixteenth connection line 316 on the substrate, the fourth insulating layer within the ninety-fifth via V95 is etched away to expose a surface of the sixteenth connection line 316, and the ninety-fifth via V95 is configured to connect the second pole of the subsequently formed nineteenth transistor T19 with the sixteenth connection line 316 through the via.

In an exemplary embodiment, an orthogonal projection of the ninety-sixth via V96 on the substrate is located within an orthogonal projection of the second end of the thirteenth connection line 313 on the substrate, the fourth insulating layer within the ninety-sixth via V96 is etched away to expose a surface of the second end of the thirteenth connection line 313, and the ninety-sixth via V96 is configured to connect a subsequently formed low voltage power supply line (VGL) with the thirteenth connection line 313 through the via.

(5) Forming a third conductive layer pattern. In an exemplary embodiment, the forming of the third conductive layer may include: depositing a third conductive film on the substrate on which the pattern is formed, patterning the third conductive film by a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, where the third conductive layer may include a third pixel conductive layer disposed in the pixel circuit region and a third gate conductive layer disposed in the gate circuit region, as shown in fig. 18a to 18d, fig. 18a is a schematic diagram of the third pixel conductive layer in the pixel circuit region, fig. 18b is a schematic diagram of the third gate conductive layer in the first region of the gate circuit region, fig. 18c is a schematic diagram of the third gate conductive layer in the second region of the gate circuit region, and fig. 18d is a schematic diagram of the third gate conductive layer in the third region of the gate circuit region. In an exemplary embodiment, the third conductive layer may be referred to as a first source drain metal (SD1) layer.

Fig. 18a illustrates a planar structure of one repeating unit (12 pixel driving circuits) in the pixel circuit region, and as shown in fig. 18a, in an exemplary embodiment, the third pixel conductive layer in the pixel circuit region includes at least: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a first power line 47, a data signal line 48, a reference signal line 49, and an initial signal line 50.

In an exemplary embodiment, the first connection electrode 41 may have a line shape in which the body portion extends in the second direction Y, a first end of the first connection electrode 41 is connected to the first region of the first active layer through the first via V1, and a second end of the first connection electrode 41 is connected to the second region of the second active layer through the fourth via V4, such that the first region of the first active layer and the second region of the second active layer have the same potential. In an exemplary embodiment, the first connection electrode 41 may serve as a first pole of the first transistor T1 and a second pole of the second transistor T2. In an exemplary embodiment, the first connection electrodes 41 in two circuit cells adjacent in the second direction Y may be an integral structure connected to each other, implementing the pixel driving circuits in the nth cell row and the n-1 st cell row sharing the second transistor T2.

In an exemplary embodiment, the second connection electrode 42 may have a bar shape in which a body portion extends along the first direction X, a first end of the second connection electrode 42 is connected to the second region of the first active layer through a second via hole V2, and a second end of the second connection electrode 42 is connected to the second electrode plate 32 through a twelfth via hole V12, such that the second region of the first active layer and the second electrode plate 32 have the same potential. In an exemplary embodiment, the second connection electrode 42 may serve as a second pole of the first transistor T1.

In an exemplary embodiment, the third connection electrode 43 may have a line shape in which the body portion extends along the second direction Y, a first end of the third connection electrode 43 is connected to the second region of the third active layer through a sixth via V6, a middle portion of the third connection electrode 43 is connected to the second region of the fourth active layer through an eighth via V8, and a second end of the third connection electrode 43 is connected to the first plate 26 through an eleventh via V11, such that the second region of the third active layer, the second region of the fourth active layer, and the first plate 26 have the same potential. In an exemplary embodiment, the third connection electrode 43 may serve as the second pole of the third transistor T3 and the second pole of the fourth transistor T4.

In an exemplary embodiment, the fourth connection electrode 44 may have a rectangular shape, a first end of the fourth connection electrode 44 is connected to the second region of the fifth active layer through a tenth via V10, and a second end of the fourth connection electrode 44 is connected to the second electrode plate 32 through a thirteenth via V13, such that the second region of the fifth active layer and the second electrode plate 32 have the same potential. In an exemplary embodiment, the fourth connection electrode 44 may serve as a second pole of the fifth transistor T5.

In an exemplary embodiment, the fifth connection electrode 45 may have a bar shape in which a body portion extends in the first direction X, a first end of the fifth connection electrode 45 is connected to the initial connection bump of the initial connection line 31 through a fifteenth via V15, and a second end of the fifth connection electrode 45 is connected to the first region of the fifth active layer through a ninth via V9, such that the initial connection line 31 and the first region of the fifth active layer have the same potential. In an exemplary embodiment, the fifth connection electrode 45 may serve as a first pole of the fifth transistor T5.

In an exemplary embodiment, the sixth connection electrode 46 may have a bar shape in which a body portion extends along the first direction X, a first end of the sixth connection electrode 46 is connected to the power connection protrusion of the power connection line 25 through a fourteenth via V14, and a second end of the sixth connection electrode 46 is connected to the first region of the second active layer through a third via V3, such that the power connection line 25 and the first region of the second active layer have the same potential. In an exemplary embodiment, the sixth connection electrode 46 may serve as a first pole of the second transistor T2.

In an exemplary embodiment, the first connection electrode 41, the second connection electrode 42, the third connection electrode 43, and the fourth connection electrode 44 may be disposed in each circuit unit, and two circuit units adjacent in the second direction Y share the fifth connection electrode 45 and the sixth connection electrode 46, the fifth connection electrode 45 may be disposed in the n-1 th unit row, and the sixth connection electrode 46 may be disposed in the n-th unit row.

In an exemplary embodiment, the first power line 47 may have a line shape in which the body portion extends in the second direction Y, and the first power line 47 is connected to the power connection line 25 through a sixteenth via V16 such that the first power line 47 transmits a power voltage to the plurality of circuit cells in one cell row through the power connection line 25. In an exemplary embodiment, in one repeating unit, two first power lines 47 may be disposed at both sides of the repeating unit in the first direction X such that two repeating units adjacent in the first direction X share the first power line 47, and a plurality of unit columns within one repeating unit share the first power line 47. For example, the first power line 47 may be disposed in the m-th cell column and the m + 5-th cell column, and the first power line 47 is not disposed in the m + 1-th cell column to the m + 4-th cell column, so that a one-to-three structure in which the first power line 47 transmits power voltage to three cell columns is formed, which is not only beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate, but also can reduce the number of signal lines and via holes, and save the wiring space.

In an exemplary embodiment, the data signal line 48 may have a line shape in which a body portion extends in the second direction Y, the data signal line 48 is connected to the first region of the fourth active layer through the seventh via hole V7, and transmits a data voltage to the plurality of pixel driving circuits in one cell column. In an exemplary embodiment, the data signal line 48 may be disposed in each cell column in one repeating unit.

In an exemplary embodiment, the reference signal line 49 may have a line shape in which the body portion extends along the second direction Y, and the reference signal line 49 is connected to the first region of the third active layer through the fifth via hole V5 such that the reference signal line 49 transmits a reference voltage to the plurality of pixel driving circuits in one cell row. In an exemplary embodiment, in one repeating unit, two reference signal lines 49 may be disposed at the middle position of the repeating unit such that the reference signal line 49 is shared by a plurality of unit columns. For example, the reference signal line 49 is arranged in the m +2 th unit column and the m +3 th unit column, and the reference signal line 49 is not arranged in the m +2 th unit column, the m +1 th unit column, the m +4 th unit column and the m +5 th unit column, so that a one-to-three structure that one reference signal line 49 transmits reference voltage to three unit columns is formed, which is not only beneficial to improving the uniformity of the panel, avoiding the poor display of the display substrate, ensuring the display effect of the display substrate, but also can reduce the number of signal lines and via holes, and save the wiring space.

In an exemplary embodiment, the initial signal line 50 may have a line shape in which the body portion extends along the second direction Y, and the initial signal line 50 is connected to the initial connection line 31 through a seventeenth via V17 such that the initial signal line 50 transmits an initial voltage to the plurality of pixel driving circuits in one cell row through the initial connection line 31. In an exemplary embodiment, one initial signal line 50 may be disposed at a middle position of a repeating unit in one repeating unit such that the initial signal line 50 is shared by a plurality of unit columns. For example, the initial signal line 50 may be disposed between the m +2 th cell column and the m +3 th cell column, and the initial signal line 50 is not disposed in the m +1 th cell column, the m +4 th cell column, and the m +5 th cell column, so that a one-to-six structure is formed in which the initial signal line 50 transmits the initial voltage to the six cell columns, which is not only beneficial to improving the uniformity of the panel, avoiding the display defect of the display substrate, and ensuring the display effect of the display substrate, but also can reduce the number of the signal lines and the via holes, and save the wiring space.

In an exemplary embodiment, in one repeating unit, a blank region where the third pixel conductive layer is not formed is disposed between at least one adjacent unit column, and the blank region may be configured to be a routing region of the GOA circuit where the first signal input line CN, the second signal input line CNB, the reset signal line RST, the enable signal line EN, the low voltage power supply line VGL, the plurality of first clock signal lines, the plurality of second clock signal lines, and the like are disposed, thereby implementing routing arrangement of the plurality of signal lines extending along the second direction Y. For example, a blank region may be formed between the m-th cell column and the m + 1-th cell column. As another example, a blank region may be formed between the m +4 th cell column and the m +5 th cell column.

In an exemplary embodiment, the first connection electrode 41, the second connection electrode 42, the third connection electrode 43, the fourth connection electrode 44, the first power line 47, the data signal line 48, the reference signal line 49, and the preliminary signal line 50 in the (n-1) th cell row and the (n) th cell row may be mirror-symmetrical with respect to the first direction reference line X1.

In an exemplary embodiment, the third pixel conductive layer in the adjacent cell column may be mirror-symmetrical with respect to the cell column center line.

In an exemplary embodiment, in one repeating unit, the third pixel conductive layers in the plurality of unit columns on both sides of the repeating unit center line may be mirror-symmetrical with respect to the repeating unit center line.

Fig. 18b, 18c, and 18d respectively illustrate the planar structures of the third gate conductive layers in the first region, the second region, and the third region of one gate circuit region, where the third gate conductive layers in the three regions together form a complete third gate conductive layer of a GOA circuit, an nth-level GOA circuit may be above the first reference line X1, and an n + 1-level GOA circuit may be below the first reference line X1. As shown in fig. 18b, 18c and 18d, in an exemplary embodiment, the third gate conductive layer in the gate circuit region may include: a first signal input line 401, a second signal input line 402, a reset signal line 403, an enable signal line 404, a low voltage power supply line 405, a first control line 406 of an nth-level GOA circuit, a second control line 407 of an nth-level GOA circuit, a first control line 408 of an n +1 th-level GOA circuit, a second control line 409 of an n +1 th-level GOA circuit, a first clock first lead 501, a first clock second lead 502, a first clock third lead 503, a first clock fourth lead 504, a second clock first lead 601, a second clock second lead 602, a second clock third lead 603, a second clock fourth lead 604, a twenty-first connection line 421, a twenty-second connection line 422, a twenty-third connection line 423, a twenty-fourth connection line 424, a twenty-fifth connection line 425, a twenty-sixth connection line 426, a twenty-seventh connection line 427, a twenty-eighth connection line 428, a twenty-ninth connection line 429, a twenty-seventh connection line 429, a first control line 501, a second control line 407, a first control line of an nth-level GOA circuit, a first control line of an nth-1, a first control line 408 of an nth-1-fourth clock fourth lead, a second lead 601, a second lead, a fourth lead, a, A thirty-first connection line 430, a thirty-first connection line 431, a thirty-second connection line 432, a thirty-third connection line 433, a thirty-fourth connection line 434, a thirty-fifth connection line 435, a thirty-sixth connection line 436, a thirty-seventh connection line 437, a thirty-eighth connection line 438, a thirty-ninth connection line 439, a forty-fourth connection line 440, a forty-fourth connection line 441, a first output electrode 451, a second output electrode 452, and a third output electrode 453.

In an exemplary embodiment, the first signal input line 401(CN) may have a line shape extending along the second direction Y, and the first signal input line 401 is connected to the first region of the eleventh active layer through the thirty-first via V31, enabling connection of the first pole of the eleventh transistor T11 to the first signal input line 401.

In an exemplary embodiment, the second signal input line 402(CNB) may have a line shape extending along the second direction Y, and the second signal input line 402 is connected to the first end of the eleventh connection line 311 through the eighth eleventh via V81.

In an exemplary embodiment, the reset signal line 403(RST) may have a line shape extending along the second direction Y, and the reset signal line 403 is connected to the second end of the twenty-first gate electrode line 221 through a fifty-fourth via V54. Since the twenty-first gate electrode line 221 serves as a gate electrode of the twenty-first transistor T21, connection of the gate electrode of the twenty-first transistor T21 to the reset signal line 403 is achieved, and the reset signal line 403 controls on and off of the twenty-first transistor T21.

In an exemplary embodiment, the enable signal line 404 may have a line shape extending along the second direction Y, and the enable signal line 404 is connected to the nineteenth and twentieth

gate electrode lines

219 and 220 through a seventeenth via V73 on the one hand, and is connected to the first region of the nineteenth active layer through a forty-seventeenth via V47 on the other hand. Since the nineteenth gate electrode line 219 serves as the gate electrode of the nineteenth transistor T19 and the twentieth gate electrode line 220 serves as the gate electrode of the twentieth transistor T20, it is realized that the gate electrode of the nineteenth transistor T19 and the gate electrode of the twentieth transistor T20 are simultaneously connected to the enable signal line 404, and the gate electrode and the first pole of the nineteenth transistor T19 are connected to each other.

In an exemplary embodiment, the low voltage power line 405 may have a line shape extending along the second direction Y, and the low voltage power line 405 is connected to the second end of the third connection line 243 through the seventeenth via V75 on one hand and the second end of the thirteenth connection line 313 through the ninety-sixth via V96 on the other hand, such that the third connection line 243 and the thirteenth connection line 313 each transmit a low voltage signal provided by the low voltage power line 405 as a low voltage connection line.

In an exemplary embodiment, the first control line in the gate circuit region may include a first control line 406 of the nth stage GOA circuit and a first control line 408 of the (n +1) th stage GOA circuit, the first control line 406 being an output signal line OUT _ n-1 of the (n-1) th stage GOA circuit, the first control line 408 being an output signal line OUT _ n of the nth stage GOA circuit. The second control line in the gate circuit region may include a second control line 407 of the nth stage GOA circuit and a second control line 409 of the n +1 th stage GOA circuit, the second control line 407 being an output signal line OUT _ n +1 of the n +1 th stage GOA circuit, the second control line 409 being an output signal line OUT _ n +2 of the n +2 th stage GOA circuit.

In an exemplary embodiment, the first control line 406 of the nth stage GOA circuit may have a line shape extending along the second direction Y, a first end of the first control line 406 is connected to the output signal line OUT _ n-1 of the nth-1 stage GOA circuit, and a second end of the first control line 406 passes through the pixel circuit region and extends to the gate circuit region, and then is connected to a second end of the eleventh gate electrode line 211 of the nth stage GOA circuit through a seventeenth via V57. Since the eleventh gate electrode line 211 serves as the gate electrode of the eleventh transistor T11, the connection of the gate electrode of the eleventh transistor T11 of the nth-stage GOA circuit with the output signal line OUT _ n-1 of the nth-1-stage GOA circuit, i.e., the output signal line of the previous-stage GOA circuit controls the eleventh transistor T11 of the present stage, is accomplished.

In an exemplary embodiment, the second control line 407 of the nth stage GOA circuit may be a line extending along the second direction Y, a first end of the second control line 407 is connected to the twelfth connection line 312 of the (n +1) th stage GOA circuit through an eighty-three via V83, and a second end of the second control line 407 extends to a region where the nth stage GOA circuit is located and is connected to a second end of the twelfth gate electrode line 212 of the nth stage GOA circuit through a fifty-eight via V58. Since the twelfth gate electrode line 212 serves as the gate electrode of the twelfth transistor T12 and the twelfth connection line 312 of the (n +1) th-stage GOA circuit serves as the output signal line OUT _ n +1 of the (n +1) th-stage GOA circuit, the connection of the gate electrode of the twelfth transistor T12 of the n-th-stage GOA circuit to the output signal line OUT _ n +1 of the (n +1) th-stage GOA circuit is achieved, i.e., the output signal line of the next-stage GOA circuit controls the twelfth transistor T12 of the present stage.

In an exemplary embodiment, the first control line 408 of the (n +1) th GOA circuit may have a line shape extending along the second direction Y, a first end of the first control line 408 is connected to the twelfth connection line 312 of the (n) th GOA circuit through an eighty-third via V83, and after the first end of the first control line 408 extends to a region where the (n +1) th GOA circuit is located, the first end is connected to the second end of the eleventh gate electrode line 211 of the (n +1) th GOA circuit through a seventeenth via V57. Since the eleventh gate electrode line 211 serves as a gate electrode of the eleventh transistor T11 and the twelfth connection line 312 of the nth-stage GOA circuit serves as an output signal line OUT _ n of the nth-stage GOA circuit, connection of the gate electrode of the eleventh transistor T11 of the (n +1) th-stage GOA circuit to the output signal line OUT _ n of the nth-stage GOA circuit, that is, the output signal line of the previous-stage GOA circuit controls the eleventh transistor T11 of the present stage. In addition, the third terminal of the first control line 408 may extend through the pixel circuit region to the region where the n-1 th level GOA circuit is located along the second direction Y as the second control line of the n-1 th level GOA circuit.

In an exemplary embodiment, the second control line 409 of the (n +1) th GOA circuit may have a line shape extending along the second direction Y, a first end of the second control line 409 may be connected to the output signal line OUT _ n +2 of the (n + 2) th GOA circuit, and a second end of the second control line 409 may be connected to a second end of the twelfth gate electrode line 212 of the (n +1) th GOA circuit through a fifty-eight via V58 after passing through the pixel circuit region and extending to the gate circuit region. Since the twelfth gate electrode line 212 serves as the gate electrode of the twelfth transistor T12, connection of the gate electrode of the twelfth transistor T12 of the (n +1) th-stage GOA circuit to the output signal line OUT _ n +2 of the (n + 2) th-stage GOA circuit, i.e., the output signal line of the next-stage GOA circuit controls the twelfth transistor T12 of the present stage, is accomplished.

In an exemplary embodiment, the GOA circuit may include a plurality of first clock signal lines (CLK) and a plurality of second clock signal lines (CLKB), and the plurality of first clock signal lines may include at least a first clock first lead 501, a first clock second lead 502, a first clock third lead 503, and a first clock fourth lead 504. The plurality of second clock signal lines may include at least a second clock first lead 601, a second clock second lead 602, a second clock third lead 603, and a second clock fourth lead 604.

In an exemplary embodiment, the first and second clock first leads 501 and 601 may have a line shape extending along the second direction Y, the first clock first leads 501 are connected to the first regions of the 2 first output active layers of the nth-order GOA circuit through the fifteenth through holes V35, respectively, and the second clock first leads 601 are connected to the first regions of the 2 first output active layers of the n + 1-order GOA circuit through the fifteenth through holes V35, respectively, the first regions of the first output active layers serving as input terminals of the first output transistor T13A.

In an exemplary embodiment, the first and second clock second leads 502 and 602 may have a line shape extending along the second direction Y, the first clock second lead 502 is connected to the first regions of the 2 second output active layers of the nth-order GOA circuit through the fifteenth through hole V35, respectively, and the second clock second lead 602 is connected to the first regions of the 2 second output active layers of the n + 1-order GOA circuit through the fifteenth through hole V35, respectively, the first region of the second output active layer serving as an input terminal of the second output transistor T13B.

In an exemplary embodiment, the first clock third lead 503 and the second clock third lead 603 may have a line shape extending along the second direction Y, the first clock second lead 502 is connected to the first regions of the 2 third output active layers of the nth-stage GOA circuit through the fifteenth via V35, respectively, the second clock third lead 603 is connected to the first regions of the 2 third output active layers of the n +1 th-stage GOA circuit through the fifteenth via V35, respectively, and the first region of the third output active layer serves as an input terminal of the third output transistor T13C.

The first clock fourth lead 504 and the second clock fourth lead 604 may be in the shape of a line extending along the second direction Y. The first clock fourth lead 504 is connected to the seventeenth gate electrode line 217 of the n +1 th-order GOA circuit through a sixteenth through hole V67, on the one hand, and to the first region of the seventeenth active layer of the n +1 th-order GOA circuit through a thirteenth through hole V43, on the other hand, such that the gate electrode and the first electrode of the seventeenth transistor T17 of the n +1 th-order GOA circuit are simultaneously connected to the first clock fourth lead 504. The second clock fourth lead 604 is connected to the seventeenth gate electrode line 217 of the nth grade GOA circuit through a sixteenth through hole V67, on the one hand, and to the first region of the seventeenth active layer of the nth grade GOA circuit through a fourteenth through hole V43, on the other hand, so that the gate electrode and the first pole of the seventeenth transistor T17 of the nth grade GOA circuit are simultaneously connected to the second clock fourth lead 604.

In an exemplary embodiment, the twenty-first connection electrode 421 is connected to the second region of the eleventh active layer through a thirty-second via V32 on the one hand, and is connected to the first end of the first connection line 241 through a fifteenth via V55 on the other hand, and the twentieth connection electrode 421 may serve as a second pole of the eleventh transistor T11.

In an exemplary embodiment, the twenty-second connection electrode 422 is connected to the second terminal of the first connection line 241 through a fifty-sixth via V56, is connected to the second region of the twelfth active layer through a thirty-fourth via V34, is connected to the first terminal of the fourth connection line 244 through a fifty-ninth via V59, and may serve as the second pole of the twelfth transistor T12. Since the twenty-second connection electrode 422 is connected to the twenty-first connection electrode 421 through the first connection line 241, the connection between the second pole of the eleventh transistor T11 and the second pole of the twelfth transistor T12 is accomplished such that both have the same potential.

In an exemplary embodiment, the twenty-third connection electrode 423 is connected to the second terminal of the eleventh connection line 311 through an eighth-twelfth via V82 on the one hand, and is connected to the first region of the twelfth active layer through a third-thirteenth via V33 on the other hand, and the twenty-third connection electrode 423 may serve as the first electrode of the twelfth transistor T12. Since the twenty-third connection electrode 423 is connected to the second signal input line 402 through the eleventh connection line 311, connection between the second signal input line 402 and the first electrode of the twelfth transistor T12 is accomplished.

In an exemplary embodiment, the twenty-fourth connection electrode 424 is connected to the second terminal of the fourth connection line 244 through a sixteenth via V60, is connected to the first region of the twenty-first active layer through a fifth eleventh via V51, is connected to the first terminal of the sixteenth gate electrode line 216 through a sixteenth via V61, and may serve as the first electrode of the twenty-first transistor T21. Since the fourth connection line 244 is connected to the twenty-second connection electrode 422 and the twenty-second connection electrode 422 is connected to the twenty-first connection electrode 421, the interconnection between the second pole of the eleventh transistor T11, the second pole of the twelfth transistor T12, and the first pole of the twenty-first transistor T21 is accomplished.

In an exemplary embodiment, the twenty-fifth connection electrode 425 is connected to the second region of the twenty-first active layer through a fifth-twelfth via V52 on the one hand, and connected to the first end of the thirteenth connection line 313 through an eighth-fifteenth via V85 on the other hand, and the twenty-fifth connection electrode 425 may serve as a second pole of the twenty-first transistor T21. Since the thirteenth connection line 313 serves as a low voltage connection line, the connection of the second pole of the twenty-first transistor T21 with the low voltage power supply line is achieved.

In an exemplary embodiment, the twenty-sixth connection electrode 426 is connected to the first region of the fifteenth active layer through a thirty-ninth via V39 on the one hand, and to the sixteenth gate electrode line 216 through a sixteenth via V63 on the other hand, and the twenty-sixth connection electrode 426 may serve as a first pole of the fifteenth transistor T15. Since the sixteenth gate electrode line 216 serves as the gate electrode of the sixteenth transistor T16, the interconnection between the first electrode of the fifteenth transistor T15 and the gate electrode of the sixteenth transistor T16 is accomplished.

In an exemplary embodiment, the twenty-seventh connection electrode 427 is connected to the second region of the fifteenth active layer through a forty-fourth via V40 on the one hand and the thirteenth connection line 313 through an eighty-sixteenth via V86 on the other hand, and the twenty-seventh connection electrode 427 may serve as a second pole of the fifteenth transistor T15. Since the thirteenth connection line 313 serves as a low voltage connection line, the connection of the second pole of the fifteenth transistor T15 with the low voltage power supply line is achieved. In an exemplary embodiment, the twenty-seventh connection electrode 427 in the nth-stage GOA circuit and the (n +1) th-stage GOA circuit may be an integral structure that is connected to each other.

In an exemplary embodiment, the twenty-eighth connecting electrode 428 is connected to the first region of the sixteenth active layer through the fourth eleventh via V41, on the one hand, and to the fifteenth gate electrode line 215 through the sixteenth via V64, on the other hand, and the twenty-eighth connecting electrode 428 may serve as a first electrode of the sixteenth transistor T16. Since the fifteenth gate electrode line 215 serves as the gate electrode of the fifteenth transistor T15, the interconnection between the first electrode of the sixteenth transistor T16 and the gate electrode of the fifteenth transistor T15 is achieved.

In an exemplary embodiment, the twenty-ninth connection electrode 429 is connected to the second region of the sixteenth active layer through the forty-second via V42 on the one hand and the thirteenth connection line 313 through the eighty-seventeenth via V87 on the other hand, and the twenty-ninth connection electrode 429 may serve as a second pole of the sixteenth transistor T16. Since the thirteenth connection line 313 serves as a low voltage connection line, the connection of the second pole of the sixteenth transistor T16 with the low voltage power supply line is achieved. In an exemplary embodiment, the twenty-ninth connection electrode 429 in the nth-stage GOA circuit and the (n +1) th-stage GOA circuit may be an integral structure that is connected to each other.

In an exemplary embodiment, the thirtieth connection electrode 430 is connected to the sixteenth gate electrode line 216 through the sixteenth via V62 on the one hand, and is connected to the fourteenth connection line 314 through the eightieth via V88 on the other hand, the thirtieth connection electrode 430 may serve as a connection electrode between the sixteenth gate electrode line 216 and the fourteenth connection line 314, and since the sixteenth gate electrode line 216 may serve as a gate electrode of the sixteenth transistor T16 and the fourteenth connection line 314 may serve as a pull-up node line (PU), connection between the gate electrode of the sixteenth transistor T16 and the pull-up node line (PU) is achieved.

In an exemplary embodiment, the thirty-first connection electrode 431 is connected to the twelfth connection line 312 through an eighty-fourteen via V84 on the one hand, and to the eighteenth gate electrode line 218 through a sixty-fifteenth via V65 on the other hand, and the thirty-first connection electrode 431 may serve as a connection electrode between the twelfth connection line 312 and the eighteenth gate electrode line 218. Since the eighteenth gate electrode line 218 may serve as a gate electrode of the eighteenth transistor T18 and the twelfth connection line 312 may serve as an output connection line to be connected to the present-stage output signal line, the connection of the gate electrode of the eighteenth transistor T18 to the present-stage output signal line is achieved.

In an exemplary embodiment, the thirty-second connecting electrode 432 is connected to the eighteenth gate electrode line 218 through a sixteenth via V66 on the one hand and to the first end of the seventeenth connecting line 317 through a ninety via V90 on the other hand, and the thirty-second connecting electrode 432 may serve as a connecting electrode between the eighteenth gate electrode line 218 and the seventeenth connecting line 317. Since the eighteenth gate electrode line 218 is connected to the twelfth connection line 312, a connection between the twelfth connection line 312 and the seventeenth connection line 317 is achieved.

In an exemplary embodiment, the thirty-third connecting electrode 433 is connected to the first region of the eighteenth active layer through a forty-fifth via V45 on the one hand, and connected to the fourteenth gate electrode line 214 through a sixteenth nineteenth via V69 on the other hand, and the thirty-third connecting electrode 433 may serve as a first electrode of the eighteenth transistor T18. Since the fourteenth gate electrode line 214 serves as the gate electrode of the fourteenth transistor T14, the interconnection between the first pole of the eighteenth transistor T18 and the gate electrode of the fourteenth transistor T14 is accomplished.

In an exemplary embodiment, the thirty-fourth connection electrode 434 is connected to the second region of the eighteenth active layer through a forty-sixth via V46 on the one hand, and is connected to the thirteenth connection line 313 through an eighty-seventeenth via V87 on the other hand, and the thirty-fourth connection electrode 434 may serve as a second pole of the eighteenth transistor T18. Since the thirteenth connection line 313 serves as a low voltage connection line, the connection of the second pole of the eighteenth transistor T18 with the low voltage power supply line is accomplished. In an exemplary embodiment, the thirty-fourth connection electrode 434 in the nth-stage GOA circuit and the n +1 th-stage GOA circuit may be an integral structure connected to each other.

In an exemplary embodiment, an orthogonal projection of the thirty-fourth connection electrode 434 on the substrate at least partially overlaps an orthogonal projection of the fourteenth gate electrode line 214 on the substrate, and since the thirty-fourth connection electrode 434 has a potential of a low voltage power supply line and the fourteenth gate electrode line 214 has a potential of a pull-down node line (PD), a second capacitance (C2) may be formed between the fourteenth gate electrode line 214 and the thirty-fourth connection electrode 434.

In an exemplary embodiment, the thirty-fifth connecting electrode 435 is connected to the second region of the seventeenth active layer through a forty-fourth via V44 on the one hand, and connected to the fourteenth gate electrode line 214 through a sixteenth eighteenth via V68 on the other hand, and the thirty-fifth connecting electrode 435 may serve as a second pole of the seventeenth transistor T17. Since the fourteenth gate electrode line 214 serves as the gate electrode of the fourteenth transistor T14, the interconnection between the second pole of the seventeenth transistor T17 and the gate electrode of the fourteenth transistor T14 is accomplished.

In an exemplary embodiment, the plurality of thirty-sixth connection electrodes 436 may serve as the first pole of the fourteenth transistor T14. As for the thirty-sixth connection electrode 436 near one side of the seventeenth transistor T17, the thirty-sixth connection electrode 436 is connected to the second end of the seventeenth connection line 317 through a ninth eleventh via V91, to the fifteenth connection line 315 through a ninth twelfth via V92, and to the first region of the fourteenth active layer through a seventeenth via V37. As for the thirty-sixth connection electrode 436 near the twentieth transistor T20, the thirty-sixth connection electrode 436 is connected to the first end of the sixteenth connection line 316 through a nineteenth through hole V94, to the fifteenth connection line 315 through a nineteenth through hole V93, to the first region of the fourteenth active layer through a seventeenth through hole V37, and to the first scan signal line 21 of the pixel circuit region through a seventeenth through hole V78. As for the other thirty-sixth connection electrodes 436 other than the two thirty-sixth connection electrodes 436, the other thirty-sixth connection electrodes 436 are connected to the first region of the fourteenth active layer through the thirty-seventh via hole V37 on the one hand, and are connected to the fifteenth connection line 315 through the ninth twelfth via hole V92 and the ninety-third via hole V93, respectively, on the other hand. In this way, the fifteenth connection line 315, the sixteenth connection line 316, and the seventeenth connection line 317 are interconnected by the plurality of thirty-sixth connection electrodes 436, and the present-stage output signal line (the first scanning signal line 21) is connected.

In an exemplary embodiment, the thirty-seventh connecting electrode 437 may be connected to the first region of the twentieth active layer through a forty-ninth via V49 on the one hand, and connected to the second end of the fourteenth gate electrode line 214 through a seventh twelfth via V72 on the other hand, and the thirty-seventh connecting electrode 437 may serve as a first electrode of the twentieth transistor T20. Since the fourteenth gate electrode line 214 serves as the gate electrode of the fourteenth transistor T14, the interconnection between the first electrode of the twentieth transistor T20 and the gate electrode of the fourteenth transistor T14 is accomplished.

In an exemplary embodiment, the thirty-eighth connecting electrode 438 is connected to the second region of the twentieth active layer through a fifty-fifth via V50 on the one hand, and is connected to the thirteenth connecting line 313 through a plurality of eighty-seventh vias V87 on the other hand, and the thirty-eighth connecting electrode 438 may serve as a second pole of the twentieth transistor T20. Since the thirteenth connection line 313 serves as a low voltage connection line, the connection of the second pole of the twentieth transistor T20 with the low voltage power supply line is achieved. In an exemplary embodiment, the thirty-eighth connecting electrode 438 in the nth stage GOA circuit and the n +1 th stage GOA circuit may be an integral structure connected to each other.

In an exemplary embodiment, the thirty-ninth connecting electrode 439 may be connected to the second region of the nineteenth active layer through a forty-eighth via V48 on the one hand, and connected to the sixteenth connecting line 316 through a ninety-fifth via V95 on the other hand, and the thirty-ninth connecting electrode 439 may serve as a second pole of the nineteenth transistor T19. Since the sixteenth connection line 316 serves as the output signal line of the present stage, the connection of the second pole of the nineteenth transistor T19 to the output line of the present stage is achieved.

In an exemplary embodiment, the plurality of fortieth connection electrodes 440 may serve as the second pole of the fourteenth transistor T14. As for the forty-fourth connection electrode 440 near the twentieth transistor T20, it is connected to the first end of the third connection line 243 through the seventy-fourth via V74, to the second connection line 242 through the seventy-eleventh via V71, and to the second region of the fourteenth active layer through the thirty-eighteenth via V38. As for the other fortieth connection electrodes 440, on the one hand, the second region of the fourteenth active layer is connected through the thirty-eighth via V38, and on the other hand, the second connection lines 242 are respectively connected through the seventy via V70 and the seventy-first via V71, respectively. Since the third connection line 243 is a low voltage connection line and the second connection line 242 connected to the third connection line 243 is also a low voltage connection line, the second poles of the fourteenth transistors T14 are all connected to the low voltage power supply line.

In an exemplary embodiment, the forty-first connection electrode 441 may serve as a connection line between the fourteenth connection line 314 and the third plate 233. The forty-fourth connecting electrode 441 is connected to the second end of the third plate 233 through a seventy-sixteenth via V76, and to the fourteenth connecting line 314 through an eighty-nineteenth via V89. Since the fourteenth connection line 314 may serve as a pull-up node line (PU), the third plate 233 has a potential of a pull-up node. Since the fourth plate 324 is connected to the sixteenth connecting line 316 and the sixteenth connecting line 316 is connected to the output signal line of the current stage, the fourth plate 324 has the potential of the output signal line of the current stage, and the third plate 233 and the fourth plate 324 form the first capacitor C1.

In an exemplary embodiment, each stage of the GOA circuit may include a first output electrode 451, an nth stage second output electrode 452, and a third output electrode 453 as an output terminal of the output transistor, each output electrode (a second pole of the output transistor) may include a first section and a second section connected to each other, the first section may be in a "C" shape, the first section may be connected to the second region of the output active layer through a thirty-sixth via V36 of east, the second section may be in an "I" shape, a first end of the second section is connected to the first section, and a second end of the second section may extend to the pixel circuit region in the second direction Y or in the opposite direction of the second direction Y and is connected to the first scan signal line 21 through a seventeenth via V77.

In an exemplary embodiment, the nth stage GOA circuit may include an nth stage first output electrode 451n, an nth stage second output electrode 452n, and an nth stage third output electrode 453 n. The nth stage first output electrode 451n is connected to the second region of the first output active layer through a sixteenth via V36, on the one hand, and to the first scan signal line 21 of the nth cell row through a seventeenth via V77, on the other hand, and the nth stage first output electrode 451n serves as an output terminal of the first output transistor T13A. The nth stage second output electrode 452n is connected to the second region of the second output active layer through a sixteenth via V36, and is connected to the first scan signal line 21 of the nth cell row through a seventeenth via V77, and the nth stage second output electrode 452n serves as an output terminal of the second output transistor T13B. The nth-stage third output electrode 453n is connected to the second region of the third output active layer through a sixteenth via V36 and to the first scan signal line 21 of the nth cell row through a seventeenth via V77, and the nth-stage third output electrode 453n serves as an output terminal of the third output transistor T13C.

In an exemplary embodiment, the thirteenth gate electrode line 213, the first output active layer 113A, the first clock first lead 501, and the nth stage first output electrode 451n may constitute the first output transistor T13A of the nth stage GOA circuit, the thirteenth gate electrode line 213, the second output active layer 113B, the first clock second lead 502, and the nth stage second output electrode 452n may constitute the second output transistor T13B of the nth stage GOA circuit, and the thirteenth gate electrode line 213, the third output active layer 113C, the first clock third lead 503, and the nth stage third output electrode 453n may constitute the third output transistor T13C of the nth stage GOA circuit. The first output transistor T13A, the second output transistor T13B, and the third output transistor T13C of the nth stage GOA circuit may be sequentially disposed along the first direction X and are all connected to the first scanning signal line 21 of the nth cell row, so that the three output transistors commonly output a scanning signal, and the first scanning signal line 21 of the nth cell row serves as an output connection line of the nth stage GOA circuit.

In an exemplary embodiment, the (n +1) th GOA circuit may include an (n +1) th first output electrode 451n +1, an (n +1) th second output electrode 452n +1, and an (n +1) th third output electrode 453n + 1. The (n +1) th-stage first output electrode 451n +1 is connected to the second region of the first output active layer through a sixteenth via V36, and is connected to the first scan signal line 21 of the (n +1) th cell row through a seventeenth via V77. The (n +1) th-stage second output electrode 452n +1 is connected to the second region of the second output active layer through a sixteenth via V36, and is connected to the first scan signal line 21 of the (n +1) th cell row through a seventeenth via V77. The (n +1) th-stage third output electrode 453n +1 is connected to the second region of the third output active layer through a sixteenth via V36, and is connected to the first scan signal line 21 of the (n +1) th cell row through a seventeenth via V77.

In an exemplary embodiment, the thirteenth gate electrode line 213, the first output active layer 113A, the second clock first lead 601, and the n +1 th-stage first output electrode 451n +1 constitute the first output transistor T13A of the n +1 th-stage GOA circuit, the thirteenth gate electrode line 213, the second output active layer 113B, the second clock second lead 602, and the n +1 th-stage second output electrode 452n +1 constitute the second output transistor T13B of the n +1 th-stage GOA circuit, and the thirteenth gate electrode line 213, the third output active layer 113C, the second clock third lead 603, and the n +1 th-stage third output electrode 453n +1 constitute the third output transistor T13C of the n +1 th-stage GOA circuit. The first output transistor T13A, the second output transistor T13B, and the third output transistor T13C of the (n +1) th stage GOA circuit may be sequentially disposed along the first direction X, and are all connected to the first scanning signal line 21 of the (n +1) th cell row, so that the three output transistors commonly output a scanning signal, and the first scanning signal line 21 of the (n +1) th cell row serves as an output connection line of the (n +1) th stage GOA circuit.

In an exemplary embodiment, since the first scan signal line 21 as an output connection line is connected to the thirty-sixth connection electrode 436 through a via, the thirty-sixth connection electrode 436 is connected to the sixteenth connection line 316 through a via, and the sixteenth connection line 316 is connected to the fourth electrode plate 324, the connection between the output line of the present stage of the GOA circuit and the first capacitor is achieved.

The subsequent preparation process may include processes of forming a planarization layer, an anode conductive layer, a pixel defining layer, an organic light emitting layer, a cathode, and an encapsulation structure layer, which are not described herein again.

In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass, quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. The first conductive layer, the second conductive layer, and the third conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, and the like. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer is referred to as a Buffer (Buffer) layer for improving the water and oxygen resistance of the substrate, the second and third insulating layers are referred to as Gate Insulating (GI) layers, and the fourth insulating layer is referred to as an interlayer Insulating (ILD) layer. The active layer may be made of amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), Indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, polythiophene, or the like, that is, the present disclosure is applicable to a transistor manufactured based on an Oxide (Oxide) technology, a silicon technology, or an organic technology.

As can be seen from the structure and the preparation process of the display substrate described above, the display substrate provided by the present disclosure effectively reduces the frame width of the display device and realizes the narrow frame of the display device by alternately arranging the pixel circuit region and the gate circuit region in the display region, the pixel circuit region being provided with the pixel driving circuit, and the gate circuit region being provided with the gate driving circuit. The output requirement of a single output transistor can be reduced, and the output capacity of the whole grid drive circuit can be improved. According to the display device, the plurality of clock signal lines are longitudinally distributed, the plurality of clock signal lines extend along the direction parallel to the data signal lines, and the plurality of clock signal lines are not connected with one another through the transverse connecting lines, so that the overlapping of the clock signal lines and the data signal lines is avoided, the noise of the data signal lines is eliminated, the overall load of the clock signal lines is reduced, and the display quality is improved to the maximum extent. This is disclosed through set up 2 grades of gate drive circuit in gate circuit area, set up 2 unit rows in pixel circuit area, and the pixel drive circuit mirror symmetry in 2 unit rows, simultaneously through the output electrode that sets up a plurality of output transistor and pixel drive circuit's first scanning signal line connection, utilize pixel drive circuit's first scanning signal line as gate drive circuit's output connecting wire, 2 unit row 2 grades of gate drive circuit structure overall arrangement that form is reasonable, connection structure is simple, pixel drive circuit and gate drive circuit's occupation space is little, be favorable to realizing high PPI and show. The preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.

The structure and the manufacturing process thereof shown in the foregoing are merely exemplary illustrations, and in an exemplary embodiment, the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs, and the disclosure is not limited herein.

The exemplary embodiment of the present disclosure also provides a method for manufacturing a display substrate, so as to manufacture the display substrate provided by the above exemplary embodiment. In an exemplary embodiment, the display substrate includes a plurality of pixel circuit regions and a plurality of gate circuit regions alternately arranged along a second direction; the preparation method can comprise the following steps:

The exemplary embodiment of the present disclosure also provides a display device, which includes the aforementioned display substrate. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator, etc., but the embodiment of the present invention is not limited thereto.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. A display substrate is characterized by comprising a plurality of pixel circuit areas and a plurality of grid circuit areas which are alternately arranged along a second direction, wherein at least one pixel circuit area comprises at least one unit row, the unit row comprises a plurality of circuit units which are sequentially arranged along a first direction, at least one circuit unit comprises a pixel driving circuit, a data signal line and a scanning signal line, the data signal line and the scanning signal line are connected with the pixel driving circuit, at least one grid circuit area comprises at least one stage of grid driving circuit, the grid driving circuit comprises at least one output transistor and a clock signal line, the clock signal line is connected with the output transistor, the orthographic projection of the data signal line on the plane of the display substrate is not overlapped with the orthographic projection of the clock signal line on the plane of the display substrate, and the first direction and the second direction are crossed.

2. The display substrate according to claim 1, wherein in at least one gate circuit region, the gate driving circuit comprises a plurality of transistors and a plurality of clock signal lines connected to the plurality of transistors, and orthographic projections of the plurality of clock signal lines on a display substrate plane do not overlap and are not connected to each other.

3. The display substrate according to claim 1, wherein at least one pixel circuit region includes k unit rows sequentially arranged along the second direction, and at least one gate circuit region includes k gate driving circuits sequentially arranged along the second direction, and k is a positive integer greater than or equal to 2.

4. The display substrate according to claim 1, wherein at least one gate circuit region includes an nth-stage gate driver circuit and an n + 1-stage gate driver circuit, which are sequentially arranged along the second direction, the pixel circuit region on a side of the nth-stage gate driver circuit away from the n + 1-stage gate driver circuit includes at least an nth cell row, the pixel circuit region on a side of the n + 1-stage gate driver circuit away from the nth-stage gate driver circuit includes at least an n +1 th cell row, the nth-stage gate driver circuit is configured to drive the pixel driver circuit of the nth cell row, the n + 1-stage gate driver circuit is configured to drive the pixel driver circuit of the n +1 th cell row, and n is a positive integer greater than or equal to 1.

5. The display substrate according to claim 4, wherein the pixel driving circuits in the n-th cell row and the pixel driving circuits in the n + 1-th cell row are mirror-symmetric with respect to a first reference line, which is a straight line bisecting the gate circuit regions in the second direction and extending along the first direction.

6. The display substrate according to claim 1, wherein the at least one pixel circuit region includes an m-th cell row and an m + 1-th cell row which are sequentially arranged along the second direction, the gate circuit region on a side of the m-th cell row away from the m + 1-th cell row includes at least an m-th stage gate driving circuit, the gate circuit region on a side of the m + 1-th cell row away from the m-th cell row includes at least an m + 1-th stage gate driving circuit, the m-th stage gate driving circuit is configured to drive the pixel driving circuit of the m-th cell row, the m + 1-th stage gate driving circuit is configured to drive the pixel driving circuit of the m + 1-th cell row, and m is a positive integer greater than or equal to 2.

7. The display substrate according to claim 6, wherein the pixel driving circuits in the m-th cell row and the pixel driving circuits in the m + 1-th cell row are mirror-symmetric with respect to a second reference line, which is a straight line bisecting the pixel circuit regions in a second direction and extending along the first direction.

8. The display substrate according to any one of claims 1 to 7, wherein at least one of the gate driving circuits comprises a first output transistor group, a second output transistor group and a third output transistor group arranged in this order along the first direction, the first output transistor group is connected to a first lead of the input clock signal, the second output transistor group is connected to a second lead of the input clock signal, the third output transistor group is connected to a third lead of the input clock signal, and orthographic projections of the first, second and third leads on a plane of the display substrate do not overlap and are not connected to each other.

9. The display substrate according to claim 8, wherein the first output transistor group comprises two first output transistors, the two first output transistors being mirror-symmetric with respect to the first lead; the second output transistor group comprises two second output transistors, and the two second output transistors are in mirror symmetry relative to the second lead; the third output transistor group includes two third output transistors that are mirror-symmetric with respect to the third lead.

10. The display substrate according to claim 9, wherein the first output transistor, the second output transistor, and the third output transistor are identical in structure and size.

11. The display substrate according to claim 8, wherein the at least one gate circuit region includes an nth-stage gate driving circuit and an n + 1-stage gate driving circuit sequentially arranged along the second direction; in the nth stage gate driving circuit, an input end of a first output transistor group is connected with a first clock first lead for inputting a first clock signal, an input end of a second output transistor group is connected with a first clock second lead for inputting the first clock signal, and an input end of a third output transistor group is connected with a first clock third lead for inputting the first clock signal; in the (n +1) -th stage gate driving circuit, an input end of a first output transistor group is connected with a first lead of a second clock to which a second clock signal is input, an input end of a second output transistor group is connected with a second lead of the second clock to which the second clock signal is input, and an input end of a third output transistor group is connected with a third lead of the second clock to which the second clock signal is input.

12. The display substrate according to claim 11, wherein the first output transistor group of the n +1 th stage gate driver circuit is disposed on one side of the first direction of the first output transistor group of the n-th stage gate driver circuit, the second output transistor group of the nth stage gate driving circuit is disposed on one side of the first output transistor group of the (n +1) th stage gate driving circuit in the first direction, the second output transistor group of the (n +1) th stage gate drive circuit is disposed on one side of the second output transistor group of the nth stage gate drive circuit in the first direction, the third output transistor group of the nth stage gate driving circuit is disposed on one side of the second output transistor group of the (n +1) th stage gate driving circuit in the first direction, the third output transistor group of the (n +1) th stage gate drive circuit is arranged on one side of the third output transistor group of the nth stage gate drive circuit in the first direction.

13. The display substrate according to claim 11, wherein in the nth stage gate driver circuit, output terminals of the first, second, and third output transistor groups are connected to a scanning signal line of an nth cell row in the pixel circuit region; in the (n +1) th stage gate drive circuit, the output ends of the first output transistor group, the second output transistor group and the third output transistor group are all connected with the scanning signal line of the (n +1) th unit row in the pixel circuit region.

14. The display substrate according to any one of claims 1 to 7, wherein the display substrate comprises a plurality of conductive layers sequentially disposed on a base in a plane perpendicular to the display substrate, and the data signal line and the clock signal line are disposed in the same layer.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

16. The preparation method of the display substrate is characterized in that the display substrate comprises a plurality of pixel circuit areas and a plurality of grid circuit areas which are alternately arranged along a second direction; the preparation method comprises the following steps: